455 lines
9.8 KiB
C
455 lines
9.8 KiB
C
/*
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Legend Silicon LGS-8GL5 DMB-TH OFDM demodulator driver
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Copyright (C) 2008 Sirius International (Hong Kong) Limited
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Timothy Lee <timothy.lee@siriushk.com>
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/string.h>
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#include <linux/slab.h>
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#include "dvb_frontend.h"
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#include "lgs8gl5.h"
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#define REG_RESET 0x02
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#define REG_RESET_OFF 0x01
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#define REG_03 0x03
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#define REG_04 0x04
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#define REG_07 0x07
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#define REG_09 0x09
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#define REG_0A 0x0a
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#define REG_0B 0x0b
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#define REG_0C 0x0c
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#define REG_37 0x37
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#define REG_STRENGTH 0x4b
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#define REG_STRENGTH_MASK 0x7f
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#define REG_STRENGTH_CARRIER 0x80
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#define REG_INVERSION 0x7c
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#define REG_INVERSION_ON 0x80
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#define REG_7D 0x7d
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#define REG_7E 0x7e
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#define REG_A2 0xa2
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#define REG_STATUS 0xa4
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#define REG_STATUS_SYNC 0x04
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#define REG_STATUS_LOCK 0x01
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struct lgs8gl5_state {
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struct i2c_adapter *i2c;
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const struct lgs8gl5_config *config;
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struct dvb_frontend frontend;
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};
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static int debug;
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#define dprintk(args...) \
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do { \
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if (debug) \
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printk(KERN_DEBUG "lgs8gl5: " args); \
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} while (0)
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/* Writes into demod's register */
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static int
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lgs8gl5_write_reg(struct lgs8gl5_state *state, u8 reg, u8 data)
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{
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int ret;
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u8 buf[] = {reg, data};
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struct i2c_msg msg = {
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.addr = state->config->demod_address,
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.flags = 0,
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.buf = buf,
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.len = 2
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};
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ret = i2c_transfer(state->i2c, &msg, 1);
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if (ret != 1)
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dprintk("%s: error (reg=0x%02x, val=0x%02x, ret=%i)\n",
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__func__, reg, data, ret);
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return (ret != 1) ? -1 : 0;
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}
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/* Reads from demod's register */
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static int
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lgs8gl5_read_reg(struct lgs8gl5_state *state, u8 reg)
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{
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int ret;
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u8 b0[] = {reg};
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u8 b1[] = {0};
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struct i2c_msg msg[2] = {
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{
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.addr = state->config->demod_address,
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.flags = 0,
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.buf = b0,
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.len = 1
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},
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{
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.addr = state->config->demod_address,
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.flags = I2C_M_RD,
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.buf = b1,
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.len = 1
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}
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};
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ret = i2c_transfer(state->i2c, msg, 2);
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if (ret != 2)
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return -EIO;
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return b1[0];
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}
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static int
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lgs8gl5_update_reg(struct lgs8gl5_state *state, u8 reg, u8 data)
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{
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lgs8gl5_read_reg(state, reg);
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lgs8gl5_write_reg(state, reg, data);
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return 0;
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}
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/* Writes into alternate device's register */
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/* TODO: Find out what that device is for! */
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static int
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lgs8gl5_update_alt_reg(struct lgs8gl5_state *state, u8 reg, u8 data)
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{
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int ret;
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u8 b0[] = {reg};
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u8 b1[] = {0};
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u8 b2[] = {reg, data};
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struct i2c_msg msg[3] = {
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{
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.addr = state->config->demod_address + 2,
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.flags = 0,
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.buf = b0,
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.len = 1
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},
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{
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.addr = state->config->demod_address + 2,
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.flags = I2C_M_RD,
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.buf = b1,
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.len = 1
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},
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{
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.addr = state->config->demod_address + 2,
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.flags = 0,
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.buf = b2,
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.len = 2
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},
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};
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ret = i2c_transfer(state->i2c, msg, 3);
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return (ret != 3) ? -1 : 0;
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}
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static void
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lgs8gl5_soft_reset(struct lgs8gl5_state *state)
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{
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u8 val;
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dprintk("%s\n", __func__);
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val = lgs8gl5_read_reg(state, REG_RESET);
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lgs8gl5_write_reg(state, REG_RESET, val & ~REG_RESET_OFF);
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lgs8gl5_write_reg(state, REG_RESET, val | REG_RESET_OFF);
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msleep(5);
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}
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/* Starts demodulation */
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static void
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lgs8gl5_start_demod(struct lgs8gl5_state *state)
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{
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u8 val;
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int n;
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dprintk("%s\n", __func__);
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lgs8gl5_update_alt_reg(state, 0xc2, 0x28);
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lgs8gl5_soft_reset(state);
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lgs8gl5_update_reg(state, REG_07, 0x10);
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lgs8gl5_update_reg(state, REG_07, 0x10);
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lgs8gl5_write_reg(state, REG_09, 0x0e);
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lgs8gl5_write_reg(state, REG_0A, 0xe5);
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lgs8gl5_write_reg(state, REG_0B, 0x35);
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lgs8gl5_write_reg(state, REG_0C, 0x30);
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lgs8gl5_update_reg(state, REG_03, 0x00);
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lgs8gl5_update_reg(state, REG_7E, 0x01);
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lgs8gl5_update_alt_reg(state, 0xc5, 0x00);
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lgs8gl5_update_reg(state, REG_04, 0x02);
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lgs8gl5_update_reg(state, REG_37, 0x01);
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lgs8gl5_soft_reset(state);
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/* Wait for carrier */
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for (n = 0; n < 10; n++) {
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val = lgs8gl5_read_reg(state, REG_STRENGTH);
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dprintk("Wait for carrier[%d] 0x%02X\n", n, val);
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if (val & REG_STRENGTH_CARRIER)
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break;
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msleep(4);
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}
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if (!(val & REG_STRENGTH_CARRIER))
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return;
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/* Wait for lock */
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for (n = 0; n < 20; n++) {
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val = lgs8gl5_read_reg(state, REG_STATUS);
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dprintk("Wait for lock[%d] 0x%02X\n", n, val);
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if (val & REG_STATUS_LOCK)
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break;
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msleep(12);
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}
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if (!(val & REG_STATUS_LOCK))
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return;
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lgs8gl5_write_reg(state, REG_7D, lgs8gl5_read_reg(state, REG_A2));
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lgs8gl5_soft_reset(state);
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}
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static int
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lgs8gl5_init(struct dvb_frontend *fe)
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{
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struct lgs8gl5_state *state = fe->demodulator_priv;
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dprintk("%s\n", __func__);
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lgs8gl5_update_alt_reg(state, 0xc2, 0x28);
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lgs8gl5_soft_reset(state);
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lgs8gl5_update_reg(state, REG_07, 0x10);
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lgs8gl5_update_reg(state, REG_07, 0x10);
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lgs8gl5_write_reg(state, REG_09, 0x0e);
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lgs8gl5_write_reg(state, REG_0A, 0xe5);
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lgs8gl5_write_reg(state, REG_0B, 0x35);
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lgs8gl5_write_reg(state, REG_0C, 0x30);
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return 0;
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}
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static int
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lgs8gl5_read_status(struct dvb_frontend *fe, enum fe_status *status)
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{
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struct lgs8gl5_state *state = fe->demodulator_priv;
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u8 level = lgs8gl5_read_reg(state, REG_STRENGTH);
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u8 flags = lgs8gl5_read_reg(state, REG_STATUS);
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*status = 0;
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if ((level & REG_STRENGTH_MASK) > 0)
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*status |= FE_HAS_SIGNAL;
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if (level & REG_STRENGTH_CARRIER)
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*status |= FE_HAS_CARRIER;
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if (flags & REG_STATUS_SYNC)
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*status |= FE_HAS_SYNC;
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if (flags & REG_STATUS_LOCK)
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*status |= FE_HAS_LOCK;
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return 0;
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}
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static int
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lgs8gl5_read_ber(struct dvb_frontend *fe, u32 *ber)
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{
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*ber = 0;
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return 0;
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}
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static int
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lgs8gl5_read_signal_strength(struct dvb_frontend *fe, u16 *signal_strength)
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{
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struct lgs8gl5_state *state = fe->demodulator_priv;
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u8 level = lgs8gl5_read_reg(state, REG_STRENGTH);
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*signal_strength = (level & REG_STRENGTH_MASK) << 8;
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return 0;
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}
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static int
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lgs8gl5_read_snr(struct dvb_frontend *fe, u16 *snr)
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{
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struct lgs8gl5_state *state = fe->demodulator_priv;
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u8 level = lgs8gl5_read_reg(state, REG_STRENGTH);
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*snr = (level & REG_STRENGTH_MASK) << 8;
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return 0;
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}
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static int
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lgs8gl5_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
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{
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*ucblocks = 0;
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return 0;
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}
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static int
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lgs8gl5_set_frontend(struct dvb_frontend *fe)
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{
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struct dtv_frontend_properties *p = &fe->dtv_property_cache;
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struct lgs8gl5_state *state = fe->demodulator_priv;
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dprintk("%s\n", __func__);
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if (p->bandwidth_hz != 8000000)
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return -EINVAL;
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if (fe->ops.tuner_ops.set_params) {
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fe->ops.tuner_ops.set_params(fe);
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if (fe->ops.i2c_gate_ctrl)
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fe->ops.i2c_gate_ctrl(fe, 0);
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}
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/* lgs8gl5_set_inversion(state, p->inversion); */
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lgs8gl5_start_demod(state);
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return 0;
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}
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static int
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lgs8gl5_get_frontend(struct dvb_frontend *fe,
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struct dtv_frontend_properties *p)
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{
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struct lgs8gl5_state *state = fe->demodulator_priv;
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u8 inv = lgs8gl5_read_reg(state, REG_INVERSION);
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p->inversion = (inv & REG_INVERSION_ON) ? INVERSION_ON : INVERSION_OFF;
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p->code_rate_HP = FEC_1_2;
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p->code_rate_LP = FEC_7_8;
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p->guard_interval = GUARD_INTERVAL_1_32;
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p->transmission_mode = TRANSMISSION_MODE_2K;
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p->modulation = QAM_64;
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p->hierarchy = HIERARCHY_NONE;
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p->bandwidth_hz = 8000000;
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return 0;
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}
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static int
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lgs8gl5_get_tune_settings(struct dvb_frontend *fe,
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struct dvb_frontend_tune_settings *fesettings)
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{
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fesettings->min_delay_ms = 240;
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fesettings->step_size = 0;
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fesettings->max_drift = 0;
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return 0;
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}
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static void
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lgs8gl5_release(struct dvb_frontend *fe)
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{
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struct lgs8gl5_state *state = fe->demodulator_priv;
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kfree(state);
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}
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static struct dvb_frontend_ops lgs8gl5_ops;
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struct dvb_frontend*
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lgs8gl5_attach(const struct lgs8gl5_config *config, struct i2c_adapter *i2c)
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{
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struct lgs8gl5_state *state = NULL;
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dprintk("%s\n", __func__);
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/* Allocate memory for the internal state */
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state = kzalloc(sizeof(struct lgs8gl5_state), GFP_KERNEL);
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if (state == NULL)
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goto error;
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/* Setup the state */
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state->config = config;
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state->i2c = i2c;
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/* Check if the demod is there */
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if (lgs8gl5_read_reg(state, REG_RESET) < 0)
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goto error;
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/* Create dvb_frontend */
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memcpy(&state->frontend.ops, &lgs8gl5_ops,
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sizeof(struct dvb_frontend_ops));
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state->frontend.demodulator_priv = state;
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return &state->frontend;
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error:
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kfree(state);
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return NULL;
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}
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EXPORT_SYMBOL(lgs8gl5_attach);
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static struct dvb_frontend_ops lgs8gl5_ops = {
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.delsys = { SYS_DTMB },
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.info = {
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.name = "Legend Silicon LGS-8GL5 DMB-TH",
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.frequency_min = 474000000,
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.frequency_max = 858000000,
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.frequency_stepsize = 10000,
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.frequency_tolerance = 0,
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.caps = FE_CAN_FEC_AUTO |
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FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_32 |
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FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
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FE_CAN_TRANSMISSION_MODE_AUTO |
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FE_CAN_BANDWIDTH_AUTO |
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FE_CAN_GUARD_INTERVAL_AUTO |
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FE_CAN_HIERARCHY_AUTO |
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FE_CAN_RECOVER
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},
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.release = lgs8gl5_release,
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.init = lgs8gl5_init,
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.set_frontend = lgs8gl5_set_frontend,
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.get_frontend = lgs8gl5_get_frontend,
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.get_tune_settings = lgs8gl5_get_tune_settings,
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.read_status = lgs8gl5_read_status,
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.read_ber = lgs8gl5_read_ber,
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.read_signal_strength = lgs8gl5_read_signal_strength,
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.read_snr = lgs8gl5_read_snr,
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.read_ucblocks = lgs8gl5_read_ucblocks,
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};
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module_param(debug, int, 0644);
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MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
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MODULE_DESCRIPTION("Legend Silicon LGS-8GL5 DMB-TH Demodulator driver");
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MODULE_AUTHOR("Timothy Lee");
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MODULE_LICENSE("GPL");
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