678 lines
18 KiB
C
678 lines
18 KiB
C
/*
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* Driver for the Conexant CX25821 PCIe bridge
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*
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* Copyright (C) 2009 Conexant Systems Inc.
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* Authors <hiep.huynh@conexant.com>, <shu.lin@conexant.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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*
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include "cx25821-video.h"
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#include "cx25821-video-upstream.h"
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#include <linux/errno.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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MODULE_DESCRIPTION("v4l2 driver module for cx25821 based TV cards");
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MODULE_AUTHOR("Hiep Huynh <hiep.huynh@conexant.com>");
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MODULE_LICENSE("GPL");
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static int _intr_msk = FLD_VID_SRC_RISC1 | FLD_VID_SRC_UF | FLD_VID_SRC_SYNC |
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FLD_VID_SRC_OPC_ERR;
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int cx25821_sram_channel_setup_upstream(struct cx25821_dev *dev,
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const struct sram_channel *ch,
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unsigned int bpl, u32 risc)
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{
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unsigned int i, lines;
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u32 cdt;
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if (ch->cmds_start == 0) {
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cx_write(ch->ptr1_reg, 0);
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cx_write(ch->ptr2_reg, 0);
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cx_write(ch->cnt2_reg, 0);
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cx_write(ch->cnt1_reg, 0);
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return 0;
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}
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bpl = (bpl + 7) & ~7; /* alignment */
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cdt = ch->cdt;
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lines = ch->fifo_size / bpl;
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if (lines > 4)
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lines = 4;
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BUG_ON(lines < 2);
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/* write CDT */
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for (i = 0; i < lines; i++) {
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cx_write(cdt + 16 * i, ch->fifo_start + bpl * i);
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cx_write(cdt + 16 * i + 4, 0);
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cx_write(cdt + 16 * i + 8, 0);
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cx_write(cdt + 16 * i + 12, 0);
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}
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/* write CMDS */
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cx_write(ch->cmds_start + 0, risc);
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cx_write(ch->cmds_start + 4, 0);
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cx_write(ch->cmds_start + 8, cdt);
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cx_write(ch->cmds_start + 12, (lines * 16) >> 3);
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cx_write(ch->cmds_start + 16, ch->ctrl_start);
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cx_write(ch->cmds_start + 20, VID_IQ_SIZE_DW);
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for (i = 24; i < 80; i += 4)
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cx_write(ch->cmds_start + i, 0);
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/* fill registers */
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cx_write(ch->ptr1_reg, ch->fifo_start);
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cx_write(ch->ptr2_reg, cdt);
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cx_write(ch->cnt2_reg, (lines * 16) >> 3);
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cx_write(ch->cnt1_reg, (bpl >> 3) - 1);
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return 0;
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}
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static __le32 *cx25821_update_riscprogram(struct cx25821_channel *chan,
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__le32 *rp, unsigned int offset,
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unsigned int bpl, u32 sync_line,
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unsigned int lines, int fifo_enable,
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int field_type)
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{
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struct cx25821_video_out_data *out = chan->out;
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unsigned int line, i;
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int dist_betwn_starts = bpl * 2;
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*(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
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if (USE_RISC_NOOP_VIDEO) {
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for (i = 0; i < NUM_NO_OPS; i++)
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*(rp++) = cpu_to_le32(RISC_NOOP);
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}
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/* scan lines */
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for (line = 0; line < lines; line++) {
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*(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
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*(rp++) = cpu_to_le32(out->_data_buf_phys_addr + offset);
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*(rp++) = cpu_to_le32(0); /* bits 63-32 */
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if ((lines <= NTSC_FIELD_HEIGHT)
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|| (line < (NTSC_FIELD_HEIGHT - 1)) || !(out->is_60hz)) {
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offset += dist_betwn_starts;
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}
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}
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return rp;
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}
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static __le32 *cx25821_risc_field_upstream(struct cx25821_channel *chan, __le32 *rp,
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dma_addr_t databuf_phys_addr,
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unsigned int offset, u32 sync_line,
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unsigned int bpl, unsigned int lines,
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int fifo_enable, int field_type)
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{
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struct cx25821_video_out_data *out = chan->out;
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unsigned int line, i;
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const struct sram_channel *sram_ch = chan->sram_channels;
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int dist_betwn_starts = bpl * 2;
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/* sync instruction */
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if (sync_line != NO_SYNC_LINE)
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*(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
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if (USE_RISC_NOOP_VIDEO) {
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for (i = 0; i < NUM_NO_OPS; i++)
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*(rp++) = cpu_to_le32(RISC_NOOP);
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}
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/* scan lines */
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for (line = 0; line < lines; line++) {
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*(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
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*(rp++) = cpu_to_le32(databuf_phys_addr + offset);
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*(rp++) = cpu_to_le32(0); /* bits 63-32 */
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if ((lines <= NTSC_FIELD_HEIGHT)
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|| (line < (NTSC_FIELD_HEIGHT - 1)) || !(out->is_60hz))
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/* to skip the other field line */
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offset += dist_betwn_starts;
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/* check if we need to enable the FIFO after the first 4 lines
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* For the upstream video channel, the risc engine will enable
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* the FIFO. */
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if (fifo_enable && line == 3) {
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*(rp++) = cpu_to_le32(RISC_WRITECR);
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*(rp++) = cpu_to_le32(sram_ch->dma_ctl);
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*(rp++) = cpu_to_le32(FLD_VID_FIFO_EN);
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*(rp++) = cpu_to_le32(0x00000001);
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}
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}
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return rp;
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}
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static int cx25821_risc_buffer_upstream(struct cx25821_channel *chan,
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struct pci_dev *pci,
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unsigned int top_offset,
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unsigned int bpl, unsigned int lines)
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{
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struct cx25821_video_out_data *out = chan->out;
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__le32 *rp;
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int fifo_enable = 0;
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/* get line count for single field */
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int singlefield_lines = lines >> 1;
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int odd_num_lines = singlefield_lines;
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int frame = 0;
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int frame_size = 0;
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int databuf_offset = 0;
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int risc_program_size = 0;
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int risc_flag = RISC_CNT_RESET;
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unsigned int bottom_offset = bpl;
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dma_addr_t risc_phys_jump_addr;
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if (out->is_60hz) {
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odd_num_lines = singlefield_lines + 1;
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risc_program_size = FRAME1_VID_PROG_SIZE;
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frame_size = (bpl == Y411_LINE_SZ) ?
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FRAME_SIZE_NTSC_Y411 : FRAME_SIZE_NTSC_Y422;
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} else {
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risc_program_size = PAL_VID_PROG_SIZE;
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frame_size = (bpl == Y411_LINE_SZ) ?
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FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422;
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}
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/* Virtual address of Risc buffer program */
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rp = out->_dma_virt_addr;
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for (frame = 0; frame < NUM_FRAMES; frame++) {
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databuf_offset = frame_size * frame;
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if (UNSET != top_offset) {
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fifo_enable = (frame == 0) ? FIFO_ENABLE : FIFO_DISABLE;
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rp = cx25821_risc_field_upstream(chan, rp,
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out->_data_buf_phys_addr +
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databuf_offset, top_offset, 0, bpl,
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odd_num_lines, fifo_enable, ODD_FIELD);
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}
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fifo_enable = FIFO_DISABLE;
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/* Even Field */
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rp = cx25821_risc_field_upstream(chan, rp,
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out->_data_buf_phys_addr +
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databuf_offset, bottom_offset,
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0x200, bpl, singlefield_lines,
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fifo_enable, EVEN_FIELD);
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if (frame == 0) {
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risc_flag = RISC_CNT_RESET;
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risc_phys_jump_addr = out->_dma_phys_start_addr +
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risc_program_size;
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} else {
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risc_phys_jump_addr = out->_dma_phys_start_addr;
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risc_flag = RISC_CNT_INC;
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}
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/* Loop to 2ndFrameRISC or to Start of Risc
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* program & generate IRQ
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*/
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*(rp++) = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | risc_flag);
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*(rp++) = cpu_to_le32(risc_phys_jump_addr);
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*(rp++) = cpu_to_le32(0);
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}
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return 0;
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}
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void cx25821_stop_upstream_video(struct cx25821_channel *chan)
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{
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struct cx25821_video_out_data *out = chan->out;
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struct cx25821_dev *dev = chan->dev;
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const struct sram_channel *sram_ch = chan->sram_channels;
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u32 tmp = 0;
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if (!out->_is_running) {
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pr_info("No video file is currently running so return!\n");
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return;
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}
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/* Set the interrupt mask register, disable irq. */
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cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) & ~(1 << sram_ch->irq_bit));
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/* Disable RISC interrupts */
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tmp = cx_read(sram_ch->int_msk);
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cx_write(sram_ch->int_msk, tmp & ~_intr_msk);
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/* Turn OFF risc and fifo enable */
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tmp = cx_read(sram_ch->dma_ctl);
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cx_write(sram_ch->dma_ctl, tmp & ~(FLD_VID_FIFO_EN | FLD_VID_RISC_EN));
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free_irq(dev->pci->irq, chan);
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/* Clear data buffer memory */
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if (out->_data_buf_virt_addr)
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memset(out->_data_buf_virt_addr, 0, out->_data_buf_size);
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out->_is_running = 0;
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out->_is_first_frame = 0;
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out->_frame_count = 0;
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out->_file_status = END_OF_FILE;
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tmp = cx_read(VID_CH_MODE_SEL);
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cx_write(VID_CH_MODE_SEL, tmp & 0xFFFFFE00);
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}
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void cx25821_free_mem_upstream(struct cx25821_channel *chan)
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{
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struct cx25821_video_out_data *out = chan->out;
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struct cx25821_dev *dev = chan->dev;
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if (out->_is_running)
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cx25821_stop_upstream_video(chan);
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if (out->_dma_virt_addr) {
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pci_free_consistent(dev->pci, out->_risc_size,
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out->_dma_virt_addr, out->_dma_phys_addr);
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out->_dma_virt_addr = NULL;
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}
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if (out->_data_buf_virt_addr) {
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pci_free_consistent(dev->pci, out->_data_buf_size,
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out->_data_buf_virt_addr,
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out->_data_buf_phys_addr);
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out->_data_buf_virt_addr = NULL;
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}
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}
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int cx25821_write_frame(struct cx25821_channel *chan,
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const char __user *data, size_t count)
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{
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struct cx25821_video_out_data *out = chan->out;
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int line_size = (out->_pixel_format == PIXEL_FRMT_411) ?
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Y411_LINE_SZ : Y422_LINE_SZ;
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int frame_size = 0;
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int frame_offset = 0;
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int curpos = out->curpos;
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if (out->is_60hz)
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frame_size = (line_size == Y411_LINE_SZ) ?
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FRAME_SIZE_NTSC_Y411 : FRAME_SIZE_NTSC_Y422;
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else
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frame_size = (line_size == Y411_LINE_SZ) ?
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FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422;
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if (curpos == 0) {
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out->cur_frame_index = out->_frame_index;
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if (wait_event_interruptible(out->waitq, out->cur_frame_index != out->_frame_index))
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return -EINTR;
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out->cur_frame_index = out->_frame_index;
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}
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frame_offset = out->cur_frame_index ? frame_size : 0;
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if (frame_size - curpos < count)
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count = frame_size - curpos;
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if (copy_from_user((__force char *)out->_data_buf_virt_addr + frame_offset + curpos,
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data, count))
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return -EFAULT;
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curpos += count;
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if (curpos == frame_size) {
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out->_frame_count++;
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curpos = 0;
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}
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out->curpos = curpos;
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return count;
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}
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static int cx25821_upstream_buffer_prepare(struct cx25821_channel *chan,
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const struct sram_channel *sram_ch,
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int bpl)
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{
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struct cx25821_video_out_data *out = chan->out;
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struct cx25821_dev *dev = chan->dev;
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int ret = 0;
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dma_addr_t dma_addr;
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dma_addr_t data_dma_addr;
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if (out->_dma_virt_addr != NULL)
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pci_free_consistent(dev->pci, out->upstream_riscbuf_size,
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out->_dma_virt_addr, out->_dma_phys_addr);
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out->_dma_virt_addr = pci_alloc_consistent(dev->pci,
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out->upstream_riscbuf_size, &dma_addr);
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out->_dma_virt_start_addr = out->_dma_virt_addr;
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out->_dma_phys_start_addr = dma_addr;
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out->_dma_phys_addr = dma_addr;
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out->_risc_size = out->upstream_riscbuf_size;
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if (!out->_dma_virt_addr) {
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pr_err("FAILED to allocate memory for Risc buffer! Returning\n");
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return -ENOMEM;
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}
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/* Clear memory at address */
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memset(out->_dma_virt_addr, 0, out->_risc_size);
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if (out->_data_buf_virt_addr != NULL)
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pci_free_consistent(dev->pci, out->upstream_databuf_size,
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out->_data_buf_virt_addr,
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out->_data_buf_phys_addr);
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/* For Video Data buffer allocation */
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out->_data_buf_virt_addr = pci_alloc_consistent(dev->pci,
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out->upstream_databuf_size, &data_dma_addr);
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out->_data_buf_phys_addr = data_dma_addr;
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out->_data_buf_size = out->upstream_databuf_size;
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if (!out->_data_buf_virt_addr) {
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pr_err("FAILED to allocate memory for data buffer! Returning\n");
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return -ENOMEM;
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}
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/* Clear memory at address */
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memset(out->_data_buf_virt_addr, 0, out->_data_buf_size);
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/* Create RISC programs */
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ret = cx25821_risc_buffer_upstream(chan, dev->pci, 0, bpl,
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out->_lines_count);
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if (ret < 0) {
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pr_info("Failed creating Video Upstream Risc programs!\n");
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goto error;
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}
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return 0;
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error:
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return ret;
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}
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static int cx25821_video_upstream_irq(struct cx25821_channel *chan, u32 status)
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{
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struct cx25821_video_out_data *out = chan->out;
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struct cx25821_dev *dev = chan->dev;
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u32 int_msk_tmp;
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const struct sram_channel *channel = chan->sram_channels;
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int singlefield_lines = NTSC_FIELD_HEIGHT;
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int line_size_in_bytes = Y422_LINE_SZ;
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int odd_risc_prog_size = 0;
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dma_addr_t risc_phys_jump_addr;
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__le32 *rp;
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if (status & FLD_VID_SRC_RISC1) {
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/* We should only process one program per call */
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u32 prog_cnt = cx_read(channel->gpcnt);
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/* Since we've identified our IRQ, clear our bits from the
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* interrupt mask and interrupt status registers */
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int_msk_tmp = cx_read(channel->int_msk);
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cx_write(channel->int_msk, int_msk_tmp & ~_intr_msk);
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cx_write(channel->int_stat, _intr_msk);
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wake_up(&out->waitq);
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spin_lock(&dev->slock);
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out->_frame_index = prog_cnt;
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if (out->_is_first_frame) {
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out->_is_first_frame = 0;
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if (out->is_60hz) {
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singlefield_lines += 1;
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odd_risc_prog_size = ODD_FLD_NTSC_PROG_SIZE;
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} else {
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singlefield_lines = PAL_FIELD_HEIGHT;
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odd_risc_prog_size = ODD_FLD_PAL_PROG_SIZE;
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}
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if (out->_dma_virt_start_addr != NULL) {
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line_size_in_bytes =
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(out->_pixel_format ==
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PIXEL_FRMT_411) ? Y411_LINE_SZ :
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Y422_LINE_SZ;
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risc_phys_jump_addr =
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out->_dma_phys_start_addr +
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odd_risc_prog_size;
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rp = cx25821_update_riscprogram(chan,
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out->_dma_virt_start_addr, TOP_OFFSET,
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line_size_in_bytes, 0x0,
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singlefield_lines, FIFO_DISABLE,
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ODD_FIELD);
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/* Jump to Even Risc program of 1st Frame */
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*(rp++) = cpu_to_le32(RISC_JUMP);
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*(rp++) = cpu_to_le32(risc_phys_jump_addr);
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*(rp++) = cpu_to_le32(0);
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}
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}
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spin_unlock(&dev->slock);
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} else {
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if (status & FLD_VID_SRC_UF)
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pr_err("%s(): Video Received Underflow Error Interrupt!\n",
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__func__);
|
|
|
|
if (status & FLD_VID_SRC_SYNC)
|
|
pr_err("%s(): Video Received Sync Error Interrupt!\n",
|
|
__func__);
|
|
|
|
if (status & FLD_VID_SRC_OPC_ERR)
|
|
pr_err("%s(): Video Received OpCode Error Interrupt!\n",
|
|
__func__);
|
|
}
|
|
|
|
if (out->_file_status == END_OF_FILE) {
|
|
pr_err("EOF Channel 1 Framecount = %d\n", out->_frame_count);
|
|
return -1;
|
|
}
|
|
/* ElSE, set the interrupt mask register, re-enable irq. */
|
|
int_msk_tmp = cx_read(channel->int_msk);
|
|
cx_write(channel->int_msk, int_msk_tmp |= _intr_msk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static irqreturn_t cx25821_upstream_irq(int irq, void *dev_id)
|
|
{
|
|
struct cx25821_channel *chan = dev_id;
|
|
struct cx25821_dev *dev = chan->dev;
|
|
u32 vid_status;
|
|
int handled = 0;
|
|
const struct sram_channel *sram_ch;
|
|
|
|
if (!dev)
|
|
return -1;
|
|
|
|
sram_ch = chan->sram_channels;
|
|
|
|
vid_status = cx_read(sram_ch->int_stat);
|
|
|
|
/* Only deal with our interrupt */
|
|
if (vid_status)
|
|
handled = cx25821_video_upstream_irq(chan, vid_status);
|
|
|
|
return IRQ_RETVAL(handled);
|
|
}
|
|
|
|
static void cx25821_set_pixelengine(struct cx25821_channel *chan,
|
|
const struct sram_channel *ch,
|
|
int pix_format)
|
|
{
|
|
struct cx25821_video_out_data *out = chan->out;
|
|
struct cx25821_dev *dev = chan->dev;
|
|
int width = WIDTH_D1;
|
|
int height = out->_lines_count;
|
|
int num_lines, odd_num_lines;
|
|
u32 value;
|
|
int vip_mode = OUTPUT_FRMT_656;
|
|
|
|
value = ((pix_format & 0x3) << 12) | (vip_mode & 0x7);
|
|
value &= 0xFFFFFFEF;
|
|
value |= out->is_60hz ? 0 : 0x10;
|
|
cx_write(ch->vid_fmt_ctl, value);
|
|
|
|
/* set number of active pixels in each line.
|
|
* Default is 720 pixels in both NTSC and PAL format */
|
|
cx_write(ch->vid_active_ctl1, width);
|
|
|
|
num_lines = (height / 2) & 0x3FF;
|
|
odd_num_lines = num_lines;
|
|
|
|
if (out->is_60hz)
|
|
odd_num_lines += 1;
|
|
|
|
value = (num_lines << 16) | odd_num_lines;
|
|
|
|
/* set number of active lines in field 0 (top) and field 1 (bottom) */
|
|
cx_write(ch->vid_active_ctl2, value);
|
|
|
|
cx_write(ch->vid_cdt_size, VID_CDT_SIZE >> 3);
|
|
}
|
|
|
|
static int cx25821_start_video_dma_upstream(struct cx25821_channel *chan,
|
|
const struct sram_channel *sram_ch)
|
|
{
|
|
struct cx25821_video_out_data *out = chan->out;
|
|
struct cx25821_dev *dev = chan->dev;
|
|
u32 tmp = 0;
|
|
int err = 0;
|
|
|
|
/* 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for
|
|
* channel A-C
|
|
*/
|
|
tmp = cx_read(VID_CH_MODE_SEL);
|
|
cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);
|
|
|
|
/* Set the physical start address of the RISC program in the initial
|
|
* program counter(IPC) member of the cmds.
|
|
*/
|
|
cx_write(sram_ch->cmds_start + 0, out->_dma_phys_addr);
|
|
/* Risc IPC High 64 bits 63-32 */
|
|
cx_write(sram_ch->cmds_start + 4, 0);
|
|
|
|
/* reset counter */
|
|
cx_write(sram_ch->gpcnt_ctl, 3);
|
|
|
|
/* Clear our bits from the interrupt status register. */
|
|
cx_write(sram_ch->int_stat, _intr_msk);
|
|
|
|
/* Set the interrupt mask register, enable irq. */
|
|
cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << sram_ch->irq_bit));
|
|
tmp = cx_read(sram_ch->int_msk);
|
|
cx_write(sram_ch->int_msk, tmp |= _intr_msk);
|
|
|
|
err = request_irq(dev->pci->irq, cx25821_upstream_irq,
|
|
IRQF_SHARED, dev->name, chan);
|
|
if (err < 0) {
|
|
pr_err("%s: can't get upstream IRQ %d\n",
|
|
dev->name, dev->pci->irq);
|
|
goto fail_irq;
|
|
}
|
|
|
|
/* Start the DMA engine */
|
|
tmp = cx_read(sram_ch->dma_ctl);
|
|
cx_set(sram_ch->dma_ctl, tmp | FLD_VID_RISC_EN);
|
|
|
|
out->_is_running = 1;
|
|
out->_is_first_frame = 1;
|
|
|
|
return 0;
|
|
|
|
fail_irq:
|
|
cx25821_dev_unregister(dev);
|
|
return err;
|
|
}
|
|
|
|
int cx25821_vidupstream_init(struct cx25821_channel *chan,
|
|
int pixel_format)
|
|
{
|
|
struct cx25821_video_out_data *out = chan->out;
|
|
struct cx25821_dev *dev = chan->dev;
|
|
const struct sram_channel *sram_ch;
|
|
u32 tmp;
|
|
int err = 0;
|
|
int data_frame_size = 0;
|
|
int risc_buffer_size = 0;
|
|
|
|
if (out->_is_running) {
|
|
pr_info("Video Channel is still running so return!\n");
|
|
return 0;
|
|
}
|
|
|
|
sram_ch = chan->sram_channels;
|
|
|
|
out->is_60hz = dev->tvnorm & V4L2_STD_525_60;
|
|
|
|
/* 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for
|
|
* channel A-C
|
|
*/
|
|
tmp = cx_read(VID_CH_MODE_SEL);
|
|
cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);
|
|
|
|
out->_is_running = 0;
|
|
out->_frame_count = 0;
|
|
out->_file_status = RESET_STATUS;
|
|
out->_lines_count = out->is_60hz ? 480 : 576;
|
|
out->_pixel_format = pixel_format;
|
|
out->_line_size = (out->_pixel_format == PIXEL_FRMT_422) ?
|
|
(WIDTH_D1 * 2) : (WIDTH_D1 * 3) / 2;
|
|
data_frame_size = out->is_60hz ? NTSC_DATA_BUF_SZ : PAL_DATA_BUF_SZ;
|
|
risc_buffer_size = out->is_60hz ?
|
|
NTSC_RISC_BUF_SIZE : PAL_RISC_BUF_SIZE;
|
|
|
|
out->_is_running = 0;
|
|
out->_frame_count = 0;
|
|
out->_file_status = RESET_STATUS;
|
|
out->_lines_count = out->is_60hz ? 480 : 576;
|
|
out->_pixel_format = pixel_format;
|
|
out->_line_size = (out->_pixel_format == PIXEL_FRMT_422) ?
|
|
(WIDTH_D1 * 2) : (WIDTH_D1 * 3) / 2;
|
|
out->curpos = 0;
|
|
init_waitqueue_head(&out->waitq);
|
|
|
|
err = cx25821_sram_channel_setup_upstream(dev, sram_ch,
|
|
out->_line_size, 0);
|
|
|
|
/* setup fifo + format */
|
|
cx25821_set_pixelengine(chan, sram_ch, out->_pixel_format);
|
|
|
|
out->upstream_riscbuf_size = risc_buffer_size * 2;
|
|
out->upstream_databuf_size = data_frame_size * 2;
|
|
|
|
/* Allocating buffers and prepare RISC program */
|
|
err = cx25821_upstream_buffer_prepare(chan, sram_ch, out->_line_size);
|
|
if (err < 0) {
|
|
pr_err("%s: Failed to set up Video upstream buffers!\n",
|
|
dev->name);
|
|
goto error;
|
|
}
|
|
|
|
cx25821_start_video_dma_upstream(chan, sram_ch);
|
|
|
|
return 0;
|
|
|
|
error:
|
|
cx25821_dev_unregister(dev);
|
|
|
|
return err;
|
|
}
|