395 lines
12 KiB
C
395 lines
12 KiB
C
/*
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* vsp1_pipe.c -- R-Car VSP1 Pipeline
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*
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* Copyright (C) 2013-2015 Renesas Electronics Corporation
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*
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* Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/delay.h>
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#include <linux/list.h>
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#include <linux/sched.h>
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#include <linux/wait.h>
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#include <media/media-entity.h>
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#include <media/v4l2-subdev.h>
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#include "vsp1.h"
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#include "vsp1_bru.h"
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#include "vsp1_dl.h"
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#include "vsp1_entity.h"
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#include "vsp1_pipe.h"
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#include "vsp1_rwpf.h"
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#include "vsp1_uds.h"
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/* -----------------------------------------------------------------------------
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* Helper Functions
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*/
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static const struct vsp1_format_info vsp1_video_formats[] = {
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{ V4L2_PIX_FMT_RGB332, MEDIA_BUS_FMT_ARGB8888_1X32,
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VI6_FMT_RGB_332, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
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VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
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1, { 8, 0, 0 }, false, false, 1, 1, false },
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{ V4L2_PIX_FMT_ARGB444, MEDIA_BUS_FMT_ARGB8888_1X32,
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VI6_FMT_ARGB_4444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
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VI6_RPF_DSWAP_P_WDS,
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1, { 16, 0, 0 }, false, false, 1, 1, true },
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{ V4L2_PIX_FMT_XRGB444, MEDIA_BUS_FMT_ARGB8888_1X32,
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VI6_FMT_XRGB_4444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
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VI6_RPF_DSWAP_P_WDS,
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1, { 16, 0, 0 }, false, false, 1, 1, false },
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{ V4L2_PIX_FMT_ARGB555, MEDIA_BUS_FMT_ARGB8888_1X32,
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VI6_FMT_ARGB_1555, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
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VI6_RPF_DSWAP_P_WDS,
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1, { 16, 0, 0 }, false, false, 1, 1, true },
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{ V4L2_PIX_FMT_XRGB555, MEDIA_BUS_FMT_ARGB8888_1X32,
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VI6_FMT_XRGB_1555, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
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VI6_RPF_DSWAP_P_WDS,
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1, { 16, 0, 0 }, false, false, 1, 1, false },
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{ V4L2_PIX_FMT_RGB565, MEDIA_BUS_FMT_ARGB8888_1X32,
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VI6_FMT_RGB_565, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
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VI6_RPF_DSWAP_P_WDS,
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1, { 16, 0, 0 }, false, false, 1, 1, false },
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{ V4L2_PIX_FMT_BGR24, MEDIA_BUS_FMT_ARGB8888_1X32,
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VI6_FMT_BGR_888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
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VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
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1, { 24, 0, 0 }, false, false, 1, 1, false },
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{ V4L2_PIX_FMT_RGB24, MEDIA_BUS_FMT_ARGB8888_1X32,
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VI6_FMT_RGB_888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
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VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
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1, { 24, 0, 0 }, false, false, 1, 1, false },
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{ V4L2_PIX_FMT_ABGR32, MEDIA_BUS_FMT_ARGB8888_1X32,
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VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS,
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1, { 32, 0, 0 }, false, false, 1, 1, true },
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{ V4L2_PIX_FMT_XBGR32, MEDIA_BUS_FMT_ARGB8888_1X32,
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VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS,
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1, { 32, 0, 0 }, false, false, 1, 1, false },
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{ V4L2_PIX_FMT_ARGB32, MEDIA_BUS_FMT_ARGB8888_1X32,
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VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
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VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
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1, { 32, 0, 0 }, false, false, 1, 1, true },
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{ V4L2_PIX_FMT_XRGB32, MEDIA_BUS_FMT_ARGB8888_1X32,
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VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
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VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
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1, { 32, 0, 0 }, false, false, 1, 1, false },
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{ V4L2_PIX_FMT_UYVY, MEDIA_BUS_FMT_AYUV8_1X32,
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VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
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VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
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1, { 16, 0, 0 }, false, false, 2, 1, false },
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{ V4L2_PIX_FMT_VYUY, MEDIA_BUS_FMT_AYUV8_1X32,
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VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
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VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
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1, { 16, 0, 0 }, false, true, 2, 1, false },
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{ V4L2_PIX_FMT_YUYV, MEDIA_BUS_FMT_AYUV8_1X32,
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VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
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VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
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1, { 16, 0, 0 }, true, false, 2, 1, false },
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{ V4L2_PIX_FMT_YVYU, MEDIA_BUS_FMT_AYUV8_1X32,
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VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
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VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
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1, { 16, 0, 0 }, true, true, 2, 1, false },
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{ V4L2_PIX_FMT_NV12M, MEDIA_BUS_FMT_AYUV8_1X32,
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VI6_FMT_Y_UV_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
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VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
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2, { 8, 16, 0 }, false, false, 2, 2, false },
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{ V4L2_PIX_FMT_NV21M, MEDIA_BUS_FMT_AYUV8_1X32,
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VI6_FMT_Y_UV_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
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VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
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2, { 8, 16, 0 }, false, true, 2, 2, false },
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{ V4L2_PIX_FMT_NV16M, MEDIA_BUS_FMT_AYUV8_1X32,
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VI6_FMT_Y_UV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
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VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
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2, { 8, 16, 0 }, false, false, 2, 1, false },
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{ V4L2_PIX_FMT_NV61M, MEDIA_BUS_FMT_AYUV8_1X32,
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VI6_FMT_Y_UV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
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VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
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2, { 8, 16, 0 }, false, true, 2, 1, false },
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{ V4L2_PIX_FMT_YUV420M, MEDIA_BUS_FMT_AYUV8_1X32,
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VI6_FMT_Y_U_V_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
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VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
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3, { 8, 8, 8 }, false, false, 2, 2, false },
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{ V4L2_PIX_FMT_YVU420M, MEDIA_BUS_FMT_AYUV8_1X32,
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VI6_FMT_Y_U_V_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
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VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
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3, { 8, 8, 8 }, false, true, 2, 2, false },
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{ V4L2_PIX_FMT_YUV422M, MEDIA_BUS_FMT_AYUV8_1X32,
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VI6_FMT_Y_U_V_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
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VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
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3, { 8, 8, 8 }, false, false, 2, 1, false },
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{ V4L2_PIX_FMT_YVU422M, MEDIA_BUS_FMT_AYUV8_1X32,
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VI6_FMT_Y_U_V_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
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VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
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3, { 8, 8, 8 }, false, true, 2, 1, false },
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{ V4L2_PIX_FMT_YUV444M, MEDIA_BUS_FMT_AYUV8_1X32,
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VI6_FMT_Y_U_V_444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
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VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
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3, { 8, 8, 8 }, false, false, 1, 1, false },
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{ V4L2_PIX_FMT_YVU444M, MEDIA_BUS_FMT_AYUV8_1X32,
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VI6_FMT_Y_U_V_444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
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VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
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3, { 8, 8, 8 }, false, true, 1, 1, false },
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};
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/**
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* vsp1_get_format_info - Retrieve format information for a 4CC
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* @vsp1: the VSP1 device
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* @fourcc: the format 4CC
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*
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* Return a pointer to the format information structure corresponding to the
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* given V4L2 format 4CC, or NULL if no corresponding format can be found.
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*/
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const struct vsp1_format_info *vsp1_get_format_info(struct vsp1_device *vsp1,
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u32 fourcc)
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{
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unsigned int i;
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/* Special case, the VYUY format is supported on Gen2 only. */
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if (vsp1->info->gen != 2 && fourcc == V4L2_PIX_FMT_VYUY)
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return NULL;
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for (i = 0; i < ARRAY_SIZE(vsp1_video_formats); ++i) {
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const struct vsp1_format_info *info = &vsp1_video_formats[i];
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if (info->fourcc == fourcc)
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return info;
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}
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return NULL;
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}
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/* -----------------------------------------------------------------------------
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* Pipeline Management
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*/
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void vsp1_pipeline_reset(struct vsp1_pipeline *pipe)
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{
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unsigned int i;
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if (pipe->bru) {
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struct vsp1_bru *bru = to_bru(&pipe->bru->subdev);
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for (i = 0; i < ARRAY_SIZE(bru->inputs); ++i)
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bru->inputs[i].rpf = NULL;
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}
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for (i = 0; i < ARRAY_SIZE(pipe->inputs); ++i) {
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if (pipe->inputs[i]) {
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pipe->inputs[i]->pipe = NULL;
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pipe->inputs[i] = NULL;
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}
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}
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if (pipe->output) {
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pipe->output->pipe = NULL;
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pipe->output = NULL;
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}
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INIT_LIST_HEAD(&pipe->entities);
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pipe->state = VSP1_PIPELINE_STOPPED;
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pipe->buffers_ready = 0;
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pipe->num_inputs = 0;
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pipe->bru = NULL;
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pipe->lif = NULL;
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pipe->uds = NULL;
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}
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void vsp1_pipeline_init(struct vsp1_pipeline *pipe)
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{
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mutex_init(&pipe->lock);
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spin_lock_init(&pipe->irqlock);
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init_waitqueue_head(&pipe->wq);
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kref_init(&pipe->kref);
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INIT_LIST_HEAD(&pipe->entities);
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pipe->state = VSP1_PIPELINE_STOPPED;
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}
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/* Must be called with the pipe irqlock held. */
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void vsp1_pipeline_run(struct vsp1_pipeline *pipe)
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{
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struct vsp1_device *vsp1 = pipe->output->entity.vsp1;
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if (pipe->state == VSP1_PIPELINE_STOPPED) {
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vsp1_write(vsp1, VI6_CMD(pipe->output->entity.index),
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VI6_CMD_STRCMD);
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pipe->state = VSP1_PIPELINE_RUNNING;
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}
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pipe->buffers_ready = 0;
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}
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bool vsp1_pipeline_stopped(struct vsp1_pipeline *pipe)
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{
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unsigned long flags;
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bool stopped;
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spin_lock_irqsave(&pipe->irqlock, flags);
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stopped = pipe->state == VSP1_PIPELINE_STOPPED;
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spin_unlock_irqrestore(&pipe->irqlock, flags);
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return stopped;
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}
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int vsp1_pipeline_stop(struct vsp1_pipeline *pipe)
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{
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struct vsp1_entity *entity;
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unsigned long flags;
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int ret;
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if (pipe->lif) {
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/* When using display lists in continuous frame mode the only
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* way to stop the pipeline is to reset the hardware.
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*/
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ret = vsp1_reset_wpf(pipe->output->entity.vsp1,
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pipe->output->entity.index);
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if (ret == 0) {
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spin_lock_irqsave(&pipe->irqlock, flags);
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pipe->state = VSP1_PIPELINE_STOPPED;
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spin_unlock_irqrestore(&pipe->irqlock, flags);
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}
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} else {
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/* Otherwise just request a stop and wait. */
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spin_lock_irqsave(&pipe->irqlock, flags);
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if (pipe->state == VSP1_PIPELINE_RUNNING)
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pipe->state = VSP1_PIPELINE_STOPPING;
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spin_unlock_irqrestore(&pipe->irqlock, flags);
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ret = wait_event_timeout(pipe->wq, vsp1_pipeline_stopped(pipe),
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msecs_to_jiffies(500));
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ret = ret == 0 ? -ETIMEDOUT : 0;
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}
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list_for_each_entry(entity, &pipe->entities, list_pipe) {
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if (entity->route && entity->route->reg)
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vsp1_write(entity->vsp1, entity->route->reg,
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VI6_DPR_NODE_UNUSED);
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}
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v4l2_subdev_call(&pipe->output->entity.subdev, video, s_stream, 0);
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return ret;
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}
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bool vsp1_pipeline_ready(struct vsp1_pipeline *pipe)
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{
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unsigned int mask;
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mask = ((1 << pipe->num_inputs) - 1) << 1;
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if (!pipe->lif)
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mask |= 1 << 0;
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return pipe->buffers_ready == mask;
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}
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void vsp1_pipeline_frame_end(struct vsp1_pipeline *pipe)
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{
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if (pipe == NULL)
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return;
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vsp1_dlm_irq_frame_end(pipe->output->dlm);
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if (pipe->frame_end)
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pipe->frame_end(pipe);
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pipe->sequence++;
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}
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/*
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* Propagate the alpha value through the pipeline.
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*
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* As the UDS has restricted scaling capabilities when the alpha component needs
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* to be scaled, we disable alpha scaling when the UDS input has a fixed alpha
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* value. The UDS then outputs a fixed alpha value which needs to be programmed
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* from the input RPF alpha.
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*/
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void vsp1_pipeline_propagate_alpha(struct vsp1_pipeline *pipe,
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struct vsp1_dl_list *dl, unsigned int alpha)
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{
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if (!pipe->uds)
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return;
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/* The BRU background color has a fixed alpha value set to 255, the
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* output alpha value is thus always equal to 255.
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*/
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if (pipe->uds_input->type == VSP1_ENTITY_BRU)
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alpha = 255;
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vsp1_uds_set_alpha(pipe->uds, dl, alpha);
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}
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void vsp1_pipelines_suspend(struct vsp1_device *vsp1)
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{
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unsigned long flags;
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unsigned int i;
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int ret;
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/* To avoid increasing the system suspend time needlessly, loop over the
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* pipelines twice, first to set them all to the stopping state, and
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* then to wait for the stop to complete.
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*/
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for (i = 0; i < vsp1->info->wpf_count; ++i) {
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struct vsp1_rwpf *wpf = vsp1->wpf[i];
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struct vsp1_pipeline *pipe;
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if (wpf == NULL)
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continue;
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pipe = wpf->pipe;
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if (pipe == NULL)
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continue;
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spin_lock_irqsave(&pipe->irqlock, flags);
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if (pipe->state == VSP1_PIPELINE_RUNNING)
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pipe->state = VSP1_PIPELINE_STOPPING;
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spin_unlock_irqrestore(&pipe->irqlock, flags);
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}
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for (i = 0; i < vsp1->info->wpf_count; ++i) {
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struct vsp1_rwpf *wpf = vsp1->wpf[i];
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struct vsp1_pipeline *pipe;
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if (wpf == NULL)
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continue;
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pipe = wpf->pipe;
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if (pipe == NULL)
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continue;
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ret = wait_event_timeout(pipe->wq, vsp1_pipeline_stopped(pipe),
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msecs_to_jiffies(500));
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if (ret == 0)
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dev_warn(vsp1->dev, "pipeline %u stop timeout\n",
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wpf->entity.index);
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}
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}
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void vsp1_pipelines_resume(struct vsp1_device *vsp1)
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{
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unsigned long flags;
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unsigned int i;
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/* Resume all running pipelines. */
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for (i = 0; i < vsp1->info->wpf_count; ++i) {
|
|
struct vsp1_rwpf *wpf = vsp1->wpf[i];
|
|
struct vsp1_pipeline *pipe;
|
|
|
|
if (wpf == NULL)
|
|
continue;
|
|
|
|
pipe = wpf->pipe;
|
|
if (pipe == NULL)
|
|
continue;
|
|
|
|
spin_lock_irqsave(&pipe->irqlock, flags);
|
|
if (vsp1_pipeline_ready(pipe))
|
|
vsp1_pipeline_run(pipe);
|
|
spin_unlock_irqrestore(&pipe->irqlock, flags);
|
|
}
|
|
}
|