288 lines
6.6 KiB
C
288 lines
6.6 KiB
C
/*
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* SDHCI support for SiRF primaII and marco SoCs
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*
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* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
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*
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* Licensed under GPLv2 or later.
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*/
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/mmc/host.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_gpio.h>
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#include <linux/mmc/slot-gpio.h>
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#include "sdhci-pltfm.h"
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#define SDHCI_CLK_DELAY_SETTING 0x4C
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#define SDHCI_SIRF_8BITBUS BIT(3)
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#define SIRF_TUNING_COUNT 16384
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struct sdhci_sirf_priv {
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int gpio_cd;
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};
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static void sdhci_sirf_set_bus_width(struct sdhci_host *host, int width)
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{
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u8 ctrl;
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ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
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ctrl &= ~(SDHCI_CTRL_4BITBUS | SDHCI_SIRF_8BITBUS);
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/*
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* CSR atlas7 and prima2 SD host version is not 3.0
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* 8bit-width enable bit of CSR SD hosts is 3,
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* while stardard hosts use bit 5
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*/
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if (width == MMC_BUS_WIDTH_8)
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ctrl |= SDHCI_SIRF_8BITBUS;
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else if (width == MMC_BUS_WIDTH_4)
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ctrl |= SDHCI_CTRL_4BITBUS;
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sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
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}
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static u32 sdhci_sirf_readl_le(struct sdhci_host *host, int reg)
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{
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u32 val = readl(host->ioaddr + reg);
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if (unlikely((reg == SDHCI_CAPABILITIES_1) &&
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(host->mmc->caps & MMC_CAP_UHS_SDR50))) {
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/* fake CAP_1 register */
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val = SDHCI_SUPPORT_DDR50 |
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SDHCI_SUPPORT_SDR50 | SDHCI_USE_SDR50_TUNING;
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}
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if (unlikely(reg == SDHCI_SLOT_INT_STATUS)) {
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u32 prss = val;
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/* fake chips as V3.0 host conreoller */
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prss &= ~(0xFF << 16);
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val = prss | (SDHCI_SPEC_300 << 16);
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}
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return val;
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}
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static u16 sdhci_sirf_readw_le(struct sdhci_host *host, int reg)
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{
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u16 ret = 0;
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ret = readw(host->ioaddr + reg);
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if (unlikely(reg == SDHCI_HOST_VERSION)) {
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ret = readw(host->ioaddr + SDHCI_HOST_VERSION);
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ret |= SDHCI_SPEC_300;
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}
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return ret;
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}
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static int sdhci_sirf_execute_tuning(struct sdhci_host *host, u32 opcode)
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{
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int tuning_seq_cnt = 3;
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int phase;
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u8 tuned_phase_cnt = 0;
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int rc = 0, longest_range = 0;
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int start = -1, end = 0, tuning_value = -1, range = 0;
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u16 clock_setting;
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struct mmc_host *mmc = host->mmc;
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clock_setting = sdhci_readw(host, SDHCI_CLK_DELAY_SETTING);
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clock_setting &= ~0x3fff;
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retry:
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phase = 0;
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tuned_phase_cnt = 0;
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do {
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sdhci_writel(host,
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clock_setting | phase,
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SDHCI_CLK_DELAY_SETTING);
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if (!mmc_send_tuning(mmc, opcode, NULL)) {
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/* Tuning is successful at this tuning point */
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tuned_phase_cnt++;
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dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n",
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mmc_hostname(mmc), phase);
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if (start == -1)
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start = phase;
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end = phase;
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range++;
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if (phase == (SIRF_TUNING_COUNT - 1)
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&& range > longest_range)
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tuning_value = (start + end) / 2;
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} else {
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dev_dbg(mmc_dev(mmc), "%s: Found bad phase = %d\n",
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mmc_hostname(mmc), phase);
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if (range > longest_range) {
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tuning_value = (start + end) / 2;
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longest_range = range;
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}
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start = -1;
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end = range = 0;
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}
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} while (++phase < SIRF_TUNING_COUNT);
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if (tuned_phase_cnt && tuning_value > 0) {
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/*
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* Finally set the selected phase in delay
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* line hw block.
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*/
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phase = tuning_value;
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sdhci_writel(host,
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clock_setting | phase,
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SDHCI_CLK_DELAY_SETTING);
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dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n",
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mmc_hostname(mmc), phase);
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} else {
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if (--tuning_seq_cnt)
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goto retry;
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/* Tuning failed */
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dev_dbg(mmc_dev(mmc), "%s: No tuning point found\n",
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mmc_hostname(mmc));
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rc = -EIO;
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}
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return rc;
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}
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static struct sdhci_ops sdhci_sirf_ops = {
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.read_l = sdhci_sirf_readl_le,
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.read_w = sdhci_sirf_readw_le,
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.platform_execute_tuning = sdhci_sirf_execute_tuning,
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.set_clock = sdhci_set_clock,
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.get_max_clock = sdhci_pltfm_clk_get_max_clock,
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.set_bus_width = sdhci_sirf_set_bus_width,
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.reset = sdhci_reset,
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.set_uhs_signaling = sdhci_set_uhs_signaling,
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};
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static struct sdhci_pltfm_data sdhci_sirf_pdata = {
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.ops = &sdhci_sirf_ops,
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.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
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SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
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SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
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SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS,
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.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
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};
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static int sdhci_sirf_probe(struct platform_device *pdev)
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{
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struct sdhci_host *host;
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struct sdhci_pltfm_host *pltfm_host;
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struct sdhci_sirf_priv *priv;
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struct clk *clk;
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int gpio_cd;
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int ret;
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clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(clk)) {
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dev_err(&pdev->dev, "unable to get clock");
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return PTR_ERR(clk);
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}
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if (pdev->dev.of_node)
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gpio_cd = of_get_named_gpio(pdev->dev.of_node, "cd-gpios", 0);
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else
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gpio_cd = -EINVAL;
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host = sdhci_pltfm_init(pdev, &sdhci_sirf_pdata, sizeof(struct sdhci_sirf_priv));
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if (IS_ERR(host))
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return PTR_ERR(host);
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pltfm_host = sdhci_priv(host);
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pltfm_host->clk = clk;
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priv = sdhci_pltfm_priv(pltfm_host);
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priv->gpio_cd = gpio_cd;
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sdhci_get_of_property(pdev);
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ret = clk_prepare_enable(pltfm_host->clk);
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if (ret)
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goto err_clk_prepare;
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ret = sdhci_add_host(host);
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if (ret)
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goto err_sdhci_add;
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/*
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* We must request the IRQ after sdhci_add_host(), as the tasklet only
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* gets setup in sdhci_add_host() and we oops.
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*/
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if (gpio_is_valid(priv->gpio_cd)) {
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ret = mmc_gpio_request_cd(host->mmc, priv->gpio_cd, 0);
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if (ret) {
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dev_err(&pdev->dev, "card detect irq request failed: %d\n",
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ret);
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goto err_request_cd;
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}
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mmc_gpiod_request_cd_irq(host->mmc);
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}
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return 0;
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err_request_cd:
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sdhci_remove_host(host, 0);
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err_sdhci_add:
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clk_disable_unprepare(pltfm_host->clk);
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err_clk_prepare:
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sdhci_pltfm_free(pdev);
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return ret;
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}
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#ifdef CONFIG_PM_SLEEP
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static int sdhci_sirf_suspend(struct device *dev)
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{
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struct sdhci_host *host = dev_get_drvdata(dev);
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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int ret;
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ret = sdhci_suspend_host(host);
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if (ret)
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return ret;
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clk_disable(pltfm_host->clk);
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return 0;
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}
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static int sdhci_sirf_resume(struct device *dev)
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{
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struct sdhci_host *host = dev_get_drvdata(dev);
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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int ret;
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ret = clk_enable(pltfm_host->clk);
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if (ret) {
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dev_dbg(dev, "Resume: Error enabling clock\n");
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return ret;
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}
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return sdhci_resume_host(host);
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}
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#endif
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static SIMPLE_DEV_PM_OPS(sdhci_sirf_pm_ops, sdhci_sirf_suspend, sdhci_sirf_resume);
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static const struct of_device_id sdhci_sirf_of_match[] = {
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{ .compatible = "sirf,prima2-sdhc" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, sdhci_sirf_of_match);
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static struct platform_driver sdhci_sirf_driver = {
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.driver = {
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.name = "sdhci-sirf",
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.of_match_table = sdhci_sirf_of_match,
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.pm = &sdhci_sirf_pm_ops,
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},
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.probe = sdhci_sirf_probe,
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.remove = sdhci_pltfm_unregister,
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};
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module_platform_driver(sdhci_sirf_driver);
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MODULE_DESCRIPTION("SDHCI driver for SiRFprimaII/SiRFmarco");
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MODULE_AUTHOR("Barry Song <21cnbao@gmail.com>");
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MODULE_LICENSE("GPL v2");
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