417 lines
10 KiB
C
417 lines
10 KiB
C
/*
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* JZ4780 NAND driver
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*
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* Copyright (c) 2015 Imagination Technologies
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* Author: Alex Smith <alex.smith@imgtec.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/list.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/gpio/consumer.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include <linux/jz4780-nemc.h>
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#include "jz4780_bch.h"
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#define DRV_NAME "jz4780-nand"
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#define OFFSET_DATA 0x00000000
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#define OFFSET_CMD 0x00400000
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#define OFFSET_ADDR 0x00800000
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/* Command delay when there is no R/B pin. */
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#define RB_DELAY_US 100
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struct jz4780_nand_cs {
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unsigned int bank;
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void __iomem *base;
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};
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struct jz4780_nand_controller {
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struct device *dev;
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struct jz4780_bch *bch;
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struct nand_hw_control controller;
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unsigned int num_banks;
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struct list_head chips;
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int selected;
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struct jz4780_nand_cs cs[];
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};
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struct jz4780_nand_chip {
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struct nand_chip chip;
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struct list_head chip_list;
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struct gpio_desc *busy_gpio;
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struct gpio_desc *wp_gpio;
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unsigned int reading: 1;
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};
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static inline struct jz4780_nand_chip *to_jz4780_nand_chip(struct mtd_info *mtd)
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{
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return container_of(mtd_to_nand(mtd), struct jz4780_nand_chip, chip);
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}
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static inline struct jz4780_nand_controller *to_jz4780_nand_controller(struct nand_hw_control *ctrl)
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{
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return container_of(ctrl, struct jz4780_nand_controller, controller);
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}
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static void jz4780_nand_select_chip(struct mtd_info *mtd, int chipnr)
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{
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struct jz4780_nand_chip *nand = to_jz4780_nand_chip(mtd);
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struct jz4780_nand_controller *nfc = to_jz4780_nand_controller(nand->chip.controller);
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struct jz4780_nand_cs *cs;
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/* Ensure the currently selected chip is deasserted. */
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if (chipnr == -1 && nfc->selected >= 0) {
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cs = &nfc->cs[nfc->selected];
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jz4780_nemc_assert(nfc->dev, cs->bank, false);
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}
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nfc->selected = chipnr;
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}
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static void jz4780_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
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unsigned int ctrl)
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{
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struct jz4780_nand_chip *nand = to_jz4780_nand_chip(mtd);
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struct jz4780_nand_controller *nfc = to_jz4780_nand_controller(nand->chip.controller);
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struct jz4780_nand_cs *cs;
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if (WARN_ON(nfc->selected < 0))
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return;
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cs = &nfc->cs[nfc->selected];
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jz4780_nemc_assert(nfc->dev, cs->bank, ctrl & NAND_NCE);
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if (cmd == NAND_CMD_NONE)
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return;
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if (ctrl & NAND_ALE)
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writeb(cmd, cs->base + OFFSET_ADDR);
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else if (ctrl & NAND_CLE)
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writeb(cmd, cs->base + OFFSET_CMD);
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}
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static int jz4780_nand_dev_ready(struct mtd_info *mtd)
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{
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struct jz4780_nand_chip *nand = to_jz4780_nand_chip(mtd);
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return !gpiod_get_value_cansleep(nand->busy_gpio);
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}
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static void jz4780_nand_ecc_hwctl(struct mtd_info *mtd, int mode)
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{
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struct jz4780_nand_chip *nand = to_jz4780_nand_chip(mtd);
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nand->reading = (mode == NAND_ECC_READ);
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}
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static int jz4780_nand_ecc_calculate(struct mtd_info *mtd, const u8 *dat,
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u8 *ecc_code)
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{
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struct jz4780_nand_chip *nand = to_jz4780_nand_chip(mtd);
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struct jz4780_nand_controller *nfc = to_jz4780_nand_controller(nand->chip.controller);
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struct jz4780_bch_params params;
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/*
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* Don't need to generate the ECC when reading, BCH does it for us as
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* part of decoding/correction.
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*/
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if (nand->reading)
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return 0;
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params.size = nand->chip.ecc.size;
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params.bytes = nand->chip.ecc.bytes;
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params.strength = nand->chip.ecc.strength;
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return jz4780_bch_calculate(nfc->bch, ¶ms, dat, ecc_code);
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}
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static int jz4780_nand_ecc_correct(struct mtd_info *mtd, u8 *dat,
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u8 *read_ecc, u8 *calc_ecc)
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{
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struct jz4780_nand_chip *nand = to_jz4780_nand_chip(mtd);
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struct jz4780_nand_controller *nfc = to_jz4780_nand_controller(nand->chip.controller);
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struct jz4780_bch_params params;
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params.size = nand->chip.ecc.size;
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params.bytes = nand->chip.ecc.bytes;
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params.strength = nand->chip.ecc.strength;
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return jz4780_bch_correct(nfc->bch, ¶ms, dat, read_ecc);
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}
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static int jz4780_nand_init_ecc(struct jz4780_nand_chip *nand, struct device *dev)
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{
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struct nand_chip *chip = &nand->chip;
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struct mtd_info *mtd = nand_to_mtd(chip);
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struct jz4780_nand_controller *nfc = to_jz4780_nand_controller(chip->controller);
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int eccbytes;
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chip->ecc.bytes = fls((1 + 8) * chip->ecc.size) *
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(chip->ecc.strength / 8);
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switch (chip->ecc.mode) {
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case NAND_ECC_HW:
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if (!nfc->bch) {
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dev_err(dev, "HW BCH selected, but BCH controller not found\n");
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return -ENODEV;
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}
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chip->ecc.hwctl = jz4780_nand_ecc_hwctl;
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chip->ecc.calculate = jz4780_nand_ecc_calculate;
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chip->ecc.correct = jz4780_nand_ecc_correct;
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/* fall through */
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case NAND_ECC_SOFT:
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dev_info(dev, "using %s (strength %d, size %d, bytes %d)\n",
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(nfc->bch) ? "hardware BCH" : "software ECC",
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chip->ecc.strength, chip->ecc.size, chip->ecc.bytes);
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break;
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case NAND_ECC_NONE:
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dev_info(dev, "not using ECC\n");
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break;
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default:
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dev_err(dev, "ECC mode %d not supported\n", chip->ecc.mode);
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return -EINVAL;
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}
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/* The NAND core will generate the ECC layout for SW ECC */
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if (chip->ecc.mode != NAND_ECC_HW)
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return 0;
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/* Generate ECC layout. ECC codes are right aligned in the OOB area. */
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eccbytes = mtd->writesize / chip->ecc.size * chip->ecc.bytes;
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if (eccbytes > mtd->oobsize - 2) {
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dev_err(dev,
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"invalid ECC config: required %d ECC bytes, but only %d are available",
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eccbytes, mtd->oobsize - 2);
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return -EINVAL;
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}
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mtd->ooblayout = &nand_ooblayout_lp_ops;
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return 0;
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}
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static int jz4780_nand_init_chip(struct platform_device *pdev,
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struct jz4780_nand_controller *nfc,
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struct device_node *np,
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unsigned int chipnr)
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{
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struct device *dev = &pdev->dev;
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struct jz4780_nand_chip *nand;
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struct jz4780_nand_cs *cs;
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struct resource *res;
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struct nand_chip *chip;
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struct mtd_info *mtd;
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const __be32 *reg;
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int ret = 0;
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cs = &nfc->cs[chipnr];
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reg = of_get_property(np, "reg", NULL);
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if (!reg)
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return -EINVAL;
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cs->bank = be32_to_cpu(*reg);
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jz4780_nemc_set_type(nfc->dev, cs->bank, JZ4780_NEMC_BANK_NAND);
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res = platform_get_resource(pdev, IORESOURCE_MEM, chipnr);
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cs->base = devm_ioremap_resource(dev, res);
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if (IS_ERR(cs->base))
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return PTR_ERR(cs->base);
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nand = devm_kzalloc(dev, sizeof(*nand), GFP_KERNEL);
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if (!nand)
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return -ENOMEM;
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nand->busy_gpio = devm_gpiod_get_optional(dev, "rb", GPIOD_IN);
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if (IS_ERR(nand->busy_gpio)) {
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ret = PTR_ERR(nand->busy_gpio);
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dev_err(dev, "failed to request busy GPIO: %d\n", ret);
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return ret;
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} else if (nand->busy_gpio) {
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nand->chip.dev_ready = jz4780_nand_dev_ready;
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}
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nand->wp_gpio = devm_gpiod_get_optional(dev, "wp", GPIOD_OUT_LOW);
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if (IS_ERR(nand->wp_gpio)) {
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ret = PTR_ERR(nand->wp_gpio);
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dev_err(dev, "failed to request WP GPIO: %d\n", ret);
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return ret;
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}
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chip = &nand->chip;
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mtd = nand_to_mtd(chip);
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mtd->name = devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev),
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cs->bank);
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if (!mtd->name)
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return -ENOMEM;
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mtd->dev.parent = dev;
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chip->IO_ADDR_R = cs->base + OFFSET_DATA;
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chip->IO_ADDR_W = cs->base + OFFSET_DATA;
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chip->chip_delay = RB_DELAY_US;
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chip->options = NAND_NO_SUBPAGE_WRITE;
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chip->select_chip = jz4780_nand_select_chip;
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chip->cmd_ctrl = jz4780_nand_cmd_ctrl;
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chip->ecc.mode = NAND_ECC_HW;
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chip->controller = &nfc->controller;
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nand_set_flash_node(chip, np);
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ret = nand_scan_ident(mtd, 1, NULL);
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if (ret)
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return ret;
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ret = jz4780_nand_init_ecc(nand, dev);
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if (ret)
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return ret;
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ret = nand_scan_tail(mtd);
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if (ret)
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return ret;
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ret = mtd_device_register(mtd, NULL, 0);
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if (ret) {
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nand_release(chip);
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return ret;
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}
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list_add_tail(&nand->chip_list, &nfc->chips);
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return 0;
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}
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static void jz4780_nand_cleanup_chips(struct jz4780_nand_controller *nfc)
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{
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struct jz4780_nand_chip *chip;
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while (!list_empty(&nfc->chips)) {
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chip = list_first_entry(&nfc->chips, struct jz4780_nand_chip, chip_list);
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nand_release(&chip->chip);
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list_del(&chip->chip_list);
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}
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}
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static int jz4780_nand_init_chips(struct jz4780_nand_controller *nfc,
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struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *np;
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int i = 0;
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int ret;
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int num_chips = of_get_child_count(dev->of_node);
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if (num_chips > nfc->num_banks) {
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dev_err(dev, "found %d chips but only %d banks\n", num_chips, nfc->num_banks);
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return -EINVAL;
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}
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for_each_child_of_node(dev->of_node, np) {
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ret = jz4780_nand_init_chip(pdev, nfc, np, i);
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if (ret) {
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jz4780_nand_cleanup_chips(nfc);
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return ret;
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}
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i++;
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}
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return 0;
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}
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static int jz4780_nand_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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unsigned int num_banks;
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struct jz4780_nand_controller *nfc;
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int ret;
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num_banks = jz4780_nemc_num_banks(dev);
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if (num_banks == 0) {
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dev_err(dev, "no banks found\n");
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return -ENODEV;
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}
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nfc = devm_kzalloc(dev, sizeof(*nfc) + (sizeof(nfc->cs[0]) * num_banks), GFP_KERNEL);
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if (!nfc)
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return -ENOMEM;
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/*
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* Check for BCH HW before we call nand_scan_ident, to prevent us from
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* having to call it again if the BCH driver returns -EPROBE_DEFER.
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*/
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nfc->bch = of_jz4780_bch_get(dev->of_node);
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if (IS_ERR(nfc->bch))
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return PTR_ERR(nfc->bch);
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nfc->dev = dev;
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nfc->num_banks = num_banks;
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nand_hw_control_init(&nfc->controller);
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INIT_LIST_HEAD(&nfc->chips);
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ret = jz4780_nand_init_chips(nfc, pdev);
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if (ret) {
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if (nfc->bch)
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jz4780_bch_release(nfc->bch);
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return ret;
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}
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platform_set_drvdata(pdev, nfc);
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return 0;
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}
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static int jz4780_nand_remove(struct platform_device *pdev)
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{
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struct jz4780_nand_controller *nfc = platform_get_drvdata(pdev);
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if (nfc->bch)
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jz4780_bch_release(nfc->bch);
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jz4780_nand_cleanup_chips(nfc);
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return 0;
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}
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static const struct of_device_id jz4780_nand_dt_match[] = {
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{ .compatible = "ingenic,jz4780-nand" },
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{},
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};
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MODULE_DEVICE_TABLE(of, jz4780_nand_dt_match);
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static struct platform_driver jz4780_nand_driver = {
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.probe = jz4780_nand_probe,
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.remove = jz4780_nand_remove,
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.driver = {
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.name = DRV_NAME,
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.of_match_table = of_match_ptr(jz4780_nand_dt_match),
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},
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};
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module_platform_driver(jz4780_nand_driver);
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MODULE_AUTHOR("Alex Smith <alex@alex-smith.me.uk>");
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MODULE_AUTHOR("Harvey Hunt <harveyhuntnexus@gmail.com>");
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MODULE_DESCRIPTION("Ingenic JZ4780 NAND driver");
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MODULE_LICENSE("GPL v2");
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