396 lines
9.5 KiB
C
396 lines
9.5 KiB
C
/*
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* B53 register access through MII registers
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*
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* Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include <linux/kernel.h>
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#include <linux/phy.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/brcmphy.h>
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#include <linux/rtnetlink.h>
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#include <net/dsa.h>
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#include "b53_priv.h"
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/* MII registers */
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#define REG_MII_PAGE 0x10 /* MII Page register */
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#define REG_MII_ADDR 0x11 /* MII Address register */
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#define REG_MII_DATA0 0x18 /* MII Data register 0 */
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#define REG_MII_DATA1 0x19 /* MII Data register 1 */
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#define REG_MII_DATA2 0x1a /* MII Data register 2 */
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#define REG_MII_DATA3 0x1b /* MII Data register 3 */
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#define REG_MII_PAGE_ENABLE BIT(0)
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#define REG_MII_ADDR_WRITE BIT(0)
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#define REG_MII_ADDR_READ BIT(1)
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static int b53_mdio_op(struct b53_device *dev, u8 page, u8 reg, u16 op)
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{
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int i;
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u16 v;
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int ret;
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struct mii_bus *bus = dev->priv;
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if (dev->current_page != page) {
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/* set page number */
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v = (page << 8) | REG_MII_PAGE_ENABLE;
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ret = mdiobus_write_nested(bus, BRCM_PSEUDO_PHY_ADDR,
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REG_MII_PAGE, v);
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if (ret)
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return ret;
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dev->current_page = page;
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}
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/* set register address */
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v = (reg << 8) | op;
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ret = mdiobus_write_nested(bus, BRCM_PSEUDO_PHY_ADDR, REG_MII_ADDR, v);
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if (ret)
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return ret;
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/* check if operation completed */
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for (i = 0; i < 5; ++i) {
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v = mdiobus_read_nested(bus, BRCM_PSEUDO_PHY_ADDR,
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REG_MII_ADDR);
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if (!(v & (REG_MII_ADDR_WRITE | REG_MII_ADDR_READ)))
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break;
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usleep_range(10, 100);
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}
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if (WARN_ON(i == 5))
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return -EIO;
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return 0;
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}
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static int b53_mdio_read8(struct b53_device *dev, u8 page, u8 reg, u8 *val)
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{
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struct mii_bus *bus = dev->priv;
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int ret;
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ret = b53_mdio_op(dev, page, reg, REG_MII_ADDR_READ);
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if (ret)
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return ret;
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*val = mdiobus_read_nested(bus, BRCM_PSEUDO_PHY_ADDR,
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REG_MII_DATA0) & 0xff;
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return 0;
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}
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static int b53_mdio_read16(struct b53_device *dev, u8 page, u8 reg, u16 *val)
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{
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struct mii_bus *bus = dev->priv;
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int ret;
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ret = b53_mdio_op(dev, page, reg, REG_MII_ADDR_READ);
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if (ret)
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return ret;
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*val = mdiobus_read_nested(bus, BRCM_PSEUDO_PHY_ADDR, REG_MII_DATA0);
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return 0;
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}
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static int b53_mdio_read32(struct b53_device *dev, u8 page, u8 reg, u32 *val)
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{
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struct mii_bus *bus = dev->priv;
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int ret;
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ret = b53_mdio_op(dev, page, reg, REG_MII_ADDR_READ);
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if (ret)
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return ret;
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*val = mdiobus_read_nested(bus, BRCM_PSEUDO_PHY_ADDR, REG_MII_DATA0);
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*val |= mdiobus_read_nested(bus, BRCM_PSEUDO_PHY_ADDR,
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REG_MII_DATA1) << 16;
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return 0;
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}
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static int b53_mdio_read48(struct b53_device *dev, u8 page, u8 reg, u64 *val)
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{
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struct mii_bus *bus = dev->priv;
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u64 temp = 0;
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int i;
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int ret;
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ret = b53_mdio_op(dev, page, reg, REG_MII_ADDR_READ);
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if (ret)
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return ret;
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for (i = 2; i >= 0; i--) {
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temp <<= 16;
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temp |= mdiobus_read_nested(bus, BRCM_PSEUDO_PHY_ADDR,
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REG_MII_DATA0 + i);
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}
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*val = temp;
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return 0;
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}
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static int b53_mdio_read64(struct b53_device *dev, u8 page, u8 reg, u64 *val)
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{
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struct mii_bus *bus = dev->priv;
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u64 temp = 0;
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int i;
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int ret;
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ret = b53_mdio_op(dev, page, reg, REG_MII_ADDR_READ);
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if (ret)
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return ret;
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for (i = 3; i >= 0; i--) {
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temp <<= 16;
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temp |= mdiobus_read_nested(bus, BRCM_PSEUDO_PHY_ADDR,
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REG_MII_DATA0 + i);
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}
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*val = temp;
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return 0;
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}
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static int b53_mdio_write8(struct b53_device *dev, u8 page, u8 reg, u8 value)
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{
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struct mii_bus *bus = dev->priv;
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int ret;
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ret = mdiobus_write_nested(bus, BRCM_PSEUDO_PHY_ADDR,
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REG_MII_DATA0, value);
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if (ret)
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return ret;
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return b53_mdio_op(dev, page, reg, REG_MII_ADDR_WRITE);
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}
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static int b53_mdio_write16(struct b53_device *dev, u8 page, u8 reg,
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u16 value)
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{
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struct mii_bus *bus = dev->priv;
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int ret;
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ret = mdiobus_write_nested(bus, BRCM_PSEUDO_PHY_ADDR,
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REG_MII_DATA0, value);
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if (ret)
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return ret;
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return b53_mdio_op(dev, page, reg, REG_MII_ADDR_WRITE);
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}
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static int b53_mdio_write32(struct b53_device *dev, u8 page, u8 reg,
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u32 value)
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{
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struct mii_bus *bus = dev->priv;
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unsigned int i;
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u32 temp = value;
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for (i = 0; i < 2; i++) {
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int ret = mdiobus_write_nested(bus, BRCM_PSEUDO_PHY_ADDR,
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REG_MII_DATA0 + i,
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temp & 0xffff);
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if (ret)
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return ret;
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temp >>= 16;
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}
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return b53_mdio_op(dev, page, reg, REG_MII_ADDR_WRITE);
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}
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static int b53_mdio_write48(struct b53_device *dev, u8 page, u8 reg,
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u64 value)
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{
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struct mii_bus *bus = dev->priv;
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unsigned int i;
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u64 temp = value;
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for (i = 0; i < 3; i++) {
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int ret = mdiobus_write_nested(bus, BRCM_PSEUDO_PHY_ADDR,
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REG_MII_DATA0 + i,
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temp & 0xffff);
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if (ret)
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return ret;
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temp >>= 16;
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}
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return b53_mdio_op(dev, page, reg, REG_MII_ADDR_WRITE);
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}
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static int b53_mdio_write64(struct b53_device *dev, u8 page, u8 reg,
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u64 value)
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{
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struct mii_bus *bus = dev->priv;
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unsigned int i;
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u64 temp = value;
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for (i = 0; i < 4; i++) {
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int ret = mdiobus_write_nested(bus, BRCM_PSEUDO_PHY_ADDR,
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REG_MII_DATA0 + i,
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temp & 0xffff);
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if (ret)
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return ret;
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temp >>= 16;
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}
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return b53_mdio_op(dev, page, reg, REG_MII_ADDR_WRITE);
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}
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static int b53_mdio_phy_read16(struct b53_device *dev, int addr, int reg,
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u16 *value)
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{
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struct mii_bus *bus = dev->priv;
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*value = mdiobus_read_nested(bus, addr, reg);
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return 0;
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}
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static int b53_mdio_phy_write16(struct b53_device *dev, int addr, int reg,
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u16 value)
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{
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struct mii_bus *bus = dev->bus;
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return mdiobus_write_nested(bus, addr, reg, value);
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}
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static const struct b53_io_ops b53_mdio_ops = {
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.read8 = b53_mdio_read8,
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.read16 = b53_mdio_read16,
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.read32 = b53_mdio_read32,
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.read48 = b53_mdio_read48,
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.read64 = b53_mdio_read64,
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.write8 = b53_mdio_write8,
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.write16 = b53_mdio_write16,
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.write32 = b53_mdio_write32,
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.write48 = b53_mdio_write48,
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.write64 = b53_mdio_write64,
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.phy_read16 = b53_mdio_phy_read16,
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.phy_write16 = b53_mdio_phy_write16,
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};
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#define B53_BRCM_OUI_1 0x0143bc00
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#define B53_BRCM_OUI_2 0x03625c00
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#define B53_BRCM_OUI_3 0x00406000
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#define B53_BRCM_OUI_4 0x01410c00
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static int b53_mdio_probe(struct mdio_device *mdiodev)
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{
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struct b53_device *dev;
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u32 phy_id;
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int ret;
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/* allow the generic PHY driver to take over the non-management MDIO
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* addresses
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*/
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if (mdiodev->addr != BRCM_PSEUDO_PHY_ADDR && mdiodev->addr != 0) {
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dev_err(&mdiodev->dev, "leaving address %d to PHY\n",
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mdiodev->addr);
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return -ENODEV;
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}
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/* read the first port's id */
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phy_id = mdiobus_read(mdiodev->bus, 0, 2) << 16;
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phy_id |= mdiobus_read(mdiodev->bus, 0, 3);
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/* BCM5325, BCM539x (OUI_1)
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* BCM53125, BCM53128 (OUI_2)
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* BCM5365 (OUI_3)
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*/
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if ((phy_id & 0xfffffc00) != B53_BRCM_OUI_1 &&
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(phy_id & 0xfffffc00) != B53_BRCM_OUI_2 &&
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(phy_id & 0xfffffc00) != B53_BRCM_OUI_3 &&
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(phy_id & 0xfffffc00) != B53_BRCM_OUI_4) {
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dev_err(&mdiodev->dev, "Unsupported device: 0x%08x\n", phy_id);
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return -ENODEV;
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}
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/* First probe will come from SWITCH_MDIO controller on the 7445D0
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* switch, which will conflict with the 7445 integrated switch
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* pseudo-phy (we end-up programming both). In that case, we return
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* -EPROBE_DEFER for the first time we get here, and wait until we come
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* back with the slave MDIO bus which has the correct indirection
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* layer setup
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*/
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if (of_machine_is_compatible("brcm,bcm7445d0") &&
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strcmp(mdiodev->bus->name, "sf2 slave mii"))
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return -EPROBE_DEFER;
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dev = b53_switch_alloc(&mdiodev->dev, &b53_mdio_ops, mdiodev->bus);
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if (!dev)
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return -ENOMEM;
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/* we don't use page 0xff, so force a page set */
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dev->current_page = 0xff;
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dev->bus = mdiodev->bus;
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dev_set_drvdata(&mdiodev->dev, dev);
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ret = b53_switch_register(dev);
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if (ret) {
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dev_err(&mdiodev->dev, "failed to register switch: %i\n", ret);
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return ret;
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}
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return ret;
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}
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static void b53_mdio_remove(struct mdio_device *mdiodev)
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{
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struct b53_device *dev = dev_get_drvdata(&mdiodev->dev);
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struct dsa_switch *ds = dev->ds;
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dsa_unregister_switch(ds);
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}
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static const struct of_device_id b53_of_match[] = {
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{ .compatible = "brcm,bcm5325" },
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{ .compatible = "brcm,bcm53115" },
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{ .compatible = "brcm,bcm53125" },
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{ .compatible = "brcm,bcm53128" },
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{ .compatible = "brcm,bcm5365" },
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{ .compatible = "brcm,bcm5389" },
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{ .compatible = "brcm,bcm5395" },
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{ .compatible = "brcm,bcm5397" },
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{ .compatible = "brcm,bcm5398" },
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{ /* sentinel */ },
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};
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MODULE_DEVICE_TABLE(of, b53_of_match);
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static struct mdio_driver b53_mdio_driver = {
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.probe = b53_mdio_probe,
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.remove = b53_mdio_remove,
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.mdiodrv.driver = {
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.name = "bcm53xx",
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.of_match_table = b53_of_match,
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},
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};
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static int __init b53_mdio_driver_register(void)
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{
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return mdio_driver_register(&b53_mdio_driver);
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}
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module_init(b53_mdio_driver_register);
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static void __exit b53_mdio_driver_unregister(void)
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{
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mdio_driver_unregister(&b53_mdio_driver);
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}
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module_exit(b53_mdio_driver_unregister);
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MODULE_DESCRIPTION("B53 MDIO access driver");
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MODULE_LICENSE("Dual BSD/GPL");
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