443 lines
10 KiB
C
443 lines
10 KiB
C
/*
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* B53 register access through Switch Register Access Bridge Registers
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*
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* Copyright (C) 2013 Hauke Mehrtens <hauke@hauke-m.de>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/platform_device.h>
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#include <linux/platform_data/b53.h>
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#include <linux/of.h>
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#include "b53_priv.h"
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/* command and status register of the SRAB */
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#define B53_SRAB_CMDSTAT 0x2c
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#define B53_SRAB_CMDSTAT_RST BIT(2)
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#define B53_SRAB_CMDSTAT_WRITE BIT(1)
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#define B53_SRAB_CMDSTAT_GORDYN BIT(0)
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#define B53_SRAB_CMDSTAT_PAGE 24
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#define B53_SRAB_CMDSTAT_REG 16
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/* high order word of write data to switch registe */
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#define B53_SRAB_WD_H 0x30
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/* low order word of write data to switch registe */
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#define B53_SRAB_WD_L 0x34
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/* high order word of read data from switch register */
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#define B53_SRAB_RD_H 0x38
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/* low order word of read data from switch register */
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#define B53_SRAB_RD_L 0x3c
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/* command and status register of the SRAB */
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#define B53_SRAB_CTRLS 0x40
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#define B53_SRAB_CTRLS_RCAREQ BIT(3)
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#define B53_SRAB_CTRLS_RCAGNT BIT(4)
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#define B53_SRAB_CTRLS_SW_INIT_DONE BIT(6)
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/* the register captures interrupt pulses from the switch */
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#define B53_SRAB_INTR 0x44
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#define B53_SRAB_INTR_P(x) BIT(x)
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#define B53_SRAB_SWITCH_PHY BIT(8)
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#define B53_SRAB_1588_SYNC BIT(9)
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#define B53_SRAB_IMP1_SLEEP_TIMER BIT(10)
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#define B53_SRAB_P7_SLEEP_TIMER BIT(11)
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#define B53_SRAB_IMP0_SLEEP_TIMER BIT(12)
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struct b53_srab_priv {
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void __iomem *regs;
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};
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static int b53_srab_request_grant(struct b53_device *dev)
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{
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struct b53_srab_priv *priv = dev->priv;
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u8 __iomem *regs = priv->regs;
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u32 ctrls;
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int i;
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ctrls = readl(regs + B53_SRAB_CTRLS);
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ctrls |= B53_SRAB_CTRLS_RCAREQ;
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writel(ctrls, regs + B53_SRAB_CTRLS);
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for (i = 0; i < 20; i++) {
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ctrls = readl(regs + B53_SRAB_CTRLS);
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if (ctrls & B53_SRAB_CTRLS_RCAGNT)
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break;
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usleep_range(10, 100);
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}
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if (WARN_ON(i == 5))
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return -EIO;
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return 0;
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}
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static void b53_srab_release_grant(struct b53_device *dev)
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{
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struct b53_srab_priv *priv = dev->priv;
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u8 __iomem *regs = priv->regs;
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u32 ctrls;
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ctrls = readl(regs + B53_SRAB_CTRLS);
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ctrls &= ~B53_SRAB_CTRLS_RCAREQ;
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writel(ctrls, regs + B53_SRAB_CTRLS);
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}
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static int b53_srab_op(struct b53_device *dev, u8 page, u8 reg, u32 op)
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{
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struct b53_srab_priv *priv = dev->priv;
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u8 __iomem *regs = priv->regs;
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int i;
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u32 cmdstat;
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/* set register address */
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cmdstat = (page << B53_SRAB_CMDSTAT_PAGE) |
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(reg << B53_SRAB_CMDSTAT_REG) |
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B53_SRAB_CMDSTAT_GORDYN |
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op;
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writel(cmdstat, regs + B53_SRAB_CMDSTAT);
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/* check if operation completed */
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for (i = 0; i < 5; ++i) {
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cmdstat = readl(regs + B53_SRAB_CMDSTAT);
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if (!(cmdstat & B53_SRAB_CMDSTAT_GORDYN))
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break;
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usleep_range(10, 100);
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}
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if (WARN_ON(i == 5))
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return -EIO;
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return 0;
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}
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static int b53_srab_read8(struct b53_device *dev, u8 page, u8 reg, u8 *val)
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{
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struct b53_srab_priv *priv = dev->priv;
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u8 __iomem *regs = priv->regs;
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int ret = 0;
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ret = b53_srab_request_grant(dev);
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if (ret)
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goto err;
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ret = b53_srab_op(dev, page, reg, 0);
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if (ret)
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goto err;
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*val = readl(regs + B53_SRAB_RD_L) & 0xff;
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err:
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b53_srab_release_grant(dev);
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return ret;
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}
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static int b53_srab_read16(struct b53_device *dev, u8 page, u8 reg, u16 *val)
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{
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struct b53_srab_priv *priv = dev->priv;
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u8 __iomem *regs = priv->regs;
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int ret = 0;
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ret = b53_srab_request_grant(dev);
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if (ret)
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goto err;
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ret = b53_srab_op(dev, page, reg, 0);
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if (ret)
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goto err;
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*val = readl(regs + B53_SRAB_RD_L) & 0xffff;
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err:
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b53_srab_release_grant(dev);
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return ret;
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}
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static int b53_srab_read32(struct b53_device *dev, u8 page, u8 reg, u32 *val)
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{
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struct b53_srab_priv *priv = dev->priv;
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u8 __iomem *regs = priv->regs;
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int ret = 0;
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ret = b53_srab_request_grant(dev);
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if (ret)
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goto err;
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ret = b53_srab_op(dev, page, reg, 0);
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if (ret)
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goto err;
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*val = readl(regs + B53_SRAB_RD_L);
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err:
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b53_srab_release_grant(dev);
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return ret;
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}
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static int b53_srab_read48(struct b53_device *dev, u8 page, u8 reg, u64 *val)
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{
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struct b53_srab_priv *priv = dev->priv;
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u8 __iomem *regs = priv->regs;
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int ret = 0;
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ret = b53_srab_request_grant(dev);
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if (ret)
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goto err;
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ret = b53_srab_op(dev, page, reg, 0);
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if (ret)
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goto err;
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*val = readl(regs + B53_SRAB_RD_L);
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*val += ((u64)readl(regs + B53_SRAB_RD_H) & 0xffff) << 32;
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err:
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b53_srab_release_grant(dev);
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return ret;
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}
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static int b53_srab_read64(struct b53_device *dev, u8 page, u8 reg, u64 *val)
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{
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struct b53_srab_priv *priv = dev->priv;
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u8 __iomem *regs = priv->regs;
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int ret = 0;
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ret = b53_srab_request_grant(dev);
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if (ret)
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goto err;
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ret = b53_srab_op(dev, page, reg, 0);
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if (ret)
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goto err;
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*val = readl(regs + B53_SRAB_RD_L);
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*val += (u64)readl(regs + B53_SRAB_RD_H) << 32;
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err:
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b53_srab_release_grant(dev);
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return ret;
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}
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static int b53_srab_write8(struct b53_device *dev, u8 page, u8 reg, u8 value)
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{
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struct b53_srab_priv *priv = dev->priv;
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u8 __iomem *regs = priv->regs;
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int ret = 0;
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ret = b53_srab_request_grant(dev);
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if (ret)
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goto err;
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writel(value, regs + B53_SRAB_WD_L);
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ret = b53_srab_op(dev, page, reg, B53_SRAB_CMDSTAT_WRITE);
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err:
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b53_srab_release_grant(dev);
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return ret;
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}
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static int b53_srab_write16(struct b53_device *dev, u8 page, u8 reg,
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u16 value)
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{
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struct b53_srab_priv *priv = dev->priv;
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u8 __iomem *regs = priv->regs;
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int ret = 0;
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ret = b53_srab_request_grant(dev);
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if (ret)
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goto err;
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writel(value, regs + B53_SRAB_WD_L);
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ret = b53_srab_op(dev, page, reg, B53_SRAB_CMDSTAT_WRITE);
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err:
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b53_srab_release_grant(dev);
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return ret;
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}
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static int b53_srab_write32(struct b53_device *dev, u8 page, u8 reg,
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u32 value)
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{
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struct b53_srab_priv *priv = dev->priv;
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u8 __iomem *regs = priv->regs;
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int ret = 0;
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ret = b53_srab_request_grant(dev);
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if (ret)
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goto err;
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writel(value, regs + B53_SRAB_WD_L);
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ret = b53_srab_op(dev, page, reg, B53_SRAB_CMDSTAT_WRITE);
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err:
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b53_srab_release_grant(dev);
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return ret;
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}
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static int b53_srab_write48(struct b53_device *dev, u8 page, u8 reg,
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u64 value)
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{
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struct b53_srab_priv *priv = dev->priv;
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u8 __iomem *regs = priv->regs;
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int ret = 0;
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ret = b53_srab_request_grant(dev);
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if (ret)
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goto err;
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writel((u32)value, regs + B53_SRAB_WD_L);
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writel((u16)(value >> 32), regs + B53_SRAB_WD_H);
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ret = b53_srab_op(dev, page, reg, B53_SRAB_CMDSTAT_WRITE);
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err:
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b53_srab_release_grant(dev);
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return ret;
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}
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static int b53_srab_write64(struct b53_device *dev, u8 page, u8 reg,
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u64 value)
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{
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struct b53_srab_priv *priv = dev->priv;
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u8 __iomem *regs = priv->regs;
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int ret = 0;
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ret = b53_srab_request_grant(dev);
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if (ret)
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goto err;
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writel((u32)value, regs + B53_SRAB_WD_L);
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writel((u32)(value >> 32), regs + B53_SRAB_WD_H);
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ret = b53_srab_op(dev, page, reg, B53_SRAB_CMDSTAT_WRITE);
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err:
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b53_srab_release_grant(dev);
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return ret;
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}
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static const struct b53_io_ops b53_srab_ops = {
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.read8 = b53_srab_read8,
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.read16 = b53_srab_read16,
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.read32 = b53_srab_read32,
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.read48 = b53_srab_read48,
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.read64 = b53_srab_read64,
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.write8 = b53_srab_write8,
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.write16 = b53_srab_write16,
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.write32 = b53_srab_write32,
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.write48 = b53_srab_write48,
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.write64 = b53_srab_write64,
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};
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static const struct of_device_id b53_srab_of_match[] = {
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{ .compatible = "brcm,bcm53010-srab" },
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{ .compatible = "brcm,bcm53011-srab" },
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{ .compatible = "brcm,bcm53012-srab" },
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{ .compatible = "brcm,bcm53018-srab" },
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{ .compatible = "brcm,bcm53019-srab" },
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{ .compatible = "brcm,bcm5301x-srab" },
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{ .compatible = "brcm,bcm58522-srab", .data = (void *)BCM58XX_DEVICE_ID },
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{ .compatible = "brcm,bcm58525-srab", .data = (void *)BCM58XX_DEVICE_ID },
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{ .compatible = "brcm,bcm58535-srab", .data = (void *)BCM58XX_DEVICE_ID },
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{ .compatible = "brcm,bcm58622-srab", .data = (void *)BCM58XX_DEVICE_ID },
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{ .compatible = "brcm,bcm58623-srab", .data = (void *)BCM58XX_DEVICE_ID },
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{ .compatible = "brcm,bcm58625-srab", .data = (void *)BCM58XX_DEVICE_ID },
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{ .compatible = "brcm,bcm88312-srab", .data = (void *)BCM58XX_DEVICE_ID },
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{ .compatible = "brcm,nsp-srab", .data = (void *)BCM58XX_DEVICE_ID },
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{ /* sentinel */ },
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};
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MODULE_DEVICE_TABLE(of, b53_srab_of_match);
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static int b53_srab_probe(struct platform_device *pdev)
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{
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struct b53_platform_data *pdata = pdev->dev.platform_data;
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struct device_node *dn = pdev->dev.of_node;
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const struct of_device_id *of_id = NULL;
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struct b53_srab_priv *priv;
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struct b53_device *dev;
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struct resource *r;
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if (dn)
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of_id = of_match_node(b53_srab_of_match, dn);
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if (of_id) {
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pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
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if (!pdata)
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return -ENOMEM;
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pdata->chip_id = (u32)(unsigned long)of_id->data;
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}
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priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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priv->regs = devm_ioremap_resource(&pdev->dev, r);
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if (IS_ERR(priv->regs))
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return -ENOMEM;
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dev = b53_switch_alloc(&pdev->dev, &b53_srab_ops, priv);
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if (!dev)
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return -ENOMEM;
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if (pdata)
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dev->pdata = pdata;
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platform_set_drvdata(pdev, dev);
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return b53_switch_register(dev);
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}
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static int b53_srab_remove(struct platform_device *pdev)
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{
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struct b53_device *dev = platform_get_drvdata(pdev);
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if (dev)
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b53_switch_remove(dev);
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return 0;
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}
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static struct platform_driver b53_srab_driver = {
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.probe = b53_srab_probe,
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.remove = b53_srab_remove,
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.driver = {
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.name = "b53-srab-switch",
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.of_match_table = b53_srab_of_match,
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},
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};
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module_platform_driver(b53_srab_driver);
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MODULE_AUTHOR("Hauke Mehrtens <hauke@hauke-m.de>");
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MODULE_DESCRIPTION("B53 Switch Register Access Bridge Registers (SRAB) access driver");
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MODULE_LICENSE("Dual BSD/GPL");
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