1204 lines
30 KiB
C
1204 lines
30 KiB
C
/*
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* Broadcom Starfighter 2 DSA switch driver
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*
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* Copyright (C) 2014, Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/list.h>
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#include <linux/module.h>
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#include <linux/netdevice.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/phy.h>
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#include <linux/phy_fixed.h>
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#include <linux/mii.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/of_net.h>
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#include <linux/of_mdio.h>
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#include <net/dsa.h>
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#include <linux/ethtool.h>
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#include <linux/if_bridge.h>
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#include <linux/brcmphy.h>
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#include <linux/etherdevice.h>
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#include <net/switchdev.h>
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#include <linux/platform_data/b53.h>
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#include "bcm_sf2.h"
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#include "bcm_sf2_regs.h"
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#include "b53/b53_priv.h"
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#include "b53/b53_regs.h"
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static enum dsa_tag_protocol bcm_sf2_sw_get_tag_protocol(struct dsa_switch *ds)
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{
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return DSA_TAG_PROTO_BRCM;
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}
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static void bcm_sf2_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
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{
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struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
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unsigned int i;
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u32 reg;
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/* Enable the IMP Port to be in the same VLAN as the other ports
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* on a per-port basis such that we only have Port i and IMP in
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* the same VLAN.
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*/
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for (i = 0; i < priv->hw_params.num_ports; i++) {
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if (!((1 << i) & ds->enabled_port_mask))
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continue;
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reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i));
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reg |= (1 << cpu_port);
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core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i));
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}
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}
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static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
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{
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struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
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u32 reg, val;
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/* Enable the port memories */
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reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
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reg &= ~P_TXQ_PSM_VDD(port);
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core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
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/* Enable Broadcast, Multicast, Unicast forwarding to IMP port */
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reg = core_readl(priv, CORE_IMP_CTL);
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reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);
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reg &= ~(RX_DIS | TX_DIS);
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core_writel(priv, reg, CORE_IMP_CTL);
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/* Enable forwarding */
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core_writel(priv, SW_FWDG_EN, CORE_SWMODE);
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/* Enable IMP port in dumb mode */
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reg = core_readl(priv, CORE_SWITCH_CTRL);
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reg |= MII_DUMB_FWDG_EN;
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core_writel(priv, reg, CORE_SWITCH_CTRL);
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/* Resolve which bit controls the Broadcom tag */
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switch (port) {
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case 8:
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val = BRCM_HDR_EN_P8;
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break;
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case 7:
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val = BRCM_HDR_EN_P7;
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break;
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case 5:
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val = BRCM_HDR_EN_P5;
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break;
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default:
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val = 0;
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break;
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}
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/* Enable Broadcom tags for IMP port */
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reg = core_readl(priv, CORE_BRCM_HDR_CTRL);
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reg |= val;
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core_writel(priv, reg, CORE_BRCM_HDR_CTRL);
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/* Enable reception Broadcom tag for CPU TX (switch RX) to
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* allow us to tag outgoing frames
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*/
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reg = core_readl(priv, CORE_BRCM_HDR_RX_DIS);
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reg &= ~(1 << port);
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core_writel(priv, reg, CORE_BRCM_HDR_RX_DIS);
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/* Enable transmission of Broadcom tags from the switch (CPU RX) to
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* allow delivering frames to the per-port net_devices
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*/
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reg = core_readl(priv, CORE_BRCM_HDR_TX_DIS);
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reg &= ~(1 << port);
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core_writel(priv, reg, CORE_BRCM_HDR_TX_DIS);
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/* Force link status for IMP port */
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reg = core_readl(priv, CORE_STS_OVERRIDE_IMP);
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reg |= (MII_SW_OR | LINK_STS);
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core_writel(priv, reg, CORE_STS_OVERRIDE_IMP);
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}
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static void bcm_sf2_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
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{
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struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
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u32 reg;
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reg = core_readl(priv, CORE_EEE_EN_CTRL);
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if (enable)
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reg |= 1 << port;
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else
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reg &= ~(1 << port);
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core_writel(priv, reg, CORE_EEE_EN_CTRL);
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}
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static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable)
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{
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struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
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u32 reg;
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reg = reg_readl(priv, REG_SPHY_CNTRL);
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if (enable) {
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reg |= PHY_RESET;
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reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | CK25_DIS);
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reg_writel(priv, reg, REG_SPHY_CNTRL);
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udelay(21);
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reg = reg_readl(priv, REG_SPHY_CNTRL);
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reg &= ~PHY_RESET;
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} else {
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reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET;
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reg_writel(priv, reg, REG_SPHY_CNTRL);
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mdelay(1);
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reg |= CK25_DIS;
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}
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reg_writel(priv, reg, REG_SPHY_CNTRL);
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/* Use PHY-driven LED signaling */
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if (!enable) {
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reg = reg_readl(priv, REG_LED_CNTRL(0));
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reg |= SPDLNK_SRC_SEL;
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reg_writel(priv, reg, REG_LED_CNTRL(0));
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}
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}
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static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv,
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int port)
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{
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unsigned int off;
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switch (port) {
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case 7:
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off = P7_IRQ_OFF;
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break;
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case 0:
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/* Port 0 interrupts are located on the first bank */
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intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF));
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return;
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default:
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off = P_IRQ_OFF(port);
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break;
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}
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intrl2_1_mask_clear(priv, P_IRQ_MASK(off));
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}
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static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv,
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int port)
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{
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unsigned int off;
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switch (port) {
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case 7:
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off = P7_IRQ_OFF;
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break;
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case 0:
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/* Port 0 interrupts are located on the first bank */
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intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF));
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intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR);
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return;
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default:
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off = P_IRQ_OFF(port);
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break;
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}
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intrl2_1_mask_set(priv, P_IRQ_MASK(off));
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intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR);
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}
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static int bcm_sf2_port_setup(struct dsa_switch *ds, int port,
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struct phy_device *phy)
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{
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struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
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s8 cpu_port = ds->dst[ds->index].cpu_port;
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u32 reg;
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/* Clear the memory power down */
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reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
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reg &= ~P_TXQ_PSM_VDD(port);
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core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
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/* Clear the Rx and Tx disable bits and set to no spanning tree */
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core_writel(priv, 0, CORE_G_PCTL_PORT(port));
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/* Re-enable the GPHY and re-apply workarounds */
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if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) {
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bcm_sf2_gphy_enable_set(ds, true);
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if (phy) {
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/* if phy_stop() has been called before, phy
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* will be in halted state, and phy_start()
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* will call resume.
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*
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* the resume path does not configure back
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* autoneg settings, and since we hard reset
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* the phy manually here, we need to reset the
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* state machine also.
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*/
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phy->state = PHY_READY;
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phy_init_hw(phy);
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}
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}
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/* Enable MoCA port interrupts to get notified */
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if (port == priv->moca_port)
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bcm_sf2_port_intr_enable(priv, port);
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/* Set this port, and only this one to be in the default VLAN,
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* if member of a bridge, restore its membership prior to
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* bringing down this port.
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*/
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reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port));
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reg &= ~PORT_VLAN_CTRL_MASK;
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reg |= (1 << port);
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reg |= priv->dev->ports[port].vlan_ctl_mask;
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core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(port));
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bcm_sf2_imp_vlan_setup(ds, cpu_port);
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/* If EEE was enabled, restore it */
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if (priv->port_sts[port].eee.eee_enabled)
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bcm_sf2_eee_enable_set(ds, port, true);
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return 0;
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}
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static void bcm_sf2_port_disable(struct dsa_switch *ds, int port,
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struct phy_device *phy)
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{
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struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
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u32 off, reg;
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if (priv->wol_ports_mask & (1 << port))
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return;
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if (port == priv->moca_port)
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bcm_sf2_port_intr_disable(priv, port);
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if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1)
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bcm_sf2_gphy_enable_set(ds, false);
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if (dsa_is_cpu_port(ds, port))
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off = CORE_IMP_CTL;
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else
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off = CORE_G_PCTL_PORT(port);
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reg = core_readl(priv, off);
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reg |= RX_DIS | TX_DIS;
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core_writel(priv, reg, off);
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/* Power down the port memory */
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reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
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reg |= P_TXQ_PSM_VDD(port);
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core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
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}
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/* Returns 0 if EEE was not enabled, or 1 otherwise
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*/
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static int bcm_sf2_eee_init(struct dsa_switch *ds, int port,
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struct phy_device *phy)
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{
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struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
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struct ethtool_eee *p = &priv->port_sts[port].eee;
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int ret;
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p->supported = (SUPPORTED_1000baseT_Full | SUPPORTED_100baseT_Full);
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ret = phy_init_eee(phy, 0);
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if (ret)
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return 0;
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bcm_sf2_eee_enable_set(ds, port, true);
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return 1;
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}
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static int bcm_sf2_sw_get_eee(struct dsa_switch *ds, int port,
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struct ethtool_eee *e)
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{
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struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
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struct ethtool_eee *p = &priv->port_sts[port].eee;
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u32 reg;
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reg = core_readl(priv, CORE_EEE_LPI_INDICATE);
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e->eee_enabled = p->eee_enabled;
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e->eee_active = !!(reg & (1 << port));
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return 0;
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}
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static int bcm_sf2_sw_set_eee(struct dsa_switch *ds, int port,
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struct phy_device *phydev,
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struct ethtool_eee *e)
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{
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struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
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struct ethtool_eee *p = &priv->port_sts[port].eee;
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p->eee_enabled = e->eee_enabled;
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if (!p->eee_enabled) {
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bcm_sf2_eee_enable_set(ds, port, false);
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} else {
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p->eee_enabled = bcm_sf2_eee_init(ds, port, phydev);
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if (!p->eee_enabled)
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return -EOPNOTSUPP;
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}
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return 0;
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}
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static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr,
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int regnum, u16 val)
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{
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int ret = 0;
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u32 reg;
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reg = reg_readl(priv, REG_SWITCH_CNTRL);
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reg |= MDIO_MASTER_SEL;
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reg_writel(priv, reg, REG_SWITCH_CNTRL);
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/* Page << 8 | offset */
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reg = 0x70;
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reg <<= 2;
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core_writel(priv, addr, reg);
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/* Page << 8 | offset */
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reg = 0x80 << 8 | regnum << 1;
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reg <<= 2;
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if (op)
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ret = core_readl(priv, reg);
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else
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core_writel(priv, val, reg);
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reg = reg_readl(priv, REG_SWITCH_CNTRL);
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reg &= ~MDIO_MASTER_SEL;
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reg_writel(priv, reg, REG_SWITCH_CNTRL);
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return ret & 0xffff;
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}
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static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
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{
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struct bcm_sf2_priv *priv = bus->priv;
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/* Intercept reads from Broadcom pseudo-PHY address, else, send
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* them to our master MDIO bus controller
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*/
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if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
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return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0);
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else
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return mdiobus_read_nested(priv->master_mii_bus, addr, regnum);
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}
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static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
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u16 val)
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{
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struct bcm_sf2_priv *priv = bus->priv;
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/* Intercept writes to the Broadcom pseudo-PHY address, else,
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* send them to our master MDIO bus controller
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*/
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if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
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return bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val);
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else
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return mdiobus_write_nested(priv->master_mii_bus, addr,
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regnum, val);
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}
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static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
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{
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struct bcm_sf2_priv *priv = dev_id;
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priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
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~priv->irq0_mask;
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intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
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return IRQ_HANDLED;
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}
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static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id)
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{
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struct bcm_sf2_priv *priv = dev_id;
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priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
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~priv->irq1_mask;
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intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
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if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF))
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priv->port_sts[7].link = 1;
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if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF))
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priv->port_sts[7].link = 0;
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return IRQ_HANDLED;
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}
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static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv)
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{
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unsigned int timeout = 1000;
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u32 reg;
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reg = core_readl(priv, CORE_WATCHDOG_CTRL);
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reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET;
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core_writel(priv, reg, CORE_WATCHDOG_CTRL);
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do {
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reg = core_readl(priv, CORE_WATCHDOG_CTRL);
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if (!(reg & SOFTWARE_RESET))
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break;
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usleep_range(1000, 2000);
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} while (timeout-- > 0);
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if (timeout == 0)
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return -ETIMEDOUT;
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return 0;
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}
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static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv)
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{
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intrl2_0_mask_set(priv, 0xffffffff);
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intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
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intrl2_1_mask_set(priv, 0xffffffff);
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intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
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}
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static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv,
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struct device_node *dn)
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{
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struct device_node *port;
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const char *phy_mode_str;
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int mode;
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unsigned int port_num;
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int ret;
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priv->moca_port = -1;
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|
|
for_each_available_child_of_node(dn, port) {
|
|
if (of_property_read_u32(port, "reg", &port_num))
|
|
continue;
|
|
|
|
/* Internal PHYs get assigned a specific 'phy-mode' property
|
|
* value: "internal" to help flag them before MDIO probing
|
|
* has completed, since they might be turned off at that
|
|
* time
|
|
*/
|
|
mode = of_get_phy_mode(port);
|
|
if (mode < 0) {
|
|
ret = of_property_read_string(port, "phy-mode",
|
|
&phy_mode_str);
|
|
if (ret < 0)
|
|
continue;
|
|
|
|
if (!strcasecmp(phy_mode_str, "internal"))
|
|
priv->int_phy_mask |= 1 << port_num;
|
|
}
|
|
|
|
if (mode == PHY_INTERFACE_MODE_MOCA)
|
|
priv->moca_port = port_num;
|
|
}
|
|
}
|
|
|
|
static int bcm_sf2_mdio_register(struct dsa_switch *ds)
|
|
{
|
|
struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
|
|
struct device_node *dn;
|
|
static int index;
|
|
int err;
|
|
|
|
/* Find our integrated MDIO bus node */
|
|
dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio");
|
|
priv->master_mii_bus = of_mdio_find_bus(dn);
|
|
if (!priv->master_mii_bus)
|
|
return -EPROBE_DEFER;
|
|
|
|
get_device(&priv->master_mii_bus->dev);
|
|
priv->master_mii_dn = dn;
|
|
|
|
priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev);
|
|
if (!priv->slave_mii_bus)
|
|
return -ENOMEM;
|
|
|
|
priv->slave_mii_bus->priv = priv;
|
|
priv->slave_mii_bus->name = "sf2 slave mii";
|
|
priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read;
|
|
priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write;
|
|
snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d",
|
|
index++);
|
|
priv->slave_mii_bus->dev.of_node = dn;
|
|
|
|
/* Include the pseudo-PHY address to divert reads towards our
|
|
* workaround. This is only required for 7445D0, since 7445E0
|
|
* disconnects the internal switch pseudo-PHY such that we can use the
|
|
* regular SWITCH_MDIO master controller instead.
|
|
*
|
|
* Here we flag the pseudo PHY as needing special treatment and would
|
|
* otherwise make all other PHY read/writes go to the master MDIO bus
|
|
* controller that comes with this switch backed by the "mdio-unimac"
|
|
* driver.
|
|
*/
|
|
if (of_machine_is_compatible("brcm,bcm7445d0"))
|
|
priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR);
|
|
else
|
|
priv->indir_phy_mask = 0;
|
|
|
|
ds->phys_mii_mask = priv->indir_phy_mask;
|
|
ds->slave_mii_bus = priv->slave_mii_bus;
|
|
priv->slave_mii_bus->parent = ds->dev->parent;
|
|
priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask;
|
|
|
|
if (dn)
|
|
err = of_mdiobus_register(priv->slave_mii_bus, dn);
|
|
else
|
|
err = mdiobus_register(priv->slave_mii_bus);
|
|
|
|
if (err)
|
|
of_node_put(dn);
|
|
|
|
return err;
|
|
}
|
|
|
|
static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv)
|
|
{
|
|
mdiobus_unregister(priv->slave_mii_bus);
|
|
if (priv->master_mii_dn)
|
|
of_node_put(priv->master_mii_dn);
|
|
}
|
|
|
|
static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port)
|
|
{
|
|
struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
|
|
|
|
/* The BCM7xxx PHY driver expects to find the integrated PHY revision
|
|
* in bits 15:8 and the patch level in bits 7:0 which is exactly what
|
|
* the REG_PHY_REVISION register layout is.
|
|
*/
|
|
|
|
return priv->hw_params.gphy_rev;
|
|
}
|
|
|
|
static void bcm_sf2_sw_adjust_link(struct dsa_switch *ds, int port,
|
|
struct phy_device *phydev)
|
|
{
|
|
struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
|
|
struct ethtool_eee *p = &priv->port_sts[port].eee;
|
|
u32 id_mode_dis = 0, port_mode;
|
|
const char *str = NULL;
|
|
u32 reg;
|
|
|
|
switch (phydev->interface) {
|
|
case PHY_INTERFACE_MODE_RGMII:
|
|
str = "RGMII (no delay)";
|
|
id_mode_dis = 1;
|
|
case PHY_INTERFACE_MODE_RGMII_TXID:
|
|
if (!str)
|
|
str = "RGMII (TX delay)";
|
|
port_mode = EXT_GPHY;
|
|
break;
|
|
case PHY_INTERFACE_MODE_MII:
|
|
str = "MII";
|
|
port_mode = EXT_EPHY;
|
|
break;
|
|
case PHY_INTERFACE_MODE_REVMII:
|
|
str = "Reverse MII";
|
|
port_mode = EXT_REVMII;
|
|
break;
|
|
default:
|
|
/* All other PHYs: internal and MoCA */
|
|
goto force_link;
|
|
}
|
|
|
|
/* If the link is down, just disable the interface to conserve power */
|
|
if (!phydev->link) {
|
|
reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
|
|
reg &= ~RGMII_MODE_EN;
|
|
reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
|
|
goto force_link;
|
|
}
|
|
|
|
/* Clear id_mode_dis bit, and the existing port mode, but
|
|
* make sure we enable the RGMII block for data to pass
|
|
*/
|
|
reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
|
|
reg &= ~ID_MODE_DIS;
|
|
reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
|
|
reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
|
|
|
|
reg |= port_mode | RGMII_MODE_EN;
|
|
if (id_mode_dis)
|
|
reg |= ID_MODE_DIS;
|
|
|
|
if (phydev->pause) {
|
|
if (phydev->asym_pause)
|
|
reg |= TX_PAUSE_EN;
|
|
reg |= RX_PAUSE_EN;
|
|
}
|
|
|
|
reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
|
|
|
|
pr_info("Port %d configured for %s\n", port, str);
|
|
|
|
force_link:
|
|
/* Force link settings detected from the PHY */
|
|
reg = SW_OVERRIDE;
|
|
switch (phydev->speed) {
|
|
case SPEED_1000:
|
|
reg |= SPDSTS_1000 << SPEED_SHIFT;
|
|
break;
|
|
case SPEED_100:
|
|
reg |= SPDSTS_100 << SPEED_SHIFT;
|
|
break;
|
|
}
|
|
|
|
if (phydev->link)
|
|
reg |= LINK_STS;
|
|
if (phydev->duplex == DUPLEX_FULL)
|
|
reg |= DUPLX_MODE;
|
|
|
|
core_writel(priv, reg, CORE_STS_OVERRIDE_GMIIP_PORT(port));
|
|
|
|
if (!phydev->is_pseudo_fixed_link)
|
|
p->eee_enabled = bcm_sf2_eee_init(ds, port, phydev);
|
|
}
|
|
|
|
static void bcm_sf2_sw_fixed_link_update(struct dsa_switch *ds, int port,
|
|
struct fixed_phy_status *status)
|
|
{
|
|
struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
|
|
u32 duplex, pause;
|
|
u32 reg;
|
|
|
|
duplex = core_readl(priv, CORE_DUPSTS);
|
|
pause = core_readl(priv, CORE_PAUSESTS);
|
|
|
|
status->link = 0;
|
|
|
|
/* MoCA port is special as we do not get link status from CORE_LNKSTS,
|
|
* which means that we need to force the link at the port override
|
|
* level to get the data to flow. We do use what the interrupt handler
|
|
* did determine before.
|
|
*
|
|
* For the other ports, we just force the link status, since this is
|
|
* a fixed PHY device.
|
|
*/
|
|
if (port == priv->moca_port) {
|
|
status->link = priv->port_sts[port].link;
|
|
/* For MoCA interfaces, also force a link down notification
|
|
* since some version of the user-space daemon (mocad) use
|
|
* cmd->autoneg to force the link, which messes up the PHY
|
|
* state machine and make it go in PHY_FORCING state instead.
|
|
*/
|
|
if (!status->link)
|
|
netif_carrier_off(ds->ports[port].netdev);
|
|
status->duplex = 1;
|
|
} else {
|
|
status->link = 1;
|
|
status->duplex = !!(duplex & (1 << port));
|
|
}
|
|
|
|
reg = core_readl(priv, CORE_STS_OVERRIDE_GMIIP_PORT(port));
|
|
reg |= SW_OVERRIDE;
|
|
if (status->link)
|
|
reg |= LINK_STS;
|
|
else
|
|
reg &= ~LINK_STS;
|
|
core_writel(priv, reg, CORE_STS_OVERRIDE_GMIIP_PORT(port));
|
|
|
|
if ((pause & (1 << port)) &&
|
|
(pause & (1 << (port + PAUSESTS_TX_PAUSE_SHIFT)))) {
|
|
status->asym_pause = 1;
|
|
status->pause = 1;
|
|
}
|
|
|
|
if (pause & (1 << port))
|
|
status->pause = 1;
|
|
}
|
|
|
|
static int bcm_sf2_sw_suspend(struct dsa_switch *ds)
|
|
{
|
|
struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
|
|
unsigned int port;
|
|
|
|
bcm_sf2_intr_disable(priv);
|
|
|
|
/* Disable all ports physically present including the IMP
|
|
* port, the other ones have already been disabled during
|
|
* bcm_sf2_sw_setup
|
|
*/
|
|
for (port = 0; port < DSA_MAX_PORTS; port++) {
|
|
if ((1 << port) & ds->enabled_port_mask ||
|
|
dsa_is_cpu_port(ds, port))
|
|
bcm_sf2_port_disable(ds, port, NULL);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int bcm_sf2_sw_resume(struct dsa_switch *ds)
|
|
{
|
|
struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
|
|
int ret;
|
|
|
|
ret = bcm_sf2_sw_rst(priv);
|
|
if (ret) {
|
|
pr_err("%s: failed to software reset switch\n", __func__);
|
|
return ret;
|
|
}
|
|
|
|
if (priv->hw_params.num_gphy == 1)
|
|
bcm_sf2_gphy_enable_set(ds, true);
|
|
|
|
ds->ops->setup(ds);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port,
|
|
struct ethtool_wolinfo *wol)
|
|
{
|
|
struct net_device *p = ds->dst[ds->index].master_netdev;
|
|
struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
|
|
struct ethtool_wolinfo pwol;
|
|
|
|
/* Get the parent device WoL settings */
|
|
p->ethtool_ops->get_wol(p, &pwol);
|
|
|
|
/* Advertise the parent device supported settings */
|
|
wol->supported = pwol.supported;
|
|
memset(&wol->sopass, 0, sizeof(wol->sopass));
|
|
|
|
if (pwol.wolopts & WAKE_MAGICSECURE)
|
|
memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass));
|
|
|
|
if (priv->wol_ports_mask & (1 << port))
|
|
wol->wolopts = pwol.wolopts;
|
|
else
|
|
wol->wolopts = 0;
|
|
}
|
|
|
|
static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port,
|
|
struct ethtool_wolinfo *wol)
|
|
{
|
|
struct net_device *p = ds->dst[ds->index].master_netdev;
|
|
struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
|
|
s8 cpu_port = ds->dst[ds->index].cpu_port;
|
|
struct ethtool_wolinfo pwol;
|
|
|
|
p->ethtool_ops->get_wol(p, &pwol);
|
|
if (wol->wolopts & ~pwol.supported)
|
|
return -EINVAL;
|
|
|
|
if (wol->wolopts)
|
|
priv->wol_ports_mask |= (1 << port);
|
|
else
|
|
priv->wol_ports_mask &= ~(1 << port);
|
|
|
|
/* If we have at least one port enabled, make sure the CPU port
|
|
* is also enabled. If the CPU port is the last one enabled, we disable
|
|
* it since this configuration does not make sense.
|
|
*/
|
|
if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port))
|
|
priv->wol_ports_mask |= (1 << cpu_port);
|
|
else
|
|
priv->wol_ports_mask &= ~(1 << cpu_port);
|
|
|
|
return p->ethtool_ops->set_wol(p, wol);
|
|
}
|
|
|
|
static int bcm_sf2_vlan_op_wait(struct bcm_sf2_priv *priv)
|
|
{
|
|
unsigned int timeout = 10;
|
|
u32 reg;
|
|
|
|
do {
|
|
reg = core_readl(priv, CORE_ARLA_VTBL_RWCTRL);
|
|
if (!(reg & ARLA_VTBL_STDN))
|
|
return 0;
|
|
|
|
usleep_range(1000, 2000);
|
|
} while (timeout--);
|
|
|
|
return -ETIMEDOUT;
|
|
}
|
|
|
|
static int bcm_sf2_vlan_op(struct bcm_sf2_priv *priv, u8 op)
|
|
{
|
|
core_writel(priv, ARLA_VTBL_STDN | op, CORE_ARLA_VTBL_RWCTRL);
|
|
|
|
return bcm_sf2_vlan_op_wait(priv);
|
|
}
|
|
|
|
static void bcm_sf2_sw_configure_vlan(struct dsa_switch *ds)
|
|
{
|
|
struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
|
|
unsigned int port;
|
|
|
|
/* Clear all VLANs */
|
|
bcm_sf2_vlan_op(priv, ARLA_VTBL_CMD_CLEAR);
|
|
|
|
for (port = 0; port < priv->hw_params.num_ports; port++) {
|
|
if (!((1 << port) & ds->enabled_port_mask))
|
|
continue;
|
|
|
|
core_writel(priv, 1, CORE_DEFAULT_1Q_TAG_P(port));
|
|
}
|
|
}
|
|
|
|
static int bcm_sf2_sw_setup(struct dsa_switch *ds)
|
|
{
|
|
struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
|
|
unsigned int port;
|
|
|
|
/* Enable all valid ports and disable those unused */
|
|
for (port = 0; port < priv->hw_params.num_ports; port++) {
|
|
/* IMP port receives special treatment */
|
|
if ((1 << port) & ds->enabled_port_mask)
|
|
bcm_sf2_port_setup(ds, port, NULL);
|
|
else if (dsa_is_cpu_port(ds, port))
|
|
bcm_sf2_imp_setup(ds, port);
|
|
else
|
|
bcm_sf2_port_disable(ds, port, NULL);
|
|
}
|
|
|
|
bcm_sf2_sw_configure_vlan(ds);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* The SWITCH_CORE register space is managed by b53 but operates on a page +
|
|
* register basis so we need to translate that into an address that the
|
|
* bus-glue understands.
|
|
*/
|
|
#define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2)
|
|
|
|
static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg,
|
|
u8 *val)
|
|
{
|
|
struct bcm_sf2_priv *priv = dev->priv;
|
|
|
|
*val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg,
|
|
u16 *val)
|
|
{
|
|
struct bcm_sf2_priv *priv = dev->priv;
|
|
|
|
*val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg,
|
|
u32 *val)
|
|
{
|
|
struct bcm_sf2_priv *priv = dev->priv;
|
|
|
|
*val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg,
|
|
u64 *val)
|
|
{
|
|
struct bcm_sf2_priv *priv = dev->priv;
|
|
|
|
*val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg,
|
|
u8 value)
|
|
{
|
|
struct bcm_sf2_priv *priv = dev->priv;
|
|
|
|
core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg,
|
|
u16 value)
|
|
{
|
|
struct bcm_sf2_priv *priv = dev->priv;
|
|
|
|
core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg,
|
|
u32 value)
|
|
{
|
|
struct bcm_sf2_priv *priv = dev->priv;
|
|
|
|
core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg,
|
|
u64 value)
|
|
{
|
|
struct bcm_sf2_priv *priv = dev->priv;
|
|
|
|
core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct b53_io_ops bcm_sf2_io_ops = {
|
|
.read8 = bcm_sf2_core_read8,
|
|
.read16 = bcm_sf2_core_read16,
|
|
.read32 = bcm_sf2_core_read32,
|
|
.read48 = bcm_sf2_core_read64,
|
|
.read64 = bcm_sf2_core_read64,
|
|
.write8 = bcm_sf2_core_write8,
|
|
.write16 = bcm_sf2_core_write16,
|
|
.write32 = bcm_sf2_core_write32,
|
|
.write48 = bcm_sf2_core_write64,
|
|
.write64 = bcm_sf2_core_write64,
|
|
};
|
|
|
|
static int bcm_sf2_sw_probe(struct platform_device *pdev)
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{
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const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
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struct device_node *dn = pdev->dev.of_node;
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struct b53_platform_data *pdata;
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struct dsa_switch_ops *ops;
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struct device_node *ports;
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struct bcm_sf2_priv *priv;
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struct b53_device *dev;
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struct dsa_switch *ds;
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void __iomem **base;
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struct resource *r;
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unsigned int i;
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u32 reg, rev;
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int ret;
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priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL);
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if (!ops)
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return -ENOMEM;
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dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv);
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if (!dev)
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return -ENOMEM;
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pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
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if (!pdata)
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return -ENOMEM;
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/* Auto-detection using standard registers will not work, so
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* provide an indication of what kind of device we are for
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* b53_common to work with
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*/
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pdata->chip_id = BCM7445_DEVICE_ID;
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dev->pdata = pdata;
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priv->dev = dev;
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ds = dev->ds;
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/* Override the parts that are non-standard wrt. normal b53 devices */
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memcpy(ops, ds->ops, sizeof(*ops));
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ds->ops = ops;
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ds->ops->get_tag_protocol = bcm_sf2_sw_get_tag_protocol;
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ds->ops->setup = bcm_sf2_sw_setup;
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ds->ops->get_phy_flags = bcm_sf2_sw_get_phy_flags;
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ds->ops->adjust_link = bcm_sf2_sw_adjust_link;
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ds->ops->fixed_link_update = bcm_sf2_sw_fixed_link_update;
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ds->ops->suspend = bcm_sf2_sw_suspend;
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ds->ops->resume = bcm_sf2_sw_resume;
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ds->ops->get_wol = bcm_sf2_sw_get_wol;
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ds->ops->set_wol = bcm_sf2_sw_set_wol;
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ds->ops->port_enable = bcm_sf2_port_setup;
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ds->ops->port_disable = bcm_sf2_port_disable;
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ds->ops->get_eee = bcm_sf2_sw_get_eee;
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ds->ops->set_eee = bcm_sf2_sw_set_eee;
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/* Avoid having DSA free our slave MDIO bus (checking for
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* ds->slave_mii_bus and ds->ops->phy_read being non-NULL)
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*/
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ds->ops->phy_read = NULL;
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dev_set_drvdata(&pdev->dev, priv);
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spin_lock_init(&priv->indir_lock);
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mutex_init(&priv->stats_mutex);
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/* Balance of_node_put() done by of_find_node_by_name() */
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of_node_get(dn);
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ports = of_find_node_by_name(dn, "ports");
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if (ports) {
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bcm_sf2_identify_ports(priv, ports);
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of_node_put(ports);
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}
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priv->irq0 = irq_of_parse_and_map(dn, 0);
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priv->irq1 = irq_of_parse_and_map(dn, 1);
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base = &priv->core;
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for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
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r = platform_get_resource(pdev, IORESOURCE_MEM, i);
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*base = devm_ioremap_resource(&pdev->dev, r);
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if (IS_ERR(*base)) {
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pr_err("unable to find register: %s\n", reg_names[i]);
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return PTR_ERR(*base);
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}
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base++;
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}
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ret = bcm_sf2_sw_rst(priv);
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if (ret) {
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pr_err("unable to software reset switch: %d\n", ret);
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return ret;
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}
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ret = bcm_sf2_mdio_register(ds);
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if (ret) {
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pr_err("failed to register MDIO bus\n");
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return ret;
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}
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/* Disable all interrupts and request them */
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bcm_sf2_intr_disable(priv);
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ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0,
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"switch_0", priv);
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if (ret < 0) {
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pr_err("failed to request switch_0 IRQ\n");
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goto out_mdio;
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}
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ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0,
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"switch_1", priv);
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if (ret < 0) {
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pr_err("failed to request switch_1 IRQ\n");
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goto out_mdio;
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}
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/* Reset the MIB counters */
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reg = core_readl(priv, CORE_GMNCFGCFG);
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reg |= RST_MIB_CNT;
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core_writel(priv, reg, CORE_GMNCFGCFG);
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reg &= ~RST_MIB_CNT;
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core_writel(priv, reg, CORE_GMNCFGCFG);
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/* Get the maximum number of ports for this switch */
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priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;
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if (priv->hw_params.num_ports > DSA_MAX_PORTS)
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priv->hw_params.num_ports = DSA_MAX_PORTS;
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/* Assume a single GPHY setup if we can't read that property */
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if (of_property_read_u32(dn, "brcm,num-gphy",
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&priv->hw_params.num_gphy))
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priv->hw_params.num_gphy = 1;
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rev = reg_readl(priv, REG_SWITCH_REVISION);
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priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
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SWITCH_TOP_REV_MASK;
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priv->hw_params.core_rev = (rev & SF2_REV_MASK);
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rev = reg_readl(priv, REG_PHY_REVISION);
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priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
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ret = b53_switch_register(dev);
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if (ret)
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goto out_mdio;
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pr_info("Starfighter 2 top: %x.%02x, core: %x.%02x base: 0x%p, IRQs: %d, %d\n",
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priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
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priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
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priv->core, priv->irq0, priv->irq1);
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return 0;
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out_mdio:
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bcm_sf2_mdio_unregister(priv);
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return ret;
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}
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static int bcm_sf2_sw_remove(struct platform_device *pdev)
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{
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struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
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priv->wol_ports_mask = 0;
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dsa_unregister_switch(priv->dev->ds);
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/* Disable all ports and interrupts */
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bcm_sf2_sw_suspend(priv->dev->ds);
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bcm_sf2_mdio_unregister(priv);
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return 0;
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}
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static void bcm_sf2_sw_shutdown(struct platform_device *pdev)
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{
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struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
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/* For a kernel about to be kexec'd we want to keep the GPHY on for a
|
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* successful MDIO bus scan to occur. If we did turn off the GPHY
|
|
* before (e.g: port_disable), this will also power it back on.
|
|
*
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|
* Do not rely on kexec_in_progress, just power the PHY on.
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|
*/
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if (priv->hw_params.num_gphy == 1)
|
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bcm_sf2_gphy_enable_set(priv->dev->ds, true);
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}
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#ifdef CONFIG_PM_SLEEP
|
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static int bcm_sf2_suspend(struct device *dev)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(dev);
|
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struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
|
|
|
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return dsa_switch_suspend(priv->dev->ds);
|
|
}
|
|
|
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static int bcm_sf2_resume(struct device *dev)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(dev);
|
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struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
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return dsa_switch_resume(priv->dev->ds);
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}
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#endif /* CONFIG_PM_SLEEP */
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|
|
static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops,
|
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bcm_sf2_suspend, bcm_sf2_resume);
|
|
|
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static const struct of_device_id bcm_sf2_of_match[] = {
|
|
{ .compatible = "brcm,bcm7445-switch-v4.0" },
|
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{ /* sentinel */ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, bcm_sf2_of_match);
|
|
|
|
static struct platform_driver bcm_sf2_driver = {
|
|
.probe = bcm_sf2_sw_probe,
|
|
.remove = bcm_sf2_sw_remove,
|
|
.shutdown = bcm_sf2_sw_shutdown,
|
|
.driver = {
|
|
.name = "brcm-sf2",
|
|
.of_match_table = bcm_sf2_of_match,
|
|
.pm = &bcm_sf2_pm_ops,
|
|
},
|
|
};
|
|
module_platform_driver(bcm_sf2_driver);
|
|
|
|
MODULE_AUTHOR("Broadcom Corporation");
|
|
MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_ALIAS("platform:brcm-sf2");
|