791 lines
16 KiB
C
791 lines
16 KiB
C
#ifndef _ACENIC_H_
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#define _ACENIC_H_
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#include <linux/interrupt.h>
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/*
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* Generate TX index update each time, when TX ring is closed.
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* Normally, this is not useful, because results in more dma (and irqs
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* without TX_COAL_INTS_ONLY).
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*/
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#define USE_TX_COAL_NOW 0
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/*
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* Addressing:
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*
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* The Tigon uses 64-bit host addresses, regardless of their actual
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* length, and it expects a big-endian format. For 32 bit systems the
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* upper 32 bits of the address are simply ignored (zero), however for
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* little endian 64 bit systems (Alpha) this looks strange with the
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* two parts of the address word being swapped.
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*
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* The addresses are split in two 32 bit words for all architectures
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* as some of them are in PCI shared memory and it is necessary to use
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* readl/writel to access them.
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*
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* The addressing code is derived from Pete Wyckoff's work, but
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* modified to deal properly with readl/writel usage.
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*/
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struct ace_regs {
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u32 pad0[16]; /* PCI control registers */
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u32 HostCtrl; /* 0x40 */
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u32 LocalCtrl;
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u32 pad1[2];
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u32 MiscCfg; /* 0x50 */
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u32 pad2[2];
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u32 PciState;
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u32 pad3[2]; /* 0x60 */
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u32 WinBase;
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u32 WinData;
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u32 pad4[12]; /* 0x70 */
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u32 DmaWriteState; /* 0xa0 */
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u32 pad5[3];
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u32 DmaReadState; /* 0xb0 */
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u32 pad6[26];
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u32 AssistState;
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u32 pad7[8]; /* 0x120 */
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u32 CpuCtrl; /* 0x140 */
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u32 Pc;
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u32 pad8[3];
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u32 SramAddr; /* 0x154 */
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u32 SramData;
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u32 pad9[49];
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u32 MacRxState; /* 0x220 */
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u32 pad10[7];
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u32 CpuBCtrl; /* 0x240 */
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u32 PcB;
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u32 pad11[3];
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u32 SramBAddr; /* 0x254 */
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u32 SramBData;
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u32 pad12[105];
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u32 pad13[32]; /* 0x400 */
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u32 Stats[32];
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u32 Mb0Hi; /* 0x500 */
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u32 Mb0Lo;
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u32 Mb1Hi;
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u32 CmdPrd;
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u32 Mb2Hi;
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u32 TxPrd;
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u32 Mb3Hi;
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u32 RxStdPrd;
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u32 Mb4Hi;
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u32 RxJumboPrd;
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u32 Mb5Hi;
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u32 RxMiniPrd;
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u32 Mb6Hi;
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u32 Mb6Lo;
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u32 Mb7Hi;
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u32 Mb7Lo;
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u32 Mb8Hi;
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u32 Mb8Lo;
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u32 Mb9Hi;
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u32 Mb9Lo;
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u32 MbAHi;
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u32 MbALo;
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u32 MbBHi;
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u32 MbBLo;
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u32 MbCHi;
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u32 MbCLo;
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u32 MbDHi;
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u32 MbDLo;
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u32 MbEHi;
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u32 MbELo;
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u32 MbFHi;
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u32 MbFLo;
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u32 pad14[32];
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u32 MacAddrHi; /* 0x600 */
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u32 MacAddrLo;
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u32 InfoPtrHi;
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u32 InfoPtrLo;
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u32 MultiCastHi; /* 0x610 */
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u32 MultiCastLo;
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u32 ModeStat;
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u32 DmaReadCfg;
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u32 DmaWriteCfg; /* 0x620 */
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u32 TxBufRat;
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u32 EvtCsm;
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u32 CmdCsm;
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u32 TuneRxCoalTicks;/* 0x630 */
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u32 TuneTxCoalTicks;
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u32 TuneStatTicks;
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u32 TuneMaxTxDesc;
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u32 TuneMaxRxDesc; /* 0x640 */
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u32 TuneTrace;
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u32 TuneLink;
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u32 TuneFastLink;
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u32 TracePtr; /* 0x650 */
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u32 TraceStrt;
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u32 TraceLen;
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u32 IfIdx;
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u32 IfMtu; /* 0x660 */
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u32 MaskInt;
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u32 GigLnkState;
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u32 FastLnkState;
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u32 pad16[4]; /* 0x670 */
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u32 RxRetCsm; /* 0x680 */
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u32 pad17[31];
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u32 CmdRng[64]; /* 0x700 */
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u32 Window[0x200];
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};
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typedef struct {
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u32 addrhi;
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u32 addrlo;
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} aceaddr;
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#define ACE_WINDOW_SIZE 0x800
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#define ACE_JUMBO_MTU 9000
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#define ACE_STD_MTU 1500
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#define ACE_TRACE_SIZE 0x8000
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/*
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* Host control register bits.
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*/
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#define IN_INT 0x01
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#define CLR_INT 0x02
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#define HW_RESET 0x08
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#define BYTE_SWAP 0x10
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#define WORD_SWAP 0x20
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#define MASK_INTS 0x40
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/*
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* Local control register bits.
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*/
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#define EEPROM_DATA_IN 0x800000
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#define EEPROM_DATA_OUT 0x400000
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#define EEPROM_WRITE_ENABLE 0x200000
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#define EEPROM_CLK_OUT 0x100000
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#define EEPROM_BASE 0xa0000000
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#define EEPROM_WRITE_SELECT 0xa0
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#define EEPROM_READ_SELECT 0xa1
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#define SRAM_BANK_512K 0x200
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/*
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* udelay() values for when clocking the eeprom
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*/
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#define ACE_SHORT_DELAY 2
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#define ACE_LONG_DELAY 4
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/*
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* Misc Config bits
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*/
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#define SYNC_SRAM_TIMING 0x100000
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/*
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* CPU state bits.
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*/
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#define CPU_RESET 0x01
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#define CPU_TRACE 0x02
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#define CPU_PROM_FAILED 0x10
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#define CPU_HALT 0x00010000
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#define CPU_HALTED 0xffff0000
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/*
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* PCI State bits.
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*/
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#define DMA_READ_MAX_4 0x04
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#define DMA_READ_MAX_16 0x08
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#define DMA_READ_MAX_32 0x0c
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#define DMA_READ_MAX_64 0x10
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#define DMA_READ_MAX_128 0x14
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#define DMA_READ_MAX_256 0x18
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#define DMA_READ_MAX_1K 0x1c
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#define DMA_WRITE_MAX_4 0x20
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#define DMA_WRITE_MAX_16 0x40
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#define DMA_WRITE_MAX_32 0x60
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#define DMA_WRITE_MAX_64 0x80
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#define DMA_WRITE_MAX_128 0xa0
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#define DMA_WRITE_MAX_256 0xc0
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#define DMA_WRITE_MAX_1K 0xe0
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#define DMA_READ_WRITE_MASK 0xfc
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#define MEM_READ_MULTIPLE 0x00020000
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#define PCI_66MHZ 0x00080000
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#define PCI_32BIT 0x00100000
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#define DMA_WRITE_ALL_ALIGN 0x00800000
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#define READ_CMD_MEM 0x06000000
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#define WRITE_CMD_MEM 0x70000000
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/*
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* Mode status
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*/
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#define ACE_BYTE_SWAP_BD 0x02
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#define ACE_WORD_SWAP_BD 0x04 /* not actually used */
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#define ACE_WARN 0x08
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#define ACE_BYTE_SWAP_DMA 0x10
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#define ACE_NO_JUMBO_FRAG 0x200
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#define ACE_FATAL 0x40000000
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/*
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* DMA config
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*/
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#define DMA_THRESH_1W 0x10
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#define DMA_THRESH_2W 0x20
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#define DMA_THRESH_4W 0x40
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#define DMA_THRESH_8W 0x80
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#define DMA_THRESH_16W 0x100
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#define DMA_THRESH_32W 0x0 /* not described in doc, but exists. */
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/*
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* Tuning parameters
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*/
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#define TICKS_PER_SEC 1000000
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/*
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* Link bits
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*/
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#define LNK_PREF 0x00008000
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#define LNK_10MB 0x00010000
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#define LNK_100MB 0x00020000
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#define LNK_1000MB 0x00040000
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#define LNK_FULL_DUPLEX 0x00080000
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#define LNK_HALF_DUPLEX 0x00100000
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#define LNK_TX_FLOW_CTL_Y 0x00200000
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#define LNK_NEG_ADVANCED 0x00400000
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#define LNK_RX_FLOW_CTL_Y 0x00800000
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#define LNK_NIC 0x01000000
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#define LNK_JAM 0x02000000
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#define LNK_JUMBO 0x04000000
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#define LNK_ALTEON 0x08000000
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#define LNK_NEG_FCTL 0x10000000
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#define LNK_NEGOTIATE 0x20000000
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#define LNK_ENABLE 0x40000000
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#define LNK_UP 0x80000000
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/*
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* Event definitions
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*/
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#define EVT_RING_ENTRIES 256
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#define EVT_RING_SIZE (EVT_RING_ENTRIES * sizeof(struct event))
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struct event {
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#ifdef __LITTLE_ENDIAN_BITFIELD
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u32 idx:12;
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u32 code:12;
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u32 evt:8;
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#else
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u32 evt:8;
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u32 code:12;
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u32 idx:12;
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#endif
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u32 pad;
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};
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/*
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* Events
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*/
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#define E_FW_RUNNING 0x01
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#define E_STATS_UPDATED 0x04
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#define E_STATS_UPDATE 0x04
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#define E_LNK_STATE 0x06
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#define E_C_LINK_UP 0x01
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#define E_C_LINK_DOWN 0x02
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#define E_C_LINK_10_100 0x03
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#define E_ERROR 0x07
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#define E_C_ERR_INVAL_CMD 0x01
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#define E_C_ERR_UNIMP_CMD 0x02
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#define E_C_ERR_BAD_CFG 0x03
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#define E_MCAST_LIST 0x08
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#define E_C_MCAST_ADDR_ADD 0x01
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#define E_C_MCAST_ADDR_DEL 0x02
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#define E_RESET_JUMBO_RNG 0x09
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/*
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* Commands
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*/
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#define CMD_RING_ENTRIES 64
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struct cmd {
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#ifdef __LITTLE_ENDIAN_BITFIELD
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u32 idx:12;
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u32 code:12;
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u32 evt:8;
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#else
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u32 evt:8;
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u32 code:12;
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u32 idx:12;
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#endif
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};
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#define C_HOST_STATE 0x01
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#define C_C_STACK_UP 0x01
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#define C_C_STACK_DOWN 0x02
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#define C_FDR_FILTERING 0x02
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#define C_C_FDR_FILT_ENABLE 0x01
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#define C_C_FDR_FILT_DISABLE 0x02
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#define C_SET_RX_PRD_IDX 0x03
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#define C_UPDATE_STATS 0x04
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#define C_RESET_JUMBO_RNG 0x05
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#define C_ADD_MULTICAST_ADDR 0x08
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#define C_DEL_MULTICAST_ADDR 0x09
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#define C_SET_PROMISC_MODE 0x0a
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#define C_C_PROMISC_ENABLE 0x01
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#define C_C_PROMISC_DISABLE 0x02
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#define C_LNK_NEGOTIATION 0x0b
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#define C_C_NEGOTIATE_BOTH 0x00
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#define C_C_NEGOTIATE_GIG 0x01
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#define C_C_NEGOTIATE_10_100 0x02
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#define C_SET_MAC_ADDR 0x0c
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#define C_CLEAR_PROFILE 0x0d
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#define C_SET_MULTICAST_MODE 0x0e
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#define C_C_MCAST_ENABLE 0x01
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#define C_C_MCAST_DISABLE 0x02
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#define C_CLEAR_STATS 0x0f
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#define C_SET_RX_JUMBO_PRD_IDX 0x10
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#define C_REFRESH_STATS 0x11
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/*
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* Descriptor flags
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*/
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#define BD_FLG_TCP_UDP_SUM 0x01
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#define BD_FLG_IP_SUM 0x02
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#define BD_FLG_END 0x04
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#define BD_FLG_MORE 0x08
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#define BD_FLG_JUMBO 0x10
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#define BD_FLG_UCAST 0x20
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#define BD_FLG_MCAST 0x40
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#define BD_FLG_BCAST 0x60
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#define BD_FLG_TYP_MASK 0x60
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#define BD_FLG_IP_FRAG 0x80
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#define BD_FLG_IP_FRAG_END 0x100
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#define BD_FLG_VLAN_TAG 0x200
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#define BD_FLG_FRAME_ERROR 0x400
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#define BD_FLG_COAL_NOW 0x800
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#define BD_FLG_MINI 0x1000
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/*
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* Ring Control block flags
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*/
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#define RCB_FLG_TCP_UDP_SUM 0x01
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#define RCB_FLG_IP_SUM 0x02
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#define RCB_FLG_NO_PSEUDO_HDR 0x08
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#define RCB_FLG_VLAN_ASSIST 0x10
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#define RCB_FLG_COAL_INT_ONLY 0x20
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#define RCB_FLG_TX_HOST_RING 0x40
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#define RCB_FLG_IEEE_SNAP_SUM 0x80
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#define RCB_FLG_EXT_RX_BD 0x100
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#define RCB_FLG_RNG_DISABLE 0x200
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/*
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* TX ring - maximum TX ring entries for Tigon I's is 128
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*/
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#define MAX_TX_RING_ENTRIES 256
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#define TIGON_I_TX_RING_ENTRIES 128
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#define TX_RING_SIZE (MAX_TX_RING_ENTRIES * sizeof(struct tx_desc))
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#define TX_RING_BASE 0x3800
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struct tx_desc{
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aceaddr addr;
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u32 flagsize;
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#if 0
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/*
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* This is in PCI shared mem and must be accessed with readl/writel
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* real layout is:
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*/
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#if __LITTLE_ENDIAN
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u16 flags;
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u16 size;
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u16 vlan;
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u16 reserved;
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#else
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u16 size;
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u16 flags;
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u16 reserved;
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u16 vlan;
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#endif
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#endif
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u32 vlanres;
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};
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#define RX_STD_RING_ENTRIES 512
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#define RX_STD_RING_SIZE (RX_STD_RING_ENTRIES * sizeof(struct rx_desc))
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#define RX_JUMBO_RING_ENTRIES 256
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#define RX_JUMBO_RING_SIZE (RX_JUMBO_RING_ENTRIES *sizeof(struct rx_desc))
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#define RX_MINI_RING_ENTRIES 1024
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#define RX_MINI_RING_SIZE (RX_MINI_RING_ENTRIES *sizeof(struct rx_desc))
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#define RX_RETURN_RING_ENTRIES 2048
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#define RX_RETURN_RING_SIZE (RX_MAX_RETURN_RING_ENTRIES * \
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sizeof(struct rx_desc))
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struct rx_desc{
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aceaddr addr;
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#ifdef __LITTLE_ENDIAN
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u16 size;
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u16 idx;
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#else
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u16 idx;
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u16 size;
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#endif
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#ifdef __LITTLE_ENDIAN
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u16 flags;
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u16 type;
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#else
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u16 type;
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u16 flags;
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#endif
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#ifdef __LITTLE_ENDIAN
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u16 tcp_udp_csum;
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u16 ip_csum;
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#else
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u16 ip_csum;
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u16 tcp_udp_csum;
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#endif
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#ifdef __LITTLE_ENDIAN
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u16 vlan;
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u16 err_flags;
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#else
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u16 err_flags;
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u16 vlan;
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#endif
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u32 reserved;
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u32 opague;
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};
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/*
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* This struct is shared with the NIC firmware.
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*/
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struct ring_ctrl {
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aceaddr rngptr;
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#ifdef __LITTLE_ENDIAN
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u16 flags;
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u16 max_len;
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#else
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u16 max_len;
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u16 flags;
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#endif
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u32 pad;
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};
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struct ace_mac_stats {
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u32 excess_colls;
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u32 coll_1;
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u32 coll_2;
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u32 coll_3;
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u32 coll_4;
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u32 coll_5;
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u32 coll_6;
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u32 coll_7;
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u32 coll_8;
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u32 coll_9;
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u32 coll_10;
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u32 coll_11;
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u32 coll_12;
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u32 coll_13;
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u32 coll_14;
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u32 coll_15;
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u32 late_coll;
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u32 defers;
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u32 crc_err;
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u32 underrun;
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u32 crs_err;
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u32 pad[3];
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u32 drop_ula;
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u32 drop_mc;
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u32 drop_fc;
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u32 drop_space;
|
|
u32 coll;
|
|
u32 kept_bc;
|
|
u32 kept_mc;
|
|
u32 kept_uc;
|
|
};
|
|
|
|
|
|
struct ace_info {
|
|
union {
|
|
u32 stats[256];
|
|
} s;
|
|
struct ring_ctrl evt_ctrl;
|
|
struct ring_ctrl cmd_ctrl;
|
|
struct ring_ctrl tx_ctrl;
|
|
struct ring_ctrl rx_std_ctrl;
|
|
struct ring_ctrl rx_jumbo_ctrl;
|
|
struct ring_ctrl rx_mini_ctrl;
|
|
struct ring_ctrl rx_return_ctrl;
|
|
aceaddr evt_prd_ptr;
|
|
aceaddr rx_ret_prd_ptr;
|
|
aceaddr tx_csm_ptr;
|
|
aceaddr stats2_ptr;
|
|
};
|
|
|
|
|
|
struct ring_info {
|
|
struct sk_buff *skb;
|
|
DEFINE_DMA_UNMAP_ADDR(mapping);
|
|
};
|
|
|
|
|
|
/*
|
|
* Funny... As soon as we add maplen on alpha, it starts to work
|
|
* much slower. Hmm... is it because struct does not fit to one cacheline?
|
|
* So, split tx_ring_info.
|
|
*/
|
|
struct tx_ring_info {
|
|
struct sk_buff *skb;
|
|
DEFINE_DMA_UNMAP_ADDR(mapping);
|
|
DEFINE_DMA_UNMAP_LEN(maplen);
|
|
};
|
|
|
|
|
|
/*
|
|
* struct ace_skb holding the rings of skb's. This is an awful lot of
|
|
* pointers, but I don't see any other smart mode to do this in an
|
|
* efficient manner ;-(
|
|
*/
|
|
struct ace_skb
|
|
{
|
|
struct tx_ring_info tx_skbuff[MAX_TX_RING_ENTRIES];
|
|
struct ring_info rx_std_skbuff[RX_STD_RING_ENTRIES];
|
|
struct ring_info rx_mini_skbuff[RX_MINI_RING_ENTRIES];
|
|
struct ring_info rx_jumbo_skbuff[RX_JUMBO_RING_ENTRIES];
|
|
};
|
|
|
|
|
|
/*
|
|
* Struct private for the AceNIC.
|
|
*
|
|
* Elements are grouped so variables used by the tx handling goes
|
|
* together, and will go into the same cache lines etc. in order to
|
|
* avoid cache line contention between the rx and tx handling on SMP.
|
|
*
|
|
* Frequently accessed variables are put at the beginning of the
|
|
* struct to help the compiler generate better/shorter code.
|
|
*/
|
|
struct ace_private
|
|
{
|
|
struct ace_info *info;
|
|
struct ace_regs __iomem *regs; /* register base */
|
|
struct ace_skb *skb;
|
|
dma_addr_t info_dma; /* 32/64 bit */
|
|
|
|
int version, link;
|
|
int promisc, mcast_all;
|
|
|
|
/*
|
|
* TX elements
|
|
*/
|
|
struct tx_desc *tx_ring;
|
|
u32 tx_prd;
|
|
volatile u32 tx_ret_csm;
|
|
int tx_ring_entries;
|
|
|
|
/*
|
|
* RX elements
|
|
*/
|
|
unsigned long std_refill_busy
|
|
__attribute__ ((aligned (SMP_CACHE_BYTES)));
|
|
unsigned long mini_refill_busy, jumbo_refill_busy;
|
|
atomic_t cur_rx_bufs;
|
|
atomic_t cur_mini_bufs;
|
|
atomic_t cur_jumbo_bufs;
|
|
u32 rx_std_skbprd, rx_mini_skbprd, rx_jumbo_skbprd;
|
|
u32 cur_rx;
|
|
|
|
struct rx_desc *rx_std_ring;
|
|
struct rx_desc *rx_jumbo_ring;
|
|
struct rx_desc *rx_mini_ring;
|
|
struct rx_desc *rx_return_ring;
|
|
|
|
int tasklet_pending, jumbo;
|
|
struct tasklet_struct ace_tasklet;
|
|
|
|
struct event *evt_ring;
|
|
|
|
volatile u32 *evt_prd, *rx_ret_prd, *tx_csm;
|
|
|
|
dma_addr_t tx_ring_dma; /* 32/64 bit */
|
|
dma_addr_t rx_ring_base_dma;
|
|
dma_addr_t evt_ring_dma;
|
|
dma_addr_t evt_prd_dma, rx_ret_prd_dma, tx_csm_dma;
|
|
|
|
unsigned char *trace_buf;
|
|
struct pci_dev *pdev;
|
|
struct net_device *next;
|
|
volatile int fw_running;
|
|
int board_idx;
|
|
u16 pci_command;
|
|
u8 pci_latency;
|
|
const char *name;
|
|
#ifdef INDEX_DEBUG
|
|
spinlock_t debug_lock
|
|
__attribute__ ((aligned (SMP_CACHE_BYTES)));
|
|
u32 last_tx, last_std_rx, last_mini_rx;
|
|
#endif
|
|
int pci_using_dac;
|
|
u8 firmware_major;
|
|
u8 firmware_minor;
|
|
u8 firmware_fix;
|
|
u32 firmware_start;
|
|
};
|
|
|
|
|
|
#define TX_RESERVED MAX_SKB_FRAGS
|
|
|
|
static inline int tx_space (struct ace_private *ap, u32 csm, u32 prd)
|
|
{
|
|
return (csm - prd - 1) & (ACE_TX_RING_ENTRIES(ap) - 1);
|
|
}
|
|
|
|
#define tx_free(ap) tx_space((ap)->tx_ret_csm, (ap)->tx_prd, ap)
|
|
#define tx_ring_full(ap, csm, prd) (tx_space(ap, csm, prd) <= TX_RESERVED)
|
|
|
|
static inline void set_aceaddr(aceaddr *aa, dma_addr_t addr)
|
|
{
|
|
u64 baddr = (u64) addr;
|
|
aa->addrlo = baddr & 0xffffffff;
|
|
aa->addrhi = baddr >> 32;
|
|
wmb();
|
|
}
|
|
|
|
|
|
static inline void ace_set_txprd(struct ace_regs __iomem *regs,
|
|
struct ace_private *ap, u32 value)
|
|
{
|
|
#ifdef INDEX_DEBUG
|
|
unsigned long flags;
|
|
spin_lock_irqsave(&ap->debug_lock, flags);
|
|
writel(value, ®s->TxPrd);
|
|
if (value == ap->last_tx)
|
|
printk(KERN_ERR "AceNIC RACE ALERT! writing identical value "
|
|
"to tx producer (%i)\n", value);
|
|
ap->last_tx = value;
|
|
spin_unlock_irqrestore(&ap->debug_lock, flags);
|
|
#else
|
|
writel(value, ®s->TxPrd);
|
|
#endif
|
|
wmb();
|
|
}
|
|
|
|
|
|
static inline void ace_mask_irq(struct net_device *dev)
|
|
{
|
|
struct ace_private *ap = netdev_priv(dev);
|
|
struct ace_regs __iomem *regs = ap->regs;
|
|
|
|
if (ACE_IS_TIGON_I(ap))
|
|
writel(1, ®s->MaskInt);
|
|
else
|
|
writel(readl(®s->HostCtrl) | MASK_INTS, ®s->HostCtrl);
|
|
|
|
ace_sync_irq(dev->irq);
|
|
}
|
|
|
|
|
|
static inline void ace_unmask_irq(struct net_device *dev)
|
|
{
|
|
struct ace_private *ap = netdev_priv(dev);
|
|
struct ace_regs __iomem *regs = ap->regs;
|
|
|
|
if (ACE_IS_TIGON_I(ap))
|
|
writel(0, ®s->MaskInt);
|
|
else
|
|
writel(readl(®s->HostCtrl) & ~MASK_INTS, ®s->HostCtrl);
|
|
}
|
|
|
|
|
|
/*
|
|
* Prototypes
|
|
*/
|
|
static int ace_init(struct net_device *dev);
|
|
static void ace_load_std_rx_ring(struct net_device *dev, int nr_bufs);
|
|
static void ace_load_mini_rx_ring(struct net_device *dev, int nr_bufs);
|
|
static void ace_load_jumbo_rx_ring(struct net_device *dev, int nr_bufs);
|
|
static irqreturn_t ace_interrupt(int irq, void *dev_id);
|
|
static int ace_load_firmware(struct net_device *dev);
|
|
static int ace_open(struct net_device *dev);
|
|
static netdev_tx_t ace_start_xmit(struct sk_buff *skb,
|
|
struct net_device *dev);
|
|
static int ace_close(struct net_device *dev);
|
|
static void ace_tasklet(unsigned long dev);
|
|
static void ace_dump_trace(struct ace_private *ap);
|
|
static void ace_set_multicast_list(struct net_device *dev);
|
|
static int ace_change_mtu(struct net_device *dev, int new_mtu);
|
|
static int ace_set_mac_addr(struct net_device *dev, void *p);
|
|
static void ace_set_rxtx_parms(struct net_device *dev, int jumbo);
|
|
static int ace_allocate_descriptors(struct net_device *dev);
|
|
static void ace_free_descriptors(struct net_device *dev);
|
|
static void ace_init_cleanup(struct net_device *dev);
|
|
static struct net_device_stats *ace_get_stats(struct net_device *dev);
|
|
static int read_eeprom_byte(struct net_device *dev, unsigned long offset);
|
|
|
|
#endif /* _ACENIC_H_ */
|