774 lines
21 KiB
C
774 lines
21 KiB
C
/**********************************************************************
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* Author: Cavium, Inc.
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*
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* Contact: support@cavium.com
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* Please include "LiquidIO" in the subject.
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*
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* Copyright (c) 2003-2015 Cavium, Inc.
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful, but
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
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* NONINFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* This file may also be available under a different license from Cavium.
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* Contact Cavium, Inc. for more information
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**********************************************************************/
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/*! \file octeon_device.h
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* \brief Host Driver: This file defines the octeon device structure.
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*/
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#ifndef _OCTEON_DEVICE_H_
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#define _OCTEON_DEVICE_H_
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/** PCI VendorId Device Id */
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#define OCTEON_CN68XX_PCIID 0x91177d
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#define OCTEON_CN66XX_PCIID 0x92177d
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#define OCTEON_CN23XX_PCIID_PF 0x9702177d
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/** Driver identifies chips by these Ids, created by clubbing together
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* DeviceId+RevisionId; Where Revision Id is not used to distinguish
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* between chips, a value of 0 is used for revision id.
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*/
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#define OCTEON_CN68XX 0x0091
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#define OCTEON_CN66XX 0x0092
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#define OCTEON_CN23XX_PF_VID 0x9702
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/**RevisionId for the chips */
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#define OCTEON_CN23XX_REV_1_0 0x00
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#define OCTEON_CN23XX_REV_1_1 0x01
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#define OCTEON_CN23XX_REV_2_0 0x80
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/** Endian-swap modes supported by Octeon. */
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enum octeon_pci_swap_mode {
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OCTEON_PCI_PASSTHROUGH = 0,
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OCTEON_PCI_64BIT_SWAP = 1,
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OCTEON_PCI_32BIT_BYTE_SWAP = 2,
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OCTEON_PCI_32BIT_LW_SWAP = 3
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};
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#define OCTEON_OUTPUT_INTR (2)
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#define OCTEON_ALL_INTR 0xff
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/*--------------- PCI BAR1 index registers -------------*/
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/* BAR1 Mask */
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#define PCI_BAR1_ENABLE_CA 1
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#define PCI_BAR1_ENDIAN_MODE OCTEON_PCI_64BIT_SWAP
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#define PCI_BAR1_ENTRY_VALID 1
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#define PCI_BAR1_MASK ((PCI_BAR1_ENABLE_CA << 3) \
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| (PCI_BAR1_ENDIAN_MODE << 1) \
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| PCI_BAR1_ENTRY_VALID)
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/** Octeon Device state.
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* Each octeon device goes through each of these states
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* as it is initialized.
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*/
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#define OCT_DEV_BEGIN_STATE 0x0
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#define OCT_DEV_PCI_MAP_DONE 0x1
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#define OCT_DEV_DISPATCH_INIT_DONE 0x2
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#define OCT_DEV_INSTR_QUEUE_INIT_DONE 0x3
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#define OCT_DEV_SC_BUFF_POOL_INIT_DONE 0x4
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#define OCT_DEV_RESP_LIST_INIT_DONE 0x5
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#define OCT_DEV_DROQ_INIT_DONE 0x6
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#define OCT_DEV_IO_QUEUES_DONE 0x7
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#define OCT_DEV_CONSOLE_INIT_DONE 0x8
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#define OCT_DEV_HOST_OK 0x9
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#define OCT_DEV_CORE_OK 0xa
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#define OCT_DEV_RUNNING 0xb
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#define OCT_DEV_IN_RESET 0xc
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#define OCT_DEV_STATE_INVALID 0xd
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#define OCT_DEV_STATES OCT_DEV_STATE_INVALID
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/** Octeon Device interrupts
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* These interrupt bits are set in int_status filed of
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* octeon_device structure
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*/
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#define OCT_DEV_INTR_DMA0_FORCE 0x01
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#define OCT_DEV_INTR_DMA1_FORCE 0x02
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#define OCT_DEV_INTR_PKT_DATA 0x04
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#define LIO_RESET_SECS (3)
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/*---------------------------DISPATCH LIST-------------------------------*/
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/** The dispatch list entry.
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* The driver keeps a record of functions registered for each
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* response header opcode in this structure. Since the opcode is
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* hashed to index into the driver's list, more than one opcode
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* can hash to the same entry, in which case the list field points
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* to a linked list with the other entries.
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*/
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struct octeon_dispatch {
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/** List head for this entry */
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struct list_head list;
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/** The opcode for which the dispatch function & arg should be used */
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u16 opcode;
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/** The function to be called for a packet received by the driver */
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octeon_dispatch_fn_t dispatch_fn;
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/* The application specified argument to be passed to the above
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* function along with the received packet
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*/
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void *arg;
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};
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/** The dispatch list structure. */
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struct octeon_dispatch_list {
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/** access to dispatch list must be atomic */
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spinlock_t lock;
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/** Count of dispatch functions currently registered */
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u32 count;
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/** The list of dispatch functions */
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struct octeon_dispatch *dlist;
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};
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/*----------------------- THE OCTEON DEVICE ---------------------------*/
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#define OCT_MEM_REGIONS 3
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/** PCI address space mapping information.
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* Each of the 3 address spaces given by BAR0, BAR2 and BAR4 of
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* Octeon gets mapped to different physical address spaces in
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* the kernel.
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*/
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struct octeon_mmio {
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/** PCI address to which the BAR is mapped. */
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u64 start;
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/** Length of this PCI address space. */
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u32 len;
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/** Length that has been mapped to phys. address space. */
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u32 mapped_len;
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/** The physical address to which the PCI address space is mapped. */
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u8 __iomem *hw_addr;
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/** Flag indicating the mapping was successful. */
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u32 done;
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};
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#define MAX_OCTEON_MAPS 32
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struct octeon_io_enable {
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u64 iq;
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u64 oq;
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u64 iq64B;
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};
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struct octeon_reg_list {
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u32 __iomem *pci_win_wr_addr_hi;
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u32 __iomem *pci_win_wr_addr_lo;
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u64 __iomem *pci_win_wr_addr;
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u32 __iomem *pci_win_rd_addr_hi;
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u32 __iomem *pci_win_rd_addr_lo;
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u64 __iomem *pci_win_rd_addr;
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u32 __iomem *pci_win_wr_data_hi;
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u32 __iomem *pci_win_wr_data_lo;
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u64 __iomem *pci_win_wr_data;
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u32 __iomem *pci_win_rd_data_hi;
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u32 __iomem *pci_win_rd_data_lo;
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u64 __iomem *pci_win_rd_data;
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};
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#define OCTEON_CONSOLE_MAX_READ_BYTES 512
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struct octeon_console {
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u32 active;
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u32 waiting;
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u64 addr;
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u32 buffer_size;
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u64 input_base_addr;
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u64 output_base_addr;
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char leftover[OCTEON_CONSOLE_MAX_READ_BYTES];
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};
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struct octeon_board_info {
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char name[OCT_BOARD_NAME];
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char serial_number[OCT_SERIAL_LEN];
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u64 major;
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u64 minor;
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};
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struct octeon_fn_list {
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void (*setup_iq_regs)(struct octeon_device *, u32);
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void (*setup_oq_regs)(struct octeon_device *, u32);
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irqreturn_t (*process_interrupt_regs)(void *);
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u64 (*msix_interrupt_handler)(void *);
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int (*soft_reset)(struct octeon_device *);
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int (*setup_device_regs)(struct octeon_device *);
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void (*bar1_idx_setup)(struct octeon_device *, u64, u32, int);
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void (*bar1_idx_write)(struct octeon_device *, u32, u32);
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u32 (*bar1_idx_read)(struct octeon_device *, u32);
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u32 (*update_iq_read_idx)(struct octeon_instr_queue *);
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void (*enable_oq_pkt_time_intr)(struct octeon_device *, u32);
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void (*disable_oq_pkt_time_intr)(struct octeon_device *, u32);
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void (*enable_interrupt)(struct octeon_device *, u8);
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void (*disable_interrupt)(struct octeon_device *, u8);
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int (*enable_io_queues)(struct octeon_device *);
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void (*disable_io_queues)(struct octeon_device *);
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};
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/* Must be multiple of 8, changing breaks ABI */
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#define CVMX_BOOTMEM_NAME_LEN 128
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/* Structure for named memory blocks
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* Number of descriptors
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* available can be changed without affecting compatibility,
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* but name length changes require a bump in the bootmem
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* descriptor version
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* Note: This structure must be naturally 64 bit aligned, as a single
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* memory image will be used by both 32 and 64 bit programs.
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*/
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struct cvmx_bootmem_named_block_desc {
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/** Base address of named block */
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u64 base_addr;
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/** Size actually allocated for named block */
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u64 size;
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/** name of named block */
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char name[CVMX_BOOTMEM_NAME_LEN];
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};
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struct oct_fw_info {
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u32 max_nic_ports; /** max nic ports for the device */
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u32 num_gmx_ports; /** num gmx ports */
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u64 app_cap_flags; /** firmware cap flags */
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/** The core application is running in this mode.
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* See octeon-drv-opcodes.h for values.
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*/
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u32 app_mode;
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char liquidio_firmware_version[32];
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};
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/* wrappers around work structs */
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struct cavium_wk {
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struct delayed_work work;
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void *ctxptr;
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u64 ctxul;
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};
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struct cavium_wq {
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struct workqueue_struct *wq;
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struct cavium_wk wk;
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};
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struct octdev_props {
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/* Each interface in the Octeon device has a network
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* device pointer (used for OS specific calls).
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*/
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int rx_on;
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int napi_enabled;
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int gmxport;
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struct net_device *netdev;
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};
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#define LIO_FLAG_MSIX_ENABLED 0x1
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#define MSIX_PO_INT 0x1
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#define MSIX_PI_INT 0x2
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struct octeon_pf_vf_hs_word {
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#ifdef __LITTLE_ENDIAN_BITFIELD
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/** PKIND value assigned for the DPI interface */
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u64 pkind : 8;
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/** OCTEON core clock multiplier */
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u64 core_tics_per_us : 16;
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/** OCTEON coprocessor clock multiplier */
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u64 coproc_tics_per_us : 16;
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/** app that currently running on OCTEON */
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u64 app_mode : 8;
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/** RESERVED */
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u64 reserved : 16;
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#else
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/** RESERVED */
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u64 reserved : 16;
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/** app that currently running on OCTEON */
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u64 app_mode : 8;
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/** OCTEON coprocessor clock multiplier */
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u64 coproc_tics_per_us : 16;
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/** OCTEON core clock multiplier */
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u64 core_tics_per_us : 16;
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/** PKIND value assigned for the DPI interface */
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u64 pkind : 8;
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#endif
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};
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struct octeon_sriov_info {
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/* Actual rings left for PF device */
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u32 num_pf_rings;
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/* SRN of PF usable IO queues */
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u32 pf_srn;
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/* total pf rings */
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u32 trs;
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};
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struct octeon_ioq_vector {
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struct octeon_device *oct_dev;
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int iq_index;
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int droq_index;
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int vector;
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struct cpumask affinity_mask;
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u32 ioq_num;
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};
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/** The Octeon device.
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* Each Octeon device has this structure to represent all its
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* components.
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*/
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struct octeon_device {
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/** Lock for PCI window configuration accesses */
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spinlock_t pci_win_lock;
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/** Lock for memory accesses */
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spinlock_t mem_access_lock;
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/** PCI device pointer */
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struct pci_dev *pci_dev;
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/** Chip specific information. */
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void *chip;
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/** Number of interfaces detected in this octeon device. */
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u32 ifcount;
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struct octdev_props props[MAX_OCTEON_LINKS];
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/** Octeon Chip type. */
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u16 chip_id;
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u16 rev_id;
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u16 pf_num;
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/** This device's id - set by the driver. */
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u32 octeon_id;
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/** This device's PCIe port used for traffic. */
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u16 pcie_port;
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u16 flags;
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#define LIO_FLAG_MSI_ENABLED (u32)(1 << 1)
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/** The state of this device */
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atomic_t status;
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/** memory mapped io range */
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struct octeon_mmio mmio[OCT_MEM_REGIONS];
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struct octeon_reg_list reg_list;
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struct octeon_fn_list fn_list;
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struct octeon_board_info boardinfo;
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u32 num_iqs;
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/* The pool containing pre allocated buffers used for soft commands */
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struct octeon_sc_buffer_pool sc_buf_pool;
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/** The input instruction queues */
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struct octeon_instr_queue *instr_queue
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[MAX_POSSIBLE_OCTEON_INSTR_QUEUES];
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/** The doubly-linked list of instruction response */
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struct octeon_response_list response_list[MAX_RESPONSE_LISTS];
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u32 num_oqs;
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/** The DROQ output queues */
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struct octeon_droq *droq[MAX_POSSIBLE_OCTEON_OUTPUT_QUEUES];
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struct octeon_io_enable io_qmask;
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/** List of dispatch functions */
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struct octeon_dispatch_list dispatch;
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/* Interrupt Moderation */
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struct oct_intrmod_cfg intrmod;
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u32 int_status;
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u64 droq_intr;
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/** Physical location of the cvmx_bootmem_desc_t in octeon memory */
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u64 bootmem_desc_addr;
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/** Placeholder memory for named blocks.
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* Assumes single-threaded access
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*/
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struct cvmx_bootmem_named_block_desc bootmem_named_block_desc;
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/** Address of consoles descriptor */
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u64 console_desc_addr;
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/** Number of consoles available. 0 means they are inaccessible */
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u32 num_consoles;
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/* Console caches */
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struct octeon_console console[MAX_OCTEON_MAPS];
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/* Coprocessor clock rate. */
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u64 coproc_clock_rate;
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/** The core application is running in this mode. See liquidio_common.h
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* for values.
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*/
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u32 app_mode;
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struct oct_fw_info fw_info;
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/** The name given to this device. */
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char device_name[32];
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/** Application Context */
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void *app_ctx;
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struct cavium_wq dma_comp_wq;
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/** Lock for dma response list */
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spinlock_t cmd_resp_wqlock;
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u32 cmd_resp_state;
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struct cavium_wq check_db_wq[MAX_POSSIBLE_OCTEON_INSTR_QUEUES];
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struct cavium_wk nic_poll_work;
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struct cavium_wk console_poll_work[MAX_OCTEON_MAPS];
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void *priv;
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int num_msix_irqs;
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void *msix_entries;
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struct octeon_sriov_info sriov_info;
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struct octeon_pf_vf_hs_word pfvf_hsword;
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int msix_on;
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/** IOq information of it's corresponding MSI-X interrupt. */
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struct octeon_ioq_vector *ioq_vector;
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int rx_pause;
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int tx_pause;
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struct oct_link_stats link_stats; /*stastics from firmware*/
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/* private flags to control driver-specific features through ethtool */
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u32 priv_flags;
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void *watchdog_task;
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};
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#define OCT_DRV_ONLINE 1
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#define OCT_DRV_OFFLINE 2
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#define OCTEON_CN6XXX(oct) ((oct->chip_id == OCTEON_CN66XX) || \
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(oct->chip_id == OCTEON_CN68XX))
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#define OCTEON_CN23XX_PF(oct) (oct->chip_id == OCTEON_CN23XX_PF_VID)
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#define CHIP_FIELD(oct, TYPE, field) \
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(((struct octeon_ ## TYPE *)(oct->chip))->field)
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struct oct_intrmod_cmd {
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struct octeon_device *oct_dev;
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struct octeon_soft_command *sc;
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struct oct_intrmod_cfg *cfg;
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};
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/*------------------ Function Prototypes ----------------------*/
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/** Initialize device list memory */
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void octeon_init_device_list(int conf_type);
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/** Free memory for Input and Output queue structures for a octeon device */
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void octeon_free_device_mem(struct octeon_device *);
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/* Look up a free entry in the octeon_device table and allocate resources
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* for the octeon_device structure for an octeon device. Called at init
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* time.
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*/
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struct octeon_device *octeon_allocate_device(u32 pci_id,
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u32 priv_size);
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/** Initialize the driver's dispatch list which is a mix of a hash table
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* and a linked list. This is done at driver load time.
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* @param octeon_dev - pointer to the octeon device structure.
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* @return 0 on success, else -ve error value
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*/
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int octeon_init_dispatch_list(struct octeon_device *octeon_dev);
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/** Delete the driver's dispatch list and all registered entries.
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* This is done at driver unload time.
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* @param octeon_dev - pointer to the octeon device structure.
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*/
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void octeon_delete_dispatch_list(struct octeon_device *octeon_dev);
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/** Initialize the core device fields with the info returned by the FW.
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* @param recv_info - Receive info structure
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* @param buf - Receive buffer
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*/
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int octeon_core_drv_init(struct octeon_recv_info *recv_info, void *buf);
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|
|
/** Gets the dispatch function registered to receive packets with a
|
|
* given opcode/subcode.
|
|
* @param octeon_dev - the octeon device pointer.
|
|
* @param opcode - the opcode for which the dispatch function
|
|
* is to checked.
|
|
* @param subcode - the subcode for which the dispatch function
|
|
* is to checked.
|
|
*
|
|
* @return Success: octeon_dispatch_fn_t (dispatch function pointer)
|
|
* @return Failure: NULL
|
|
*
|
|
* Looks up the dispatch list to get the dispatch function for a
|
|
* given opcode.
|
|
*/
|
|
octeon_dispatch_fn_t
|
|
octeon_get_dispatch(struct octeon_device *octeon_dev, u16 opcode,
|
|
u16 subcode);
|
|
|
|
/** Get the octeon device pointer.
|
|
* @param octeon_id - The id for which the octeon device pointer is required.
|
|
* @return Success: Octeon device pointer.
|
|
* @return Failure: NULL.
|
|
*/
|
|
struct octeon_device *lio_get_device(u32 octeon_id);
|
|
|
|
/** Get the octeon id assigned to the octeon device passed as argument.
|
|
* This function is exported to other modules.
|
|
* @param dev - octeon device pointer passed as a void *.
|
|
* @return octeon device id
|
|
*/
|
|
int lio_get_device_id(void *dev);
|
|
|
|
static inline u16 OCTEON_MAJOR_REV(struct octeon_device *oct)
|
|
{
|
|
u16 rev = (oct->rev_id & 0xC) >> 2;
|
|
|
|
return (rev == 0) ? 1 : rev;
|
|
}
|
|
|
|
static inline u16 OCTEON_MINOR_REV(struct octeon_device *oct)
|
|
{
|
|
return oct->rev_id & 0x3;
|
|
}
|
|
|
|
/** Read windowed register.
|
|
* @param oct - pointer to the Octeon device.
|
|
* @param addr - Address of the register to read.
|
|
*
|
|
* This routine is called to read from the indirectly accessed
|
|
* Octeon registers that are visible through a PCI BAR0 mapped window
|
|
* register.
|
|
* @return - 64 bit value read from the register.
|
|
*/
|
|
|
|
u64 lio_pci_readq(struct octeon_device *oct, u64 addr);
|
|
|
|
/** Write windowed register.
|
|
* @param oct - pointer to the Octeon device.
|
|
* @param val - Value to write
|
|
* @param addr - Address of the register to write
|
|
*
|
|
* This routine is called to write to the indirectly accessed
|
|
* Octeon registers that are visible through a PCI BAR0 mapped window
|
|
* register.
|
|
* @return Nothing.
|
|
*/
|
|
void lio_pci_writeq(struct octeon_device *oct, u64 val, u64 addr);
|
|
|
|
/* Routines for reading and writing CSRs */
|
|
#define octeon_write_csr(oct_dev, reg_off, value) \
|
|
writel(value, oct_dev->mmio[0].hw_addr + reg_off)
|
|
|
|
#define octeon_write_csr64(oct_dev, reg_off, val64) \
|
|
writeq(val64, oct_dev->mmio[0].hw_addr + reg_off)
|
|
|
|
#define octeon_read_csr(oct_dev, reg_off) \
|
|
readl(oct_dev->mmio[0].hw_addr + reg_off)
|
|
|
|
#define octeon_read_csr64(oct_dev, reg_off) \
|
|
readq(oct_dev->mmio[0].hw_addr + reg_off)
|
|
|
|
/**
|
|
* Checks if memory access is okay
|
|
*
|
|
* @param oct which octeon to send to
|
|
* @return Zero on success, negative on failure.
|
|
*/
|
|
int octeon_mem_access_ok(struct octeon_device *oct);
|
|
|
|
/**
|
|
* Waits for DDR initialization.
|
|
*
|
|
* @param oct which octeon to send to
|
|
* @param timeout_in_ms pointer to how long to wait until DDR is initialized
|
|
* in ms.
|
|
* If contents are 0, it waits until contents are non-zero
|
|
* before starting to check.
|
|
* @return Zero on success, negative on failure.
|
|
*/
|
|
int octeon_wait_for_ddr_init(struct octeon_device *oct,
|
|
u32 *timeout_in_ms);
|
|
|
|
/**
|
|
* Wait for u-boot to boot and be waiting for a command.
|
|
*
|
|
* @param wait_time_hundredths
|
|
* Maximum time to wait
|
|
*
|
|
* @return Zero on success, negative on failure.
|
|
*/
|
|
int octeon_wait_for_bootloader(struct octeon_device *oct,
|
|
u32 wait_time_hundredths);
|
|
|
|
/**
|
|
* Initialize console access
|
|
*
|
|
* @param oct which octeon initialize
|
|
* @return Zero on success, negative on failure.
|
|
*/
|
|
int octeon_init_consoles(struct octeon_device *oct);
|
|
|
|
/**
|
|
* Adds access to a console to the device.
|
|
*
|
|
* @param oct which octeon to add to
|
|
* @param console_num which console
|
|
* @return Zero on success, negative on failure.
|
|
*/
|
|
int octeon_add_console(struct octeon_device *oct, u32 console_num);
|
|
|
|
/** write or read from a console */
|
|
int octeon_console_write(struct octeon_device *oct, u32 console_num,
|
|
char *buffer, u32 write_request_size, u32 flags);
|
|
int octeon_console_write_avail(struct octeon_device *oct, u32 console_num);
|
|
|
|
int octeon_console_read_avail(struct octeon_device *oct, u32 console_num);
|
|
|
|
/** Removes all attached consoles. */
|
|
void octeon_remove_consoles(struct octeon_device *oct);
|
|
|
|
/**
|
|
* Send a string to u-boot on console 0 as a command.
|
|
*
|
|
* @param oct which octeon to send to
|
|
* @param cmd_str String to send
|
|
* @param wait_hundredths Time to wait for u-boot to accept the command.
|
|
*
|
|
* @return Zero on success, negative on failure.
|
|
*/
|
|
int octeon_console_send_cmd(struct octeon_device *oct, char *cmd_str,
|
|
u32 wait_hundredths);
|
|
|
|
/** Parses, validates, and downloads firmware, then boots associated cores.
|
|
* @param oct which octeon to download firmware to
|
|
* @param data - The complete firmware file image
|
|
* @param size - The size of the data
|
|
*
|
|
* @return 0 if success.
|
|
* -EINVAL if file is incompatible or badly formatted.
|
|
* -ENODEV if no handler was found for the application type or an
|
|
* invalid octeon id was passed.
|
|
*/
|
|
int octeon_download_firmware(struct octeon_device *oct, const u8 *data,
|
|
size_t size);
|
|
|
|
char *lio_get_state_string(atomic_t *state_ptr);
|
|
|
|
/** Sets up instruction queues for the device
|
|
* @param oct which octeon to setup
|
|
*
|
|
* @return 0 if success. 1 if fails
|
|
*/
|
|
int octeon_setup_instr_queues(struct octeon_device *oct);
|
|
|
|
/** Sets up output queues for the device
|
|
* @param oct which octeon to setup
|
|
*
|
|
* @return 0 if success. 1 if fails
|
|
*/
|
|
int octeon_setup_output_queues(struct octeon_device *oct);
|
|
|
|
int octeon_get_tx_qsize(struct octeon_device *oct, u32 q_no);
|
|
|
|
int octeon_get_rx_qsize(struct octeon_device *oct, u32 q_no);
|
|
|
|
/** Turns off the input and output queues for the device
|
|
* @param oct which octeon to disable
|
|
*/
|
|
void octeon_set_io_queues_off(struct octeon_device *oct);
|
|
|
|
/** Turns on or off the given output queue for the device
|
|
* @param oct which octeon to change
|
|
* @param q_no which queue
|
|
* @param enable 1 to enable, 0 to disable
|
|
*/
|
|
void octeon_set_droq_pkt_op(struct octeon_device *oct, u32 q_no, u32 enable);
|
|
|
|
/** Retrieve the config for the device
|
|
* @param oct which octeon
|
|
* @param card_type type of card
|
|
*
|
|
* @returns pointer to configuration
|
|
*/
|
|
void *oct_get_config_info(struct octeon_device *oct, u16 card_type);
|
|
|
|
/** Gets the octeon device configuration
|
|
* @return - pointer to the octeon configuration struture
|
|
*/
|
|
struct octeon_config *octeon_get_conf(struct octeon_device *oct);
|
|
|
|
void octeon_free_ioq_vector(struct octeon_device *oct);
|
|
int octeon_allocate_ioq_vector(struct octeon_device *oct);
|
|
void lio_enable_irq(struct octeon_droq *droq, struct octeon_instr_queue *iq);
|
|
|
|
/* LiquidIO driver pivate flags */
|
|
enum {
|
|
OCT_PRIV_FLAG_TX_BYTES = 0, /* Tx interrupts by pending byte count */
|
|
};
|
|
|
|
#define OCT_PRIV_FLAG_DEFAULT 0x0
|
|
|
|
static inline u32 lio_get_priv_flag(struct octeon_device *octdev, u32 flag)
|
|
{
|
|
return !!(octdev->priv_flags & (0x1 << flag));
|
|
}
|
|
|
|
static inline void lio_set_priv_flag(struct octeon_device *octdev,
|
|
u32 flag, u32 val)
|
|
{
|
|
if (val)
|
|
octdev->priv_flags |= (0x1 << flag);
|
|
else
|
|
octdev->priv_flags &= ~(0x1 << flag);
|
|
}
|
|
#endif
|