476 lines
16 KiB
C
476 lines
16 KiB
C
/*******************************************************************************
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*
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* Intel Ethernet Controller XL710 Family Linux Driver
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* Copyright(c) 2013 - 2016 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* The full GNU General Public License is included in this distribution in
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* the file called "COPYING".
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*
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* Contact Information:
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* e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*
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******************************************************************************/
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#ifndef _I40E_TXRX_H_
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#define _I40E_TXRX_H_
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/* Interrupt Throttling and Rate Limiting Goodies */
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#define I40E_MAX_ITR 0x0FF0 /* reg uses 2 usec resolution */
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#define I40E_MIN_ITR 0x0001 /* reg uses 2 usec resolution */
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#define I40E_ITR_100K 0x0005
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#define I40E_ITR_50K 0x000A
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#define I40E_ITR_20K 0x0019
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#define I40E_ITR_18K 0x001B
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#define I40E_ITR_8K 0x003E
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#define I40E_ITR_4K 0x007A
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#define I40E_MAX_INTRL 0x3B /* reg uses 4 usec resolution */
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#define I40E_ITR_RX_DEF I40E_ITR_20K
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#define I40E_ITR_TX_DEF I40E_ITR_20K
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#define I40E_ITR_DYNAMIC 0x8000 /* use top bit as a flag */
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#define I40E_MIN_INT_RATE 250 /* ~= 1000000 / (I40E_MAX_ITR * 2) */
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#define I40E_MAX_INT_RATE 500000 /* == 1000000 / (I40E_MIN_ITR * 2) */
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#define I40E_DEFAULT_IRQ_WORK 256
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#define ITR_TO_REG(setting) ((setting & ~I40E_ITR_DYNAMIC) >> 1)
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#define ITR_IS_DYNAMIC(setting) (!!(setting & I40E_ITR_DYNAMIC))
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#define ITR_REG_TO_USEC(itr_reg) (itr_reg << 1)
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/* 0x40 is the enable bit for interrupt rate limiting, and must be set if
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* the value of the rate limit is non-zero
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*/
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#define INTRL_ENA BIT(6)
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#define INTRL_REG_TO_USEC(intrl) ((intrl & ~INTRL_ENA) << 2)
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#define INTRL_USEC_TO_REG(set) ((set) ? ((set) >> 2) | INTRL_ENA : 0)
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#define I40E_INTRL_8K 125 /* 8000 ints/sec */
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#define I40E_INTRL_62K 16 /* 62500 ints/sec */
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#define I40E_INTRL_83K 12 /* 83333 ints/sec */
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#define I40E_QUEUE_END_OF_LIST 0x7FF
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/* this enum matches hardware bits and is meant to be used by DYN_CTLN
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* registers and QINT registers or more generally anywhere in the manual
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* mentioning ITR_INDX, ITR_NONE cannot be used as an index 'n' into any
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* register but instead is a special value meaning "don't update" ITR0/1/2.
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*/
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enum i40e_dyn_idx_t {
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I40E_IDX_ITR0 = 0,
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I40E_IDX_ITR1 = 1,
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I40E_IDX_ITR2 = 2,
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I40E_ITR_NONE = 3 /* ITR_NONE must not be used as an index */
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};
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/* these are indexes into ITRN registers */
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#define I40E_RX_ITR I40E_IDX_ITR0
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#define I40E_TX_ITR I40E_IDX_ITR1
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#define I40E_PE_ITR I40E_IDX_ITR2
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/* Supported RSS offloads */
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#define I40E_DEFAULT_RSS_HENA ( \
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BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
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BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
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BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \
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BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
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BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV4) | \
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BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \
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BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \
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BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
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BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
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BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV6) | \
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BIT_ULL(I40E_FILTER_PCTYPE_L2_PAYLOAD))
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#define I40E_DEFAULT_RSS_HENA_EXPANDED (I40E_DEFAULT_RSS_HENA | \
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BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \
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BIT_ULL(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \
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BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \
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BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \
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BIT_ULL(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \
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BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
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#define i40e_pf_get_default_rss_hena(pf) \
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(((pf)->flags & I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE) ? \
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I40E_DEFAULT_RSS_HENA_EXPANDED : I40E_DEFAULT_RSS_HENA)
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/* Supported Rx Buffer Sizes (a multiple of 128) */
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#define I40E_RXBUFFER_256 256
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#define I40E_RXBUFFER_2048 2048
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#define I40E_RXBUFFER_3072 3072 /* For FCoE MTU of 2158 */
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#define I40E_RXBUFFER_4096 4096
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#define I40E_RXBUFFER_8192 8192
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#define I40E_MAX_RXBUFFER 9728 /* largest size for single descriptor */
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/* NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we
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* reserve 2 more, and skb_shared_info adds an additional 384 bytes more,
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* this adds up to 512 bytes of extra data meaning the smallest allocation
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* we could have is 1K.
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* i.e. RXBUFFER_256 --> 960 byte skb (size-1024 slab)
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* i.e. RXBUFFER_512 --> 1216 byte skb (size-2048 slab)
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*/
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#define I40E_RX_HDR_SIZE I40E_RXBUFFER_256
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#define i40e_rx_desc i40e_32byte_rx_desc
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/**
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* i40e_test_staterr - tests bits in Rx descriptor status and error fields
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* @rx_desc: pointer to receive descriptor (in le64 format)
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* @stat_err_bits: value to mask
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*
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* This function does some fast chicanery in order to return the
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* value of the mask which is really only used for boolean tests.
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* The status_error_len doesn't need to be shifted because it begins
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* at offset zero.
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*/
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static inline bool i40e_test_staterr(union i40e_rx_desc *rx_desc,
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const u64 stat_err_bits)
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{
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return !!(rx_desc->wb.qword1.status_error_len &
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cpu_to_le64(stat_err_bits));
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}
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/* How many Rx Buffers do we bundle into one write to the hardware ? */
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#define I40E_RX_BUFFER_WRITE 16 /* Must be power of 2 */
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#define I40E_RX_INCREMENT(r, i) \
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do { \
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(i)++; \
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if ((i) == (r)->count) \
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i = 0; \
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r->next_to_clean = i; \
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} while (0)
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#define I40E_RX_NEXT_DESC(r, i, n) \
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do { \
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(i)++; \
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if ((i) == (r)->count) \
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i = 0; \
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(n) = I40E_RX_DESC((r), (i)); \
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} while (0)
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#define I40E_RX_NEXT_DESC_PREFETCH(r, i, n) \
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do { \
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I40E_RX_NEXT_DESC((r), (i), (n)); \
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prefetch((n)); \
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} while (0)
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#define I40E_MAX_BUFFER_TXD 8
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#define I40E_MIN_TX_LEN 17
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/* The size limit for a transmit buffer in a descriptor is (16K - 1).
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* In order to align with the read requests we will align the value to
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* the nearest 4K which represents our maximum read request size.
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*/
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#define I40E_MAX_READ_REQ_SIZE 4096
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#define I40E_MAX_DATA_PER_TXD (16 * 1024 - 1)
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#define I40E_MAX_DATA_PER_TXD_ALIGNED \
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(I40E_MAX_DATA_PER_TXD & ~(I40E_MAX_READ_REQ_SIZE - 1))
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/* This ugly bit of math is equivalent to DIV_ROUNDUP(size, X) where X is
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* the value I40E_MAX_DATA_PER_TXD_ALIGNED. It is needed due to the fact
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* that 12K is not a power of 2 and division is expensive. It is used to
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* approximate the number of descriptors used per linear buffer. Note
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* that this will overestimate in some cases as it doesn't account for the
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* fact that we will add up to 4K - 1 in aligning the 12K buffer, however
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* the error should not impact things much as large buffers usually mean
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* we will use fewer descriptors then there are frags in an skb.
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*/
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static inline unsigned int i40e_txd_use_count(unsigned int size)
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{
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const unsigned int max = I40E_MAX_DATA_PER_TXD_ALIGNED;
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const unsigned int reciprocal = ((1ull << 32) - 1 + (max / 2)) / max;
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unsigned int adjust = ~(u32)0;
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/* if we rounded up on the reciprocal pull down the adjustment */
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if ((max * reciprocal) > adjust)
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adjust = ~(u32)(reciprocal - 1);
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return (u32)((((u64)size * reciprocal) + adjust) >> 32);
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}
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/* Tx Descriptors needed, worst case */
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#define DESC_NEEDED (MAX_SKB_FRAGS + 4)
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#define I40E_MIN_DESC_PENDING 4
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#define I40E_TX_FLAGS_HW_VLAN BIT(1)
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#define I40E_TX_FLAGS_SW_VLAN BIT(2)
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#define I40E_TX_FLAGS_TSO BIT(3)
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#define I40E_TX_FLAGS_IPV4 BIT(4)
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#define I40E_TX_FLAGS_IPV6 BIT(5)
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#define I40E_TX_FLAGS_FCCRC BIT(6)
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#define I40E_TX_FLAGS_FSO BIT(7)
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#define I40E_TX_FLAGS_TSYN BIT(8)
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#define I40E_TX_FLAGS_FD_SB BIT(9)
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#define I40E_TX_FLAGS_UDP_TUNNEL BIT(10)
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#define I40E_TX_FLAGS_VLAN_MASK 0xffff0000
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#define I40E_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000
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#define I40E_TX_FLAGS_VLAN_PRIO_SHIFT 29
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#define I40E_TX_FLAGS_VLAN_SHIFT 16
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struct i40e_tx_buffer {
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struct i40e_tx_desc *next_to_watch;
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union {
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struct sk_buff *skb;
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void *raw_buf;
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};
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unsigned int bytecount;
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unsigned short gso_segs;
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DEFINE_DMA_UNMAP_ADDR(dma);
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DEFINE_DMA_UNMAP_LEN(len);
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u32 tx_flags;
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};
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struct i40e_rx_buffer {
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struct sk_buff *skb;
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dma_addr_t dma;
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struct page *page;
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unsigned int page_offset;
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};
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struct i40e_queue_stats {
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u64 packets;
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u64 bytes;
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};
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struct i40e_tx_queue_stats {
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u64 restart_queue;
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u64 tx_busy;
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u64 tx_done_old;
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u64 tx_linearize;
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u64 tx_force_wb;
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u64 tx_lost_interrupt;
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};
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struct i40e_rx_queue_stats {
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u64 non_eop_descs;
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u64 alloc_page_failed;
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u64 alloc_buff_failed;
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u64 page_reuse_count;
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u64 realloc_count;
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};
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enum i40e_ring_state_t {
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__I40E_TX_FDIR_INIT_DONE,
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__I40E_TX_XPS_INIT_DONE,
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};
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/* some useful defines for virtchannel interface, which
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* is the only remaining user of header split
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*/
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#define I40E_RX_DTYPE_NO_SPLIT 0
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#define I40E_RX_DTYPE_HEADER_SPLIT 1
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#define I40E_RX_DTYPE_SPLIT_ALWAYS 2
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#define I40E_RX_SPLIT_L2 0x1
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#define I40E_RX_SPLIT_IP 0x2
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#define I40E_RX_SPLIT_TCP_UDP 0x4
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#define I40E_RX_SPLIT_SCTP 0x8
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/* struct that defines a descriptor ring, associated with a VSI */
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struct i40e_ring {
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struct i40e_ring *next; /* pointer to next ring in q_vector */
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void *desc; /* Descriptor ring memory */
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struct device *dev; /* Used for DMA mapping */
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struct net_device *netdev; /* netdev ring maps to */
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union {
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struct i40e_tx_buffer *tx_bi;
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struct i40e_rx_buffer *rx_bi;
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};
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unsigned long state;
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u16 queue_index; /* Queue number of ring */
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u8 dcb_tc; /* Traffic class of ring */
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u8 __iomem *tail;
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/* high bit set means dynamic, use accessor routines to read/write.
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* hardware only supports 2us resolution for the ITR registers.
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* these values always store the USER setting, and must be converted
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* before programming to a register.
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*/
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u16 rx_itr_setting;
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u16 tx_itr_setting;
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u16 count; /* Number of descriptors */
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u16 reg_idx; /* HW register index of the ring */
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u16 rx_buf_len;
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/* used in interrupt processing */
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u16 next_to_use;
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u16 next_to_clean;
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u8 atr_sample_rate;
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u8 atr_count;
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unsigned long last_rx_timestamp;
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bool ring_active; /* is ring online or not */
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bool arm_wb; /* do something to arm write back */
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u8 packet_stride;
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u16 flags;
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#define I40E_TXR_FLAGS_WB_ON_ITR BIT(0)
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#define I40E_TXR_FLAGS_LAST_XMIT_MORE_SET BIT(2)
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/* stats structs */
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struct i40e_queue_stats stats;
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struct u64_stats_sync syncp;
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union {
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struct i40e_tx_queue_stats tx_stats;
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struct i40e_rx_queue_stats rx_stats;
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};
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unsigned int size; /* length of descriptor ring in bytes */
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dma_addr_t dma; /* physical address of ring */
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struct i40e_vsi *vsi; /* Backreference to associated VSI */
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struct i40e_q_vector *q_vector; /* Backreference to associated vector */
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struct rcu_head rcu; /* to avoid race on free */
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u16 next_to_alloc;
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} ____cacheline_internodealigned_in_smp;
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enum i40e_latency_range {
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I40E_LOWEST_LATENCY = 0,
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I40E_LOW_LATENCY = 1,
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I40E_BULK_LATENCY = 2,
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I40E_ULTRA_LATENCY = 3,
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};
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struct i40e_ring_container {
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/* array of pointers to rings */
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struct i40e_ring *ring;
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unsigned int total_bytes; /* total bytes processed this int */
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unsigned int total_packets; /* total packets processed this int */
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u16 count;
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enum i40e_latency_range latency_range;
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u16 itr;
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};
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/* iterator for handling rings in ring container */
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#define i40e_for_each_ring(pos, head) \
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for (pos = (head).ring; pos != NULL; pos = pos->next)
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bool i40e_alloc_rx_buffers(struct i40e_ring *rxr, u16 cleaned_count);
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netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
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void i40e_clean_tx_ring(struct i40e_ring *tx_ring);
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void i40e_clean_rx_ring(struct i40e_ring *rx_ring);
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int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring);
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int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring);
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void i40e_free_tx_resources(struct i40e_ring *tx_ring);
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void i40e_free_rx_resources(struct i40e_ring *rx_ring);
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int i40e_napi_poll(struct napi_struct *napi, int budget);
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#ifdef I40E_FCOE
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void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
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struct i40e_tx_buffer *first, u32 tx_flags,
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const u8 hdr_len, u32 td_cmd, u32 td_offset);
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int i40e_tx_prepare_vlan_flags(struct sk_buff *skb,
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struct i40e_ring *tx_ring, u32 *flags);
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#endif
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void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector);
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u32 i40e_get_tx_pending(struct i40e_ring *ring, bool in_sw);
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int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size);
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bool __i40e_chk_linearize(struct sk_buff *skb);
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/**
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* i40e_get_head - Retrieve head from head writeback
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* @tx_ring: tx ring to fetch head of
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*
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* Returns value of Tx ring head based on value stored
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* in head write-back location
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**/
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static inline u32 i40e_get_head(struct i40e_ring *tx_ring)
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{
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void *head = (struct i40e_tx_desc *)tx_ring->desc + tx_ring->count;
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return le32_to_cpu(*(volatile __le32 *)head);
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}
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/**
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* i40e_xmit_descriptor_count - calculate number of Tx descriptors needed
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* @skb: send buffer
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* @tx_ring: ring to send buffer on
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*
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* Returns number of data descriptors needed for this skb. Returns 0 to indicate
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* there is not enough descriptors available in this ring since we need at least
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* one descriptor.
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**/
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static inline int i40e_xmit_descriptor_count(struct sk_buff *skb)
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{
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const struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
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unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
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int count = 0, size = skb_headlen(skb);
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for (;;) {
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count += i40e_txd_use_count(size);
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if (!nr_frags--)
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break;
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size = skb_frag_size(frag++);
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}
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return count;
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}
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/**
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* i40e_maybe_stop_tx - 1st level check for Tx stop conditions
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* @tx_ring: the ring to be checked
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* @size: the size buffer we want to assure is available
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|
*
|
|
* Returns 0 if stop is not needed
|
|
**/
|
|
static inline int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
|
|
{
|
|
if (likely(I40E_DESC_UNUSED(tx_ring) >= size))
|
|
return 0;
|
|
return __i40e_maybe_stop_tx(tx_ring, size);
|
|
}
|
|
|
|
/**
|
|
* i40e_chk_linearize - Check if there are more than 8 fragments per packet
|
|
* @skb: send buffer
|
|
* @count: number of buffers used
|
|
*
|
|
* Note: Our HW can't scatter-gather more than 8 fragments to build
|
|
* a packet on the wire and so we need to figure out the cases where we
|
|
* need to linearize the skb.
|
|
**/
|
|
static inline bool i40e_chk_linearize(struct sk_buff *skb, int count)
|
|
{
|
|
/* Both TSO and single send will work if count is less than 8 */
|
|
if (likely(count < I40E_MAX_BUFFER_TXD))
|
|
return false;
|
|
|
|
if (skb_is_gso(skb))
|
|
return __i40e_chk_linearize(skb);
|
|
|
|
/* we can support up to 8 data buffers for a single send */
|
|
return count != I40E_MAX_BUFFER_TXD;
|
|
}
|
|
|
|
/**
|
|
* i40e_rx_is_fcoe - returns true if the Rx packet type is FCoE
|
|
* @ptype: the packet type field from Rx descriptor write-back
|
|
**/
|
|
static inline bool i40e_rx_is_fcoe(u16 ptype)
|
|
{
|
|
return (ptype >= I40E_RX_PTYPE_L2_FCOE_PAY3) &&
|
|
(ptype <= I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER);
|
|
}
|
|
|
|
/**
|
|
* txring_txq - Find the netdev Tx ring based on the i40e Tx ring
|
|
* @ring: Tx ring to find the netdev equivalent of
|
|
**/
|
|
static inline struct netdev_queue *txring_txq(const struct i40e_ring *ring)
|
|
{
|
|
return netdev_get_tx_queue(ring->netdev, ring->queue_index);
|
|
}
|
|
#endif /* _I40E_TXRX_H_ */
|