1031 lines
30 KiB
C
1031 lines
30 KiB
C
/*******************************************************************************
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Intel 10 Gigabit PCI Express Linux driver
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Copyright(c) 1999 - 2016 Intel Corporation.
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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Contact Information:
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Linux NICS <linux.nics@intel.com>
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e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*******************************************************************************/
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#ifndef _IXGBE_H_
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#define _IXGBE_H_
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#include <linux/bitops.h>
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/netdevice.h>
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#include <linux/cpumask.h>
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#include <linux/aer.h>
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#include <linux/if_vlan.h>
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#include <linux/jiffies.h>
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#include <linux/timecounter.h>
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#include <linux/net_tstamp.h>
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#include <linux/ptp_clock_kernel.h>
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#include "ixgbe_type.h"
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#include "ixgbe_common.h"
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#include "ixgbe_dcb.h"
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#if IS_ENABLED(CONFIG_FCOE)
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#define IXGBE_FCOE
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#include "ixgbe_fcoe.h"
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#endif /* IS_ENABLED(CONFIG_FCOE) */
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#ifdef CONFIG_IXGBE_DCA
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#include <linux/dca.h>
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#endif
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#include <net/busy_poll.h>
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#ifdef CONFIG_NET_RX_BUSY_POLL
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#define BP_EXTENDED_STATS
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#endif
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/* common prefix used by pr_<> macros */
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#undef pr_fmt
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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/* TX/RX descriptor defines */
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#define IXGBE_DEFAULT_TXD 512
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#define IXGBE_DEFAULT_TX_WORK 256
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#define IXGBE_MAX_TXD 4096
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#define IXGBE_MIN_TXD 64
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#if (PAGE_SIZE < 8192)
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#define IXGBE_DEFAULT_RXD 512
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#else
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#define IXGBE_DEFAULT_RXD 128
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#endif
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#define IXGBE_MAX_RXD 4096
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#define IXGBE_MIN_RXD 64
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#define IXGBE_ETH_P_LLDP 0x88CC
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/* flow control */
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#define IXGBE_MIN_FCRTL 0x40
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#define IXGBE_MAX_FCRTL 0x7FF80
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#define IXGBE_MIN_FCRTH 0x600
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#define IXGBE_MAX_FCRTH 0x7FFF0
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#define IXGBE_DEFAULT_FCPAUSE 0xFFFF
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#define IXGBE_MIN_FCPAUSE 0
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#define IXGBE_MAX_FCPAUSE 0xFFFF
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/* Supported Rx Buffer Sizes */
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#define IXGBE_RXBUFFER_256 256 /* Used for skb receive header */
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#define IXGBE_RXBUFFER_2K 2048
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#define IXGBE_RXBUFFER_3K 3072
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#define IXGBE_RXBUFFER_4K 4096
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#define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */
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/*
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* NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we
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* reserve 64 more, and skb_shared_info adds an additional 320 bytes more,
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* this adds up to 448 bytes of extra data.
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*
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* Since netdev_alloc_skb now allocates a page fragment we can use a value
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* of 256 and the resultant skb will have a truesize of 960 or less.
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*/
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#define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256
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/* How many Rx Buffers do we bundle into one write to the hardware ? */
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#define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
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enum ixgbe_tx_flags {
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/* cmd_type flags */
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IXGBE_TX_FLAGS_HW_VLAN = 0x01,
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IXGBE_TX_FLAGS_TSO = 0x02,
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IXGBE_TX_FLAGS_TSTAMP = 0x04,
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/* olinfo flags */
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IXGBE_TX_FLAGS_CC = 0x08,
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IXGBE_TX_FLAGS_IPV4 = 0x10,
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IXGBE_TX_FLAGS_CSUM = 0x20,
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/* software defined flags */
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IXGBE_TX_FLAGS_SW_VLAN = 0x40,
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IXGBE_TX_FLAGS_FCOE = 0x80,
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};
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/* VLAN info */
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#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
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#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000
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#define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29
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#define IXGBE_TX_FLAGS_VLAN_SHIFT 16
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#define IXGBE_MAX_VF_MC_ENTRIES 30
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#define IXGBE_MAX_VF_FUNCTIONS 64
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#define IXGBE_MAX_VFTA_ENTRIES 128
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#define MAX_EMULATION_MAC_ADDRS 16
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#define IXGBE_MAX_PF_MACVLANS 15
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#define VMDQ_P(p) ((p) + adapter->ring_feature[RING_F_VMDQ].offset)
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#define IXGBE_82599_VF_DEVICE_ID 0x10ED
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#define IXGBE_X540_VF_DEVICE_ID 0x1515
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struct vf_data_storage {
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struct pci_dev *vfdev;
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unsigned char vf_mac_addresses[ETH_ALEN];
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u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
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u16 num_vf_mc_hashes;
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bool clear_to_send;
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bool pf_set_mac;
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u16 pf_vlan; /* When set, guest VLAN config not allowed. */
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u16 pf_qos;
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u16 tx_rate;
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u8 spoofchk_enabled;
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bool rss_query_enabled;
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u8 trusted;
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int xcast_mode;
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unsigned int vf_api;
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};
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enum ixgbevf_xcast_modes {
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IXGBEVF_XCAST_MODE_NONE = 0,
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IXGBEVF_XCAST_MODE_MULTI,
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IXGBEVF_XCAST_MODE_ALLMULTI,
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};
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struct vf_macvlans {
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struct list_head l;
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int vf;
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bool free;
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bool is_macvlan;
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u8 vf_macvlan[ETH_ALEN];
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};
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#define IXGBE_MAX_TXD_PWR 14
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#define IXGBE_MAX_DATA_PER_TXD (1u << IXGBE_MAX_TXD_PWR)
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/* Tx Descriptors needed, worst case */
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#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD)
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#define DESC_NEEDED (MAX_SKB_FRAGS + 4)
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/* wrapper around a pointer to a socket buffer,
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* so a DMA handle can be stored along with the buffer */
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struct ixgbe_tx_buffer {
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union ixgbe_adv_tx_desc *next_to_watch;
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unsigned long time_stamp;
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struct sk_buff *skb;
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unsigned int bytecount;
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unsigned short gso_segs;
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__be16 protocol;
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DEFINE_DMA_UNMAP_ADDR(dma);
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DEFINE_DMA_UNMAP_LEN(len);
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u32 tx_flags;
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};
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struct ixgbe_rx_buffer {
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struct sk_buff *skb;
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dma_addr_t dma;
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struct page *page;
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unsigned int page_offset;
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};
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struct ixgbe_queue_stats {
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u64 packets;
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u64 bytes;
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#ifdef BP_EXTENDED_STATS
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u64 yields;
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u64 misses;
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u64 cleaned;
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#endif /* BP_EXTENDED_STATS */
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};
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struct ixgbe_tx_queue_stats {
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u64 restart_queue;
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u64 tx_busy;
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u64 tx_done_old;
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};
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struct ixgbe_rx_queue_stats {
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u64 rsc_count;
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u64 rsc_flush;
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u64 non_eop_descs;
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u64 alloc_rx_page_failed;
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u64 alloc_rx_buff_failed;
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u64 csum_err;
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};
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#define IXGBE_TS_HDR_LEN 8
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enum ixgbe_ring_state_t {
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__IXGBE_TX_FDIR_INIT_DONE,
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__IXGBE_TX_XPS_INIT_DONE,
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__IXGBE_TX_DETECT_HANG,
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__IXGBE_HANG_CHECK_ARMED,
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__IXGBE_RX_RSC_ENABLED,
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__IXGBE_RX_CSUM_UDP_ZERO_ERR,
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__IXGBE_RX_FCOE,
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};
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struct ixgbe_fwd_adapter {
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unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
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struct net_device *netdev;
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struct ixgbe_adapter *real_adapter;
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unsigned int tx_base_queue;
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unsigned int rx_base_queue;
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int pool;
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};
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#define check_for_tx_hang(ring) \
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test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
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#define set_check_for_tx_hang(ring) \
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set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
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#define clear_check_for_tx_hang(ring) \
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clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
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#define ring_is_rsc_enabled(ring) \
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test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
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#define set_ring_rsc_enabled(ring) \
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set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
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#define clear_ring_rsc_enabled(ring) \
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clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
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struct ixgbe_ring {
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struct ixgbe_ring *next; /* pointer to next ring in q_vector */
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struct ixgbe_q_vector *q_vector; /* backpointer to host q_vector */
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struct net_device *netdev; /* netdev ring belongs to */
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struct device *dev; /* device for DMA mapping */
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struct ixgbe_fwd_adapter *l2_accel_priv;
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void *desc; /* descriptor ring memory */
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union {
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struct ixgbe_tx_buffer *tx_buffer_info;
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struct ixgbe_rx_buffer *rx_buffer_info;
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};
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unsigned long state;
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u8 __iomem *tail;
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dma_addr_t dma; /* phys. address of descriptor ring */
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unsigned int size; /* length in bytes */
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u16 count; /* amount of descriptors */
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u8 queue_index; /* needed for multiqueue queue management */
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u8 reg_idx; /* holds the special value that gets
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* the hardware register offset
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* associated with this ring, which is
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* different for DCB and RSS modes
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*/
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u16 next_to_use;
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u16 next_to_clean;
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unsigned long last_rx_timestamp;
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union {
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u16 next_to_alloc;
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struct {
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u8 atr_sample_rate;
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u8 atr_count;
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};
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};
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u8 dcb_tc;
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struct ixgbe_queue_stats stats;
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struct u64_stats_sync syncp;
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union {
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struct ixgbe_tx_queue_stats tx_stats;
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struct ixgbe_rx_queue_stats rx_stats;
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};
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} ____cacheline_internodealigned_in_smp;
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enum ixgbe_ring_f_enum {
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RING_F_NONE = 0,
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RING_F_VMDQ, /* SR-IOV uses the same ring feature */
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RING_F_RSS,
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RING_F_FDIR,
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#ifdef IXGBE_FCOE
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RING_F_FCOE,
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#endif /* IXGBE_FCOE */
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RING_F_ARRAY_SIZE /* must be last in enum set */
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};
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#define IXGBE_MAX_RSS_INDICES 16
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#define IXGBE_MAX_RSS_INDICES_X550 63
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#define IXGBE_MAX_VMDQ_INDICES 64
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#define IXGBE_MAX_FDIR_INDICES 63 /* based on q_vector limit */
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#define IXGBE_MAX_FCOE_INDICES 8
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#define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1)
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#define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1)
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#define IXGBE_MAX_L2A_QUEUES 4
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#define IXGBE_BAD_L2A_QUEUE 3
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#define IXGBE_MAX_MACVLANS 31
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#define IXGBE_MAX_DCBMACVLANS 8
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struct ixgbe_ring_feature {
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u16 limit; /* upper limit on feature indices */
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u16 indices; /* current value of indices */
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u16 mask; /* Mask used for feature to ring mapping */
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u16 offset; /* offset to start of feature */
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} ____cacheline_internodealigned_in_smp;
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#define IXGBE_82599_VMDQ_8Q_MASK 0x78
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#define IXGBE_82599_VMDQ_4Q_MASK 0x7C
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#define IXGBE_82599_VMDQ_2Q_MASK 0x7E
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/*
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* FCoE requires that all Rx buffers be over 2200 bytes in length. Since
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* this is twice the size of a half page we need to double the page order
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* for FCoE enabled Rx queues.
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*/
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static inline unsigned int ixgbe_rx_bufsz(struct ixgbe_ring *ring)
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{
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#ifdef IXGBE_FCOE
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if (test_bit(__IXGBE_RX_FCOE, &ring->state))
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return (PAGE_SIZE < 8192) ? IXGBE_RXBUFFER_4K :
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IXGBE_RXBUFFER_3K;
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#endif
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return IXGBE_RXBUFFER_2K;
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}
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static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring *ring)
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{
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#ifdef IXGBE_FCOE
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if (test_bit(__IXGBE_RX_FCOE, &ring->state))
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return (PAGE_SIZE < 8192) ? 1 : 0;
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#endif
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return 0;
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}
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#define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring))
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struct ixgbe_ring_container {
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struct ixgbe_ring *ring; /* pointer to linked list of rings */
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unsigned int total_bytes; /* total bytes processed this int */
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unsigned int total_packets; /* total packets processed this int */
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u16 work_limit; /* total work allowed per interrupt */
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u8 count; /* total number of rings in vector */
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u8 itr; /* current ITR setting for ring */
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};
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/* iterator for handling rings in ring container */
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#define ixgbe_for_each_ring(pos, head) \
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for (pos = (head).ring; pos != NULL; pos = pos->next)
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#define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
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? 8 : 1)
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#define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
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/* MAX_Q_VECTORS of these are allocated,
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* but we only use one per queue-specific vector.
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*/
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struct ixgbe_q_vector {
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struct ixgbe_adapter *adapter;
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#ifdef CONFIG_IXGBE_DCA
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int cpu; /* CPU for DCA */
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#endif
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u16 v_idx; /* index of q_vector within array, also used for
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* finding the bit in EICR and friends that
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* represents the vector for this ring */
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u16 itr; /* Interrupt throttle rate written to EITR */
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struct ixgbe_ring_container rx, tx;
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struct napi_struct napi;
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cpumask_t affinity_mask;
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int numa_node;
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struct rcu_head rcu; /* to avoid race with update stats on free */
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char name[IFNAMSIZ + 9];
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#ifdef CONFIG_NET_RX_BUSY_POLL
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atomic_t state;
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#endif /* CONFIG_NET_RX_BUSY_POLL */
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/* for dynamic allocation of rings associated with this q_vector */
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struct ixgbe_ring ring[0] ____cacheline_internodealigned_in_smp;
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};
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#ifdef CONFIG_NET_RX_BUSY_POLL
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enum ixgbe_qv_state_t {
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IXGBE_QV_STATE_IDLE = 0,
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IXGBE_QV_STATE_NAPI,
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IXGBE_QV_STATE_POLL,
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IXGBE_QV_STATE_DISABLE
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};
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static inline void ixgbe_qv_init_lock(struct ixgbe_q_vector *q_vector)
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{
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/* reset state to idle */
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atomic_set(&q_vector->state, IXGBE_QV_STATE_IDLE);
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}
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/* called from the device poll routine to get ownership of a q_vector */
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static inline bool ixgbe_qv_lock_napi(struct ixgbe_q_vector *q_vector)
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{
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int rc = atomic_cmpxchg(&q_vector->state, IXGBE_QV_STATE_IDLE,
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IXGBE_QV_STATE_NAPI);
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#ifdef BP_EXTENDED_STATS
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if (rc != IXGBE_QV_STATE_IDLE)
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q_vector->tx.ring->stats.yields++;
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#endif
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return rc == IXGBE_QV_STATE_IDLE;
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}
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/* returns true is someone tried to get the qv while napi had it */
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static inline void ixgbe_qv_unlock_napi(struct ixgbe_q_vector *q_vector)
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{
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WARN_ON(atomic_read(&q_vector->state) != IXGBE_QV_STATE_NAPI);
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/* flush any outstanding Rx frames */
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if (q_vector->napi.gro_list)
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napi_gro_flush(&q_vector->napi, false);
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/* reset state to idle */
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atomic_set(&q_vector->state, IXGBE_QV_STATE_IDLE);
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}
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/* called from ixgbe_low_latency_poll() */
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static inline bool ixgbe_qv_lock_poll(struct ixgbe_q_vector *q_vector)
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{
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int rc = atomic_cmpxchg(&q_vector->state, IXGBE_QV_STATE_IDLE,
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IXGBE_QV_STATE_POLL);
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#ifdef BP_EXTENDED_STATS
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if (rc != IXGBE_QV_STATE_IDLE)
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q_vector->rx.ring->stats.yields++;
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#endif
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return rc == IXGBE_QV_STATE_IDLE;
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}
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/* returns true if someone tried to get the qv while it was locked */
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static inline void ixgbe_qv_unlock_poll(struct ixgbe_q_vector *q_vector)
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{
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WARN_ON(atomic_read(&q_vector->state) != IXGBE_QV_STATE_POLL);
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/* reset state to idle */
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atomic_set(&q_vector->state, IXGBE_QV_STATE_IDLE);
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}
|
|
|
|
/* true if a socket is polling, even if it did not get the lock */
|
|
static inline bool ixgbe_qv_busy_polling(struct ixgbe_q_vector *q_vector)
|
|
{
|
|
return atomic_read(&q_vector->state) == IXGBE_QV_STATE_POLL;
|
|
}
|
|
|
|
/* false if QV is currently owned */
|
|
static inline bool ixgbe_qv_disable(struct ixgbe_q_vector *q_vector)
|
|
{
|
|
int rc = atomic_cmpxchg(&q_vector->state, IXGBE_QV_STATE_IDLE,
|
|
IXGBE_QV_STATE_DISABLE);
|
|
|
|
return rc == IXGBE_QV_STATE_IDLE;
|
|
}
|
|
|
|
#else /* CONFIG_NET_RX_BUSY_POLL */
|
|
static inline void ixgbe_qv_init_lock(struct ixgbe_q_vector *q_vector)
|
|
{
|
|
}
|
|
|
|
static inline bool ixgbe_qv_lock_napi(struct ixgbe_q_vector *q_vector)
|
|
{
|
|
return true;
|
|
}
|
|
|
|
static inline bool ixgbe_qv_unlock_napi(struct ixgbe_q_vector *q_vector)
|
|
{
|
|
return false;
|
|
}
|
|
|
|
static inline bool ixgbe_qv_lock_poll(struct ixgbe_q_vector *q_vector)
|
|
{
|
|
return false;
|
|
}
|
|
|
|
static inline bool ixgbe_qv_unlock_poll(struct ixgbe_q_vector *q_vector)
|
|
{
|
|
return false;
|
|
}
|
|
|
|
static inline bool ixgbe_qv_busy_polling(struct ixgbe_q_vector *q_vector)
|
|
{
|
|
return false;
|
|
}
|
|
|
|
static inline bool ixgbe_qv_disable(struct ixgbe_q_vector *q_vector)
|
|
{
|
|
return true;
|
|
}
|
|
|
|
#endif /* CONFIG_NET_RX_BUSY_POLL */
|
|
|
|
#ifdef CONFIG_IXGBE_HWMON
|
|
|
|
#define IXGBE_HWMON_TYPE_LOC 0
|
|
#define IXGBE_HWMON_TYPE_TEMP 1
|
|
#define IXGBE_HWMON_TYPE_CAUTION 2
|
|
#define IXGBE_HWMON_TYPE_MAX 3
|
|
|
|
struct hwmon_attr {
|
|
struct device_attribute dev_attr;
|
|
struct ixgbe_hw *hw;
|
|
struct ixgbe_thermal_diode_data *sensor;
|
|
char name[12];
|
|
};
|
|
|
|
struct hwmon_buff {
|
|
struct attribute_group group;
|
|
const struct attribute_group *groups[2];
|
|
struct attribute *attrs[IXGBE_MAX_SENSORS * 4 + 1];
|
|
struct hwmon_attr hwmon_list[IXGBE_MAX_SENSORS * 4];
|
|
unsigned int n_hwmon;
|
|
};
|
|
#endif /* CONFIG_IXGBE_HWMON */
|
|
|
|
/*
|
|
* microsecond values for various ITR rates shifted by 2 to fit itr register
|
|
* with the first 3 bits reserved 0
|
|
*/
|
|
#define IXGBE_MIN_RSC_ITR 24
|
|
#define IXGBE_100K_ITR 40
|
|
#define IXGBE_20K_ITR 200
|
|
#define IXGBE_12K_ITR 336
|
|
|
|
/* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */
|
|
static inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc,
|
|
const u32 stat_err_bits)
|
|
{
|
|
return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
|
|
}
|
|
|
|
static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring)
|
|
{
|
|
u16 ntc = ring->next_to_clean;
|
|
u16 ntu = ring->next_to_use;
|
|
|
|
return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
|
|
}
|
|
|
|
#define IXGBE_RX_DESC(R, i) \
|
|
(&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
|
|
#define IXGBE_TX_DESC(R, i) \
|
|
(&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
|
|
#define IXGBE_TX_CTXTDESC(R, i) \
|
|
(&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
|
|
|
|
#define IXGBE_MAX_JUMBO_FRAME_SIZE 9728 /* Maximum Supported Size 9.5KB */
|
|
#ifdef IXGBE_FCOE
|
|
/* Use 3K as the baby jumbo frame size for FCoE */
|
|
#define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072
|
|
#endif /* IXGBE_FCOE */
|
|
|
|
#define OTHER_VECTOR 1
|
|
#define NON_Q_VECTORS (OTHER_VECTOR)
|
|
|
|
#define MAX_MSIX_VECTORS_82599 64
|
|
#define MAX_Q_VECTORS_82599 64
|
|
#define MAX_MSIX_VECTORS_82598 18
|
|
#define MAX_Q_VECTORS_82598 16
|
|
|
|
struct ixgbe_mac_addr {
|
|
u8 addr[ETH_ALEN];
|
|
u16 pool;
|
|
u16 state; /* bitmask */
|
|
};
|
|
|
|
#define IXGBE_MAC_STATE_DEFAULT 0x1
|
|
#define IXGBE_MAC_STATE_MODIFIED 0x2
|
|
#define IXGBE_MAC_STATE_IN_USE 0x4
|
|
|
|
#define MAX_Q_VECTORS MAX_Q_VECTORS_82599
|
|
#define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
|
|
|
|
#define MIN_MSIX_Q_VECTORS 1
|
|
#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
|
|
|
|
/* default to trying for four seconds */
|
|
#define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
|
|
#define IXGBE_SFP_POLL_JIFFIES (2 * HZ) /* SFP poll every 2 seconds */
|
|
|
|
/* board specific private data structure */
|
|
struct ixgbe_adapter {
|
|
unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
|
|
/* OS defined structs */
|
|
struct net_device *netdev;
|
|
struct pci_dev *pdev;
|
|
|
|
unsigned long state;
|
|
|
|
/* Some features need tri-state capability,
|
|
* thus the additional *_CAPABLE flags.
|
|
*/
|
|
u32 flags;
|
|
#define IXGBE_FLAG_MSI_ENABLED BIT(1)
|
|
#define IXGBE_FLAG_MSIX_ENABLED BIT(3)
|
|
#define IXGBE_FLAG_RX_1BUF_CAPABLE BIT(4)
|
|
#define IXGBE_FLAG_RX_PS_CAPABLE BIT(5)
|
|
#define IXGBE_FLAG_RX_PS_ENABLED BIT(6)
|
|
#define IXGBE_FLAG_DCA_ENABLED BIT(8)
|
|
#define IXGBE_FLAG_DCA_CAPABLE BIT(9)
|
|
#define IXGBE_FLAG_IMIR_ENABLED BIT(10)
|
|
#define IXGBE_FLAG_MQ_CAPABLE BIT(11)
|
|
#define IXGBE_FLAG_DCB_ENABLED BIT(12)
|
|
#define IXGBE_FLAG_VMDQ_CAPABLE BIT(13)
|
|
#define IXGBE_FLAG_VMDQ_ENABLED BIT(14)
|
|
#define IXGBE_FLAG_FAN_FAIL_CAPABLE BIT(15)
|
|
#define IXGBE_FLAG_NEED_LINK_UPDATE BIT(16)
|
|
#define IXGBE_FLAG_NEED_LINK_CONFIG BIT(17)
|
|
#define IXGBE_FLAG_FDIR_HASH_CAPABLE BIT(18)
|
|
#define IXGBE_FLAG_FDIR_PERFECT_CAPABLE BIT(19)
|
|
#define IXGBE_FLAG_FCOE_CAPABLE BIT(20)
|
|
#define IXGBE_FLAG_FCOE_ENABLED BIT(21)
|
|
#define IXGBE_FLAG_SRIOV_CAPABLE BIT(22)
|
|
#define IXGBE_FLAG_SRIOV_ENABLED BIT(23)
|
|
#define IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE BIT(24)
|
|
#define IXGBE_FLAG_RX_HWTSTAMP_ENABLED BIT(25)
|
|
#define IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER BIT(26)
|
|
#define IXGBE_FLAG_DCB_CAPABLE BIT(27)
|
|
#define IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE BIT(28)
|
|
|
|
u32 flags2;
|
|
#define IXGBE_FLAG2_RSC_CAPABLE BIT(0)
|
|
#define IXGBE_FLAG2_RSC_ENABLED BIT(1)
|
|
#define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE BIT(2)
|
|
#define IXGBE_FLAG2_TEMP_SENSOR_EVENT BIT(3)
|
|
#define IXGBE_FLAG2_SEARCH_FOR_SFP BIT(4)
|
|
#define IXGBE_FLAG2_SFP_NEEDS_RESET BIT(5)
|
|
#define IXGBE_FLAG2_FDIR_REQUIRES_REINIT BIT(7)
|
|
#define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP BIT(8)
|
|
#define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP BIT(9)
|
|
#define IXGBE_FLAG2_PTP_PPS_ENABLED BIT(10)
|
|
#define IXGBE_FLAG2_PHY_INTERRUPT BIT(11)
|
|
#define IXGBE_FLAG2_UDP_TUN_REREG_NEEDED BIT(12)
|
|
#define IXGBE_FLAG2_VLAN_PROMISC BIT(13)
|
|
|
|
/* Tx fast path data */
|
|
int num_tx_queues;
|
|
u16 tx_itr_setting;
|
|
u16 tx_work_limit;
|
|
|
|
/* Rx fast path data */
|
|
int num_rx_queues;
|
|
u16 rx_itr_setting;
|
|
|
|
/* Port number used to identify VXLAN traffic */
|
|
__be16 vxlan_port;
|
|
__be16 geneve_port;
|
|
|
|
/* TX */
|
|
struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp;
|
|
|
|
u64 restart_queue;
|
|
u64 lsc_int;
|
|
u32 tx_timeout_count;
|
|
|
|
/* RX */
|
|
struct ixgbe_ring *rx_ring[MAX_RX_QUEUES];
|
|
int num_rx_pools; /* == num_rx_queues in 82598 */
|
|
int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */
|
|
u64 hw_csum_rx_error;
|
|
u64 hw_rx_no_dma_resources;
|
|
u64 rsc_total_count;
|
|
u64 rsc_total_flush;
|
|
u64 non_eop_descs;
|
|
u32 alloc_rx_page_failed;
|
|
u32 alloc_rx_buff_failed;
|
|
|
|
struct ixgbe_q_vector *q_vector[MAX_Q_VECTORS];
|
|
|
|
/* DCB parameters */
|
|
struct ieee_pfc *ixgbe_ieee_pfc;
|
|
struct ieee_ets *ixgbe_ieee_ets;
|
|
struct ixgbe_dcb_config dcb_cfg;
|
|
struct ixgbe_dcb_config temp_dcb_cfg;
|
|
u8 dcb_set_bitmap;
|
|
u8 dcbx_cap;
|
|
enum ixgbe_fc_mode last_lfc_mode;
|
|
|
|
int num_q_vectors; /* current number of q_vectors for device */
|
|
int max_q_vectors; /* true count of q_vectors for device */
|
|
struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
|
|
struct msix_entry *msix_entries;
|
|
|
|
u32 test_icr;
|
|
struct ixgbe_ring test_tx_ring;
|
|
struct ixgbe_ring test_rx_ring;
|
|
|
|
/* structs defined in ixgbe_hw.h */
|
|
struct ixgbe_hw hw;
|
|
u16 msg_enable;
|
|
struct ixgbe_hw_stats stats;
|
|
|
|
u64 tx_busy;
|
|
unsigned int tx_ring_count;
|
|
unsigned int rx_ring_count;
|
|
|
|
u32 link_speed;
|
|
bool link_up;
|
|
unsigned long sfp_poll_time;
|
|
unsigned long link_check_timeout;
|
|
|
|
struct timer_list service_timer;
|
|
struct work_struct service_task;
|
|
|
|
struct hlist_head fdir_filter_list;
|
|
unsigned long fdir_overflow; /* number of times ATR was backed off */
|
|
union ixgbe_atr_input fdir_mask;
|
|
int fdir_filter_count;
|
|
u32 fdir_pballoc;
|
|
u32 atr_sample_rate;
|
|
spinlock_t fdir_perfect_lock;
|
|
|
|
#ifdef IXGBE_FCOE
|
|
struct ixgbe_fcoe fcoe;
|
|
#endif /* IXGBE_FCOE */
|
|
u8 __iomem *io_addr; /* Mainly for iounmap use */
|
|
u32 wol;
|
|
|
|
u16 bridge_mode;
|
|
|
|
u16 eeprom_verh;
|
|
u16 eeprom_verl;
|
|
u16 eeprom_cap;
|
|
|
|
u32 interrupt_event;
|
|
u32 led_reg;
|
|
|
|
struct ptp_clock *ptp_clock;
|
|
struct ptp_clock_info ptp_caps;
|
|
struct work_struct ptp_tx_work;
|
|
struct sk_buff *ptp_tx_skb;
|
|
struct hwtstamp_config tstamp_config;
|
|
unsigned long ptp_tx_start;
|
|
unsigned long last_overflow_check;
|
|
unsigned long last_rx_ptp_check;
|
|
unsigned long last_rx_timestamp;
|
|
spinlock_t tmreg_lock;
|
|
struct cyclecounter hw_cc;
|
|
struct timecounter hw_tc;
|
|
u32 base_incval;
|
|
u32 tx_hwtstamp_timeouts;
|
|
u32 rx_hwtstamp_cleared;
|
|
void (*ptp_setup_sdp)(struct ixgbe_adapter *);
|
|
|
|
/* SR-IOV */
|
|
DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
|
|
unsigned int num_vfs;
|
|
struct vf_data_storage *vfinfo;
|
|
int vf_rate_link_speed;
|
|
struct vf_macvlans vf_mvs;
|
|
struct vf_macvlans *mv_list;
|
|
|
|
u32 timer_event_accumulator;
|
|
u32 vferr_refcount;
|
|
struct ixgbe_mac_addr *mac_table;
|
|
struct kobject *info_kobj;
|
|
#ifdef CONFIG_IXGBE_HWMON
|
|
struct hwmon_buff *ixgbe_hwmon_buff;
|
|
#endif /* CONFIG_IXGBE_HWMON */
|
|
#ifdef CONFIG_DEBUG_FS
|
|
struct dentry *ixgbe_dbg_adapter;
|
|
#endif /*CONFIG_DEBUG_FS*/
|
|
|
|
u8 default_up;
|
|
unsigned long fwd_bitmask; /* Bitmask indicating in use pools */
|
|
|
|
#define IXGBE_MAX_LINK_HANDLE 10
|
|
struct ixgbe_jump_table *jump_tables[IXGBE_MAX_LINK_HANDLE];
|
|
unsigned long tables;
|
|
|
|
/* maximum number of RETA entries among all devices supported by ixgbe
|
|
* driver: currently it's x550 device in non-SRIOV mode
|
|
*/
|
|
#define IXGBE_MAX_RETA_ENTRIES 512
|
|
u8 rss_indir_tbl[IXGBE_MAX_RETA_ENTRIES];
|
|
|
|
#define IXGBE_RSS_KEY_SIZE 40 /* size of RSS Hash Key in bytes */
|
|
u32 rss_key[IXGBE_RSS_KEY_SIZE / sizeof(u32)];
|
|
};
|
|
|
|
static inline u8 ixgbe_max_rss_indices(struct ixgbe_adapter *adapter)
|
|
{
|
|
switch (adapter->hw.mac.type) {
|
|
case ixgbe_mac_82598EB:
|
|
case ixgbe_mac_82599EB:
|
|
case ixgbe_mac_X540:
|
|
return IXGBE_MAX_RSS_INDICES;
|
|
case ixgbe_mac_X550:
|
|
case ixgbe_mac_X550EM_x:
|
|
case ixgbe_mac_x550em_a:
|
|
return IXGBE_MAX_RSS_INDICES_X550;
|
|
default:
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
struct ixgbe_fdir_filter {
|
|
struct hlist_node fdir_node;
|
|
union ixgbe_atr_input filter;
|
|
u16 sw_idx;
|
|
u64 action;
|
|
};
|
|
|
|
enum ixgbe_state_t {
|
|
__IXGBE_TESTING,
|
|
__IXGBE_RESETTING,
|
|
__IXGBE_DOWN,
|
|
__IXGBE_DISABLED,
|
|
__IXGBE_REMOVING,
|
|
__IXGBE_SERVICE_SCHED,
|
|
__IXGBE_SERVICE_INITED,
|
|
__IXGBE_IN_SFP_INIT,
|
|
__IXGBE_PTP_RUNNING,
|
|
__IXGBE_PTP_TX_IN_PROGRESS,
|
|
__IXGBE_RESET_REQUESTED,
|
|
};
|
|
|
|
struct ixgbe_cb {
|
|
union { /* Union defining head/tail partner */
|
|
struct sk_buff *head;
|
|
struct sk_buff *tail;
|
|
};
|
|
dma_addr_t dma;
|
|
u16 append_cnt;
|
|
bool page_released;
|
|
};
|
|
#define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb)
|
|
|
|
enum ixgbe_boards {
|
|
board_82598,
|
|
board_82599,
|
|
board_X540,
|
|
board_X550,
|
|
board_X550EM_x,
|
|
board_x550em_a,
|
|
};
|
|
|
|
extern const struct ixgbe_info ixgbe_82598_info;
|
|
extern const struct ixgbe_info ixgbe_82599_info;
|
|
extern const struct ixgbe_info ixgbe_X540_info;
|
|
extern const struct ixgbe_info ixgbe_X550_info;
|
|
extern const struct ixgbe_info ixgbe_X550EM_x_info;
|
|
extern const struct ixgbe_info ixgbe_x550em_a_info;
|
|
#ifdef CONFIG_IXGBE_DCB
|
|
extern const struct dcbnl_rtnl_ops dcbnl_ops;
|
|
#endif
|
|
|
|
extern char ixgbe_driver_name[];
|
|
extern const char ixgbe_driver_version[];
|
|
#ifdef IXGBE_FCOE
|
|
extern char ixgbe_default_device_descr[];
|
|
#endif /* IXGBE_FCOE */
|
|
|
|
int ixgbe_open(struct net_device *netdev);
|
|
int ixgbe_close(struct net_device *netdev);
|
|
void ixgbe_up(struct ixgbe_adapter *adapter);
|
|
void ixgbe_down(struct ixgbe_adapter *adapter);
|
|
void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
|
|
void ixgbe_reset(struct ixgbe_adapter *adapter);
|
|
void ixgbe_set_ethtool_ops(struct net_device *netdev);
|
|
int ixgbe_setup_rx_resources(struct ixgbe_ring *);
|
|
int ixgbe_setup_tx_resources(struct ixgbe_ring *);
|
|
void ixgbe_free_rx_resources(struct ixgbe_ring *);
|
|
void ixgbe_free_tx_resources(struct ixgbe_ring *);
|
|
void ixgbe_configure_rx_ring(struct ixgbe_adapter *, struct ixgbe_ring *);
|
|
void ixgbe_configure_tx_ring(struct ixgbe_adapter *, struct ixgbe_ring *);
|
|
void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, struct ixgbe_ring *);
|
|
void ixgbe_update_stats(struct ixgbe_adapter *adapter);
|
|
int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
|
|
bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
|
|
u16 subdevice_id);
|
|
#ifdef CONFIG_PCI_IOV
|
|
void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter);
|
|
#endif
|
|
int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter,
|
|
const u8 *addr, u16 queue);
|
|
int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter,
|
|
const u8 *addr, u16 queue);
|
|
void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid);
|
|
void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
|
|
netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *, struct ixgbe_adapter *,
|
|
struct ixgbe_ring *);
|
|
void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *,
|
|
struct ixgbe_tx_buffer *);
|
|
void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16);
|
|
void ixgbe_write_eitr(struct ixgbe_q_vector *);
|
|
int ixgbe_poll(struct napi_struct *napi, int budget);
|
|
int ethtool_ioctl(struct ifreq *ifr);
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s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
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s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl);
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s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl);
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s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
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union ixgbe_atr_hash_dword input,
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union ixgbe_atr_hash_dword common,
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u8 queue);
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s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
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union ixgbe_atr_input *input_mask);
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s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
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union ixgbe_atr_input *input,
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u16 soft_id, u8 queue);
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s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
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union ixgbe_atr_input *input,
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u16 soft_id);
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void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
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union ixgbe_atr_input *mask);
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int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
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struct ixgbe_fdir_filter *input,
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u16 sw_idx);
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void ixgbe_set_rx_mode(struct net_device *netdev);
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#ifdef CONFIG_IXGBE_DCB
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void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter);
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#endif
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int ixgbe_setup_tc(struct net_device *dev, u8 tc);
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void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32);
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void ixgbe_do_reset(struct net_device *netdev);
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#ifdef CONFIG_IXGBE_HWMON
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void ixgbe_sysfs_exit(struct ixgbe_adapter *adapter);
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int ixgbe_sysfs_init(struct ixgbe_adapter *adapter);
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#endif /* CONFIG_IXGBE_HWMON */
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#ifdef IXGBE_FCOE
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void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
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int ixgbe_fso(struct ixgbe_ring *tx_ring, struct ixgbe_tx_buffer *first,
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u8 *hdr_len);
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int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
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union ixgbe_adv_rx_desc *rx_desc, struct sk_buff *skb);
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int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
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struct scatterlist *sgl, unsigned int sgc);
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int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid,
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|
struct scatterlist *sgl, unsigned int sgc);
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int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
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int ixgbe_setup_fcoe_ddp_resources(struct ixgbe_adapter *adapter);
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void ixgbe_free_fcoe_ddp_resources(struct ixgbe_adapter *adapter);
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int ixgbe_fcoe_enable(struct net_device *netdev);
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int ixgbe_fcoe_disable(struct net_device *netdev);
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|
#ifdef CONFIG_IXGBE_DCB
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u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter);
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u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up);
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#endif /* CONFIG_IXGBE_DCB */
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int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);
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|
int ixgbe_fcoe_get_hbainfo(struct net_device *netdev,
|
|
struct netdev_fcoe_hbainfo *info);
|
|
u8 ixgbe_fcoe_get_tc(struct ixgbe_adapter *adapter);
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|
#endif /* IXGBE_FCOE */
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|
#ifdef CONFIG_DEBUG_FS
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|
void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter);
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|
void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter);
|
|
void ixgbe_dbg_init(void);
|
|
void ixgbe_dbg_exit(void);
|
|
#else
|
|
static inline void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter) {}
|
|
static inline void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter) {}
|
|
static inline void ixgbe_dbg_init(void) {}
|
|
static inline void ixgbe_dbg_exit(void) {}
|
|
#endif /* CONFIG_DEBUG_FS */
|
|
static inline struct netdev_queue *txring_txq(const struct ixgbe_ring *ring)
|
|
{
|
|
return netdev_get_tx_queue(ring->netdev, ring->queue_index);
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|
}
|
|
|
|
void ixgbe_ptp_init(struct ixgbe_adapter *adapter);
|
|
void ixgbe_ptp_suspend(struct ixgbe_adapter *adapter);
|
|
void ixgbe_ptp_stop(struct ixgbe_adapter *adapter);
|
|
void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter);
|
|
void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter);
|
|
void ixgbe_ptp_rx_pktstamp(struct ixgbe_q_vector *, struct sk_buff *);
|
|
void ixgbe_ptp_rx_rgtstamp(struct ixgbe_q_vector *, struct sk_buff *skb);
|
|
static inline void ixgbe_ptp_rx_hwtstamp(struct ixgbe_ring *rx_ring,
|
|
union ixgbe_adv_rx_desc *rx_desc,
|
|
struct sk_buff *skb)
|
|
{
|
|
if (unlikely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_TSIP))) {
|
|
ixgbe_ptp_rx_pktstamp(rx_ring->q_vector, skb);
|
|
return;
|
|
}
|
|
|
|
if (unlikely(!ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS)))
|
|
return;
|
|
|
|
ixgbe_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
|
|
|
|
/* Update the last_rx_timestamp timer in order to enable watchdog check
|
|
* for error case of latched timestamp on a dropped packet.
|
|
*/
|
|
rx_ring->last_rx_timestamp = jiffies;
|
|
}
|
|
|
|
int ixgbe_ptp_set_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr);
|
|
int ixgbe_ptp_get_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr);
|
|
void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter);
|
|
void ixgbe_ptp_reset(struct ixgbe_adapter *adapter);
|
|
void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter);
|
|
#ifdef CONFIG_PCI_IOV
|
|
void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter);
|
|
#endif
|
|
|
|
netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
|
|
struct ixgbe_adapter *adapter,
|
|
struct ixgbe_ring *tx_ring);
|
|
u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter);
|
|
void ixgbe_store_reta(struct ixgbe_adapter *adapter);
|
|
#endif /* _IXGBE_H_ */
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