290 lines
7.3 KiB
C
290 lines
7.3 KiB
C
/*
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* Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
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* Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies.
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* All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <linux/export.h>
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#include "fw_qos.h"
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#include "fw.h"
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enum {
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/* allocate vpp opcode modifiers */
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MLX4_ALLOCATE_VPP_ALLOCATE = 0x0,
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MLX4_ALLOCATE_VPP_QUERY = 0x1
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};
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enum {
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/* set vport qos opcode modifiers */
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MLX4_SET_VPORT_QOS_SET = 0x0,
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MLX4_SET_VPORT_QOS_QUERY = 0x1
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};
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struct mlx4_set_port_prio2tc_context {
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u8 prio2tc[4];
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};
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struct mlx4_port_scheduler_tc_cfg_be {
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__be16 pg;
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__be16 bw_precentage;
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__be16 max_bw_units; /* 3-100Mbps, 4-1Gbps, other values - reserved */
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__be16 max_bw_value;
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};
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struct mlx4_set_port_scheduler_context {
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struct mlx4_port_scheduler_tc_cfg_be tc[MLX4_NUM_TC];
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};
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/* Granular Qos (per VF) section */
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struct mlx4_alloc_vpp_param {
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__be32 availible_vpp;
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__be32 vpp_p_up[MLX4_NUM_UP];
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};
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struct mlx4_prio_qos_param {
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__be32 bw_share;
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__be32 max_avg_bw;
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__be32 reserved;
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__be32 enable;
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__be32 reserved1[4];
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};
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struct mlx4_set_vport_context {
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__be32 reserved[8];
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struct mlx4_prio_qos_param qos_p_up[MLX4_NUM_UP];
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};
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int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc)
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{
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struct mlx4_cmd_mailbox *mailbox;
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struct mlx4_set_port_prio2tc_context *context;
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int err;
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u32 in_mod;
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int i;
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mailbox = mlx4_alloc_cmd_mailbox(dev);
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if (IS_ERR(mailbox))
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return PTR_ERR(mailbox);
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context = mailbox->buf;
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for (i = 0; i < MLX4_NUM_UP; i += 2)
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context->prio2tc[i >> 1] = prio2tc[i] << 4 | prio2tc[i + 1];
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in_mod = MLX4_SET_PORT_PRIO2TC << 8 | port;
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err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
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MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
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mlx4_free_cmd_mailbox(dev, mailbox);
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return err;
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}
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EXPORT_SYMBOL(mlx4_SET_PORT_PRIO2TC);
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int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw,
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u8 *pg, u16 *ratelimit)
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{
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struct mlx4_cmd_mailbox *mailbox;
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struct mlx4_set_port_scheduler_context *context;
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int err;
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u32 in_mod;
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int i;
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mailbox = mlx4_alloc_cmd_mailbox(dev);
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if (IS_ERR(mailbox))
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return PTR_ERR(mailbox);
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context = mailbox->buf;
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for (i = 0; i < MLX4_NUM_TC; i++) {
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struct mlx4_port_scheduler_tc_cfg_be *tc = &context->tc[i];
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u16 r;
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if (ratelimit && ratelimit[i]) {
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if (ratelimit[i] <= MLX4_MAX_100M_UNITS_VAL) {
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r = ratelimit[i];
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tc->max_bw_units =
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htons(MLX4_RATELIMIT_100M_UNITS);
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} else {
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r = ratelimit[i] / 10;
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tc->max_bw_units =
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htons(MLX4_RATELIMIT_1G_UNITS);
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}
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tc->max_bw_value = htons(r);
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} else {
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tc->max_bw_value = htons(MLX4_RATELIMIT_DEFAULT);
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tc->max_bw_units = htons(MLX4_RATELIMIT_1G_UNITS);
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}
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tc->pg = htons(pg[i]);
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tc->bw_precentage = htons(tc_tx_bw[i]);
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}
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in_mod = MLX4_SET_PORT_SCHEDULER << 8 | port;
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err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
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MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
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mlx4_free_cmd_mailbox(dev, mailbox);
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return err;
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}
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EXPORT_SYMBOL(mlx4_SET_PORT_SCHEDULER);
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int mlx4_ALLOCATE_VPP_get(struct mlx4_dev *dev, u8 port,
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u16 *availible_vpp, u8 *vpp_p_up)
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{
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int i;
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int err;
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struct mlx4_cmd_mailbox *mailbox;
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struct mlx4_alloc_vpp_param *out_param;
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mailbox = mlx4_alloc_cmd_mailbox(dev);
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if (IS_ERR(mailbox))
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return PTR_ERR(mailbox);
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out_param = mailbox->buf;
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err = mlx4_cmd_box(dev, 0, mailbox->dma, port,
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MLX4_ALLOCATE_VPP_QUERY,
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MLX4_CMD_ALLOCATE_VPP,
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MLX4_CMD_TIME_CLASS_A,
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MLX4_CMD_NATIVE);
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if (err)
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goto out;
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/* Total number of supported VPPs */
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*availible_vpp = (u16)be32_to_cpu(out_param->availible_vpp);
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for (i = 0; i < MLX4_NUM_UP; i++)
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vpp_p_up[i] = (u8)be32_to_cpu(out_param->vpp_p_up[i]);
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out:
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mlx4_free_cmd_mailbox(dev, mailbox);
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return err;
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}
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EXPORT_SYMBOL(mlx4_ALLOCATE_VPP_get);
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int mlx4_ALLOCATE_VPP_set(struct mlx4_dev *dev, u8 port, u8 *vpp_p_up)
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{
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int i;
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int err;
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struct mlx4_cmd_mailbox *mailbox;
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struct mlx4_alloc_vpp_param *in_param;
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mailbox = mlx4_alloc_cmd_mailbox(dev);
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if (IS_ERR(mailbox))
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return PTR_ERR(mailbox);
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in_param = mailbox->buf;
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for (i = 0; i < MLX4_NUM_UP; i++)
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in_param->vpp_p_up[i] = cpu_to_be32(vpp_p_up[i]);
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err = mlx4_cmd(dev, mailbox->dma, port,
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MLX4_ALLOCATE_VPP_ALLOCATE,
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MLX4_CMD_ALLOCATE_VPP,
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MLX4_CMD_TIME_CLASS_A,
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MLX4_CMD_NATIVE);
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mlx4_free_cmd_mailbox(dev, mailbox);
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return err;
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}
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EXPORT_SYMBOL(mlx4_ALLOCATE_VPP_set);
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int mlx4_SET_VPORT_QOS_get(struct mlx4_dev *dev, u8 port, u8 vport,
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struct mlx4_vport_qos_param *out_param)
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{
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int i;
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int err;
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struct mlx4_cmd_mailbox *mailbox;
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struct mlx4_set_vport_context *ctx;
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mailbox = mlx4_alloc_cmd_mailbox(dev);
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if (IS_ERR(mailbox))
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return PTR_ERR(mailbox);
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ctx = mailbox->buf;
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err = mlx4_cmd_box(dev, 0, mailbox->dma, (vport << 8) | port,
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MLX4_SET_VPORT_QOS_QUERY,
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MLX4_CMD_SET_VPORT_QOS,
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MLX4_CMD_TIME_CLASS_A,
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MLX4_CMD_NATIVE);
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if (err)
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goto out;
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for (i = 0; i < MLX4_NUM_UP; i++) {
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out_param[i].bw_share = be32_to_cpu(ctx->qos_p_up[i].bw_share);
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out_param[i].max_avg_bw =
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be32_to_cpu(ctx->qos_p_up[i].max_avg_bw);
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out_param[i].enable =
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!!(be32_to_cpu(ctx->qos_p_up[i].enable) & 31);
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}
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out:
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mlx4_free_cmd_mailbox(dev, mailbox);
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return err;
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}
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EXPORT_SYMBOL(mlx4_SET_VPORT_QOS_get);
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int mlx4_SET_VPORT_QOS_set(struct mlx4_dev *dev, u8 port, u8 vport,
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struct mlx4_vport_qos_param *in_param)
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{
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int i;
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int err;
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struct mlx4_cmd_mailbox *mailbox;
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struct mlx4_set_vport_context *ctx;
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mailbox = mlx4_alloc_cmd_mailbox(dev);
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if (IS_ERR(mailbox))
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return PTR_ERR(mailbox);
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ctx = mailbox->buf;
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for (i = 0; i < MLX4_NUM_UP; i++) {
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ctx->qos_p_up[i].bw_share = cpu_to_be32(in_param[i].bw_share);
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ctx->qos_p_up[i].max_avg_bw =
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cpu_to_be32(in_param[i].max_avg_bw);
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ctx->qos_p_up[i].enable =
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cpu_to_be32(in_param[i].enable << 31);
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}
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err = mlx4_cmd(dev, mailbox->dma, (vport << 8) | port,
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MLX4_SET_VPORT_QOS_SET,
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MLX4_CMD_SET_VPORT_QOS,
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MLX4_CMD_TIME_CLASS_A,
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MLX4_CMD_NATIVE);
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mlx4_free_cmd_mailbox(dev, mailbox);
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return err;
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}
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EXPORT_SYMBOL(mlx4_SET_VPORT_QOS_set);
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