234 lines
5.9 KiB
C
234 lines
5.9 KiB
C
/*
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* Copyright (C) 2016 Netronome Systems, Inc.
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*
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* This software is dual licensed under the GNU General License Version 2,
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* June 1991 as shown in the file COPYING in the top-level directory of this
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* source tree or the BSD 2-Clause License provided below. You have the
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* option to license this software under the complete terms of either license.
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*
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* The BSD 2-Clause License:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* 1. Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef __NFP_ASM_H__
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#define __NFP_ASM_H__ 1
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#include "nfp_bpf.h"
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#define REG_NONE 0
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#define RE_REG_NO_DST 0x020
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#define RE_REG_IMM 0x020
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#define RE_REG_IMM_encode(x) \
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(RE_REG_IMM | ((x) & 0x1f) | (((x) & 0x60) << 1))
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#define RE_REG_IMM_MAX 0x07fULL
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#define RE_REG_XFR 0x080
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#define UR_REG_XFR 0x180
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#define UR_REG_NN 0x280
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#define UR_REG_NO_DST 0x300
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#define UR_REG_IMM UR_REG_NO_DST
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#define UR_REG_IMM_encode(x) (UR_REG_IMM | (x))
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#define UR_REG_IMM_MAX 0x0ffULL
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#define OP_BR_BASE 0x0d800000020ULL
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#define OP_BR_BASE_MASK 0x0f8000c3ce0ULL
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#define OP_BR_MASK 0x0000000001fULL
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#define OP_BR_EV_PIP 0x00000000300ULL
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#define OP_BR_CSS 0x0000003c000ULL
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#define OP_BR_DEFBR 0x00000300000ULL
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#define OP_BR_ADDR_LO 0x007ffc00000ULL
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#define OP_BR_ADDR_HI 0x10000000000ULL
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#define nfp_is_br(_insn) \
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(((_insn) & OP_BR_BASE_MASK) == OP_BR_BASE)
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enum br_mask {
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BR_BEQ = 0x00,
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BR_BNE = 0x01,
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BR_BHS = 0x04,
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BR_BLO = 0x05,
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BR_BGE = 0x08,
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BR_UNC = 0x18,
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};
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enum br_ev_pip {
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BR_EV_PIP_UNCOND = 0,
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BR_EV_PIP_COND = 1,
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};
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enum br_ctx_signal_state {
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BR_CSS_NONE = 2,
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};
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#define OP_BBYTE_BASE 0x0c800000000ULL
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#define OP_BB_A_SRC 0x000000000ffULL
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#define OP_BB_BYTE 0x00000000300ULL
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#define OP_BB_B_SRC 0x0000003fc00ULL
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#define OP_BB_I8 0x00000040000ULL
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#define OP_BB_EQ 0x00000080000ULL
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#define OP_BB_DEFBR 0x00000300000ULL
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#define OP_BB_ADDR_LO 0x007ffc00000ULL
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#define OP_BB_ADDR_HI 0x10000000000ULL
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#define OP_BALU_BASE 0x0e800000000ULL
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#define OP_BA_A_SRC 0x000000003ffULL
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#define OP_BA_B_SRC 0x000000ffc00ULL
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#define OP_BA_DEFBR 0x00000300000ULL
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#define OP_BA_ADDR_HI 0x0007fc00000ULL
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#define OP_IMMED_A_SRC 0x000000003ffULL
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#define OP_IMMED_B_SRC 0x000000ffc00ULL
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#define OP_IMMED_IMM 0x0000ff00000ULL
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#define OP_IMMED_WIDTH 0x00060000000ULL
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#define OP_IMMED_INV 0x00080000000ULL
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#define OP_IMMED_SHIFT 0x00600000000ULL
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#define OP_IMMED_BASE 0x0f000000000ULL
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#define OP_IMMED_WR_AB 0x20000000000ULL
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enum immed_width {
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IMMED_WIDTH_ALL = 0,
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IMMED_WIDTH_BYTE = 1,
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IMMED_WIDTH_WORD = 2,
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};
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enum immed_shift {
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IMMED_SHIFT_0B = 0,
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IMMED_SHIFT_1B = 1,
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IMMED_SHIFT_2B = 2,
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};
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#define OP_SHF_BASE 0x08000000000ULL
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#define OP_SHF_A_SRC 0x000000000ffULL
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#define OP_SHF_SC 0x00000000300ULL
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#define OP_SHF_B_SRC 0x0000003fc00ULL
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#define OP_SHF_I8 0x00000040000ULL
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#define OP_SHF_SW 0x00000080000ULL
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#define OP_SHF_DST 0x0000ff00000ULL
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#define OP_SHF_SHIFT 0x001f0000000ULL
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#define OP_SHF_OP 0x00e00000000ULL
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#define OP_SHF_DST_AB 0x01000000000ULL
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#define OP_SHF_WR_AB 0x20000000000ULL
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enum shf_op {
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SHF_OP_NONE = 0,
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SHF_OP_AND = 2,
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SHF_OP_OR = 5,
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};
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enum shf_sc {
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SHF_SC_R_ROT = 0,
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SHF_SC_R_SHF = 1,
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SHF_SC_L_SHF = 2,
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SHF_SC_R_DSHF = 3,
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};
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#define OP_ALU_A_SRC 0x000000003ffULL
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#define OP_ALU_B_SRC 0x000000ffc00ULL
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#define OP_ALU_DST 0x0003ff00000ULL
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#define OP_ALU_SW 0x00040000000ULL
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#define OP_ALU_OP 0x00f80000000ULL
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#define OP_ALU_DST_AB 0x01000000000ULL
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#define OP_ALU_BASE 0x0a000000000ULL
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#define OP_ALU_WR_AB 0x20000000000ULL
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enum alu_op {
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ALU_OP_NONE = 0x00,
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ALU_OP_ADD = 0x01,
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ALU_OP_NEG = 0x04,
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ALU_OP_AND = 0x08,
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ALU_OP_SUB_C = 0x0d,
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ALU_OP_ADD_C = 0x11,
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ALU_OP_OR = 0x14,
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ALU_OP_SUB = 0x15,
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ALU_OP_XOR = 0x18,
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};
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enum alu_dst_ab {
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ALU_DST_A = 0,
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ALU_DST_B = 1,
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};
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#define OP_LDF_BASE 0x0c000000000ULL
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#define OP_LDF_A_SRC 0x000000000ffULL
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#define OP_LDF_SC 0x00000000300ULL
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#define OP_LDF_B_SRC 0x0000003fc00ULL
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#define OP_LDF_I8 0x00000040000ULL
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#define OP_LDF_SW 0x00000080000ULL
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#define OP_LDF_ZF 0x00000100000ULL
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#define OP_LDF_BMASK 0x0000f000000ULL
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#define OP_LDF_SHF 0x001f0000000ULL
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#define OP_LDF_WR_AB 0x20000000000ULL
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#define OP_CMD_A_SRC 0x000000000ffULL
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#define OP_CMD_CTX 0x00000000300ULL
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#define OP_CMD_B_SRC 0x0000003fc00ULL
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#define OP_CMD_TOKEN 0x000000c0000ULL
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#define OP_CMD_XFER 0x00001f00000ULL
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#define OP_CMD_CNT 0x0000e000000ULL
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#define OP_CMD_SIG 0x000f0000000ULL
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#define OP_CMD_TGT_CMD 0x07f00000000ULL
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#define OP_CMD_MODE 0x1c0000000000ULL
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struct cmd_tgt_act {
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u8 token;
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u8 tgt_cmd;
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};
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enum cmd_tgt_map {
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CMD_TGT_READ8,
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CMD_TGT_WRITE8,
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CMD_TGT_READ_LE,
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CMD_TGT_READ_SWAP_LE,
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__CMD_TGT_MAP_SIZE,
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};
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enum cmd_mode {
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CMD_MODE_40b_AB = 0,
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CMD_MODE_40b_BA = 1,
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CMD_MODE_32b = 4,
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};
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enum cmd_ctx_swap {
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CMD_CTX_SWAP = 0,
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CMD_CTX_NO_SWAP = 3,
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};
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#define OP_LCSR_BASE 0x0fc00000000ULL
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#define OP_LCSR_A_SRC 0x000000003ffULL
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#define OP_LCSR_B_SRC 0x000000ffc00ULL
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#define OP_LCSR_WRITE 0x00000200000ULL
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#define OP_LCSR_ADDR 0x001ffc00000ULL
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enum lcsr_wr_src {
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LCSR_WR_AREG,
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LCSR_WR_BREG,
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LCSR_WR_IMM,
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};
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#define OP_CARB_BASE 0x0e000000000ULL
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#define OP_CARB_OR 0x00000010000ULL
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#endif
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