370 lines
9.6 KiB
C
370 lines
9.6 KiB
C
/* QLogic qede NIC Driver
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* Copyright (c) 2015 QLogic Corporation
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*
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* This software is available under the terms of the GNU General Public License
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* (GPL) Version 2, available from the file COPYING in the main directory of
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* this source tree.
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*/
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#ifndef _QEDE_H_
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#define _QEDE_H_
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#include <linux/compiler.h>
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#include <linux/version.h>
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#include <linux/workqueue.h>
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#include <linux/netdevice.h>
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#include <linux/interrupt.h>
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#include <linux/bitmap.h>
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#include <linux/kernel.h>
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#include <linux/mutex.h>
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#include <linux/io.h>
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#include <linux/qed/common_hsi.h>
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#include <linux/qed/eth_common.h>
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#include <linux/qed/qed_if.h>
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#include <linux/qed/qed_chain.h>
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#include <linux/qed/qed_eth_if.h>
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#define QEDE_MAJOR_VERSION 8
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#define QEDE_MINOR_VERSION 10
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#define QEDE_REVISION_VERSION 9
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#define QEDE_ENGINEERING_VERSION 20
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#define DRV_MODULE_VERSION __stringify(QEDE_MAJOR_VERSION) "." \
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__stringify(QEDE_MINOR_VERSION) "." \
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__stringify(QEDE_REVISION_VERSION) "." \
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__stringify(QEDE_ENGINEERING_VERSION)
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#define DRV_MODULE_SYM qede
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struct qede_stats {
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u64 no_buff_discards;
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u64 packet_too_big_discard;
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u64 ttl0_discard;
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u64 rx_ucast_bytes;
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u64 rx_mcast_bytes;
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u64 rx_bcast_bytes;
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u64 rx_ucast_pkts;
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u64 rx_mcast_pkts;
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u64 rx_bcast_pkts;
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u64 mftag_filter_discards;
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u64 mac_filter_discards;
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u64 tx_ucast_bytes;
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u64 tx_mcast_bytes;
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u64 tx_bcast_bytes;
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u64 tx_ucast_pkts;
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u64 tx_mcast_pkts;
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u64 tx_bcast_pkts;
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u64 tx_err_drop_pkts;
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u64 coalesced_pkts;
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u64 coalesced_events;
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u64 coalesced_aborts_num;
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u64 non_coalesced_pkts;
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u64 coalesced_bytes;
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/* port */
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u64 rx_64_byte_packets;
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u64 rx_65_to_127_byte_packets;
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u64 rx_128_to_255_byte_packets;
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u64 rx_256_to_511_byte_packets;
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u64 rx_512_to_1023_byte_packets;
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u64 rx_1024_to_1518_byte_packets;
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u64 rx_1519_to_1522_byte_packets;
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u64 rx_1519_to_2047_byte_packets;
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u64 rx_2048_to_4095_byte_packets;
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u64 rx_4096_to_9216_byte_packets;
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u64 rx_9217_to_16383_byte_packets;
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u64 rx_crc_errors;
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u64 rx_mac_crtl_frames;
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u64 rx_pause_frames;
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u64 rx_pfc_frames;
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u64 rx_align_errors;
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u64 rx_carrier_errors;
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u64 rx_oversize_packets;
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u64 rx_jabbers;
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u64 rx_undersize_packets;
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u64 rx_fragments;
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u64 tx_64_byte_packets;
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u64 tx_65_to_127_byte_packets;
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u64 tx_128_to_255_byte_packets;
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u64 tx_256_to_511_byte_packets;
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u64 tx_512_to_1023_byte_packets;
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u64 tx_1024_to_1518_byte_packets;
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u64 tx_1519_to_2047_byte_packets;
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u64 tx_2048_to_4095_byte_packets;
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u64 tx_4096_to_9216_byte_packets;
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u64 tx_9217_to_16383_byte_packets;
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u64 tx_pause_frames;
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u64 tx_pfc_frames;
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u64 tx_lpi_entry_count;
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u64 tx_total_collisions;
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u64 brb_truncates;
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u64 brb_discards;
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u64 tx_mac_ctrl_frames;
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};
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struct qede_vlan {
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struct list_head list;
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u16 vid;
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bool configured;
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};
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struct qede_rdma_dev {
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struct qedr_dev *qedr_dev;
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struct list_head entry;
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struct list_head roce_event_list;
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struct workqueue_struct *roce_wq;
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};
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struct qede_dev {
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struct qed_dev *cdev;
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struct net_device *ndev;
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struct pci_dev *pdev;
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u32 dp_module;
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u8 dp_level;
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u32 flags;
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#define QEDE_FLAG_IS_VF BIT(0)
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#define IS_VF(edev) (!!((edev)->flags & QEDE_FLAG_IS_VF))
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const struct qed_eth_ops *ops;
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struct qed_dev_eth_info dev_info;
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#define QEDE_MAX_RSS_CNT(edev) ((edev)->dev_info.num_queues)
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#define QEDE_MAX_TSS_CNT(edev) ((edev)->dev_info.num_queues * \
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(edev)->dev_info.num_tc)
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struct qede_fastpath *fp_array;
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u8 req_num_tx;
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u8 fp_num_tx;
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u8 req_num_rx;
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u8 fp_num_rx;
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u16 req_queues;
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u16 num_queues;
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u8 num_tc;
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#define QEDE_QUEUE_CNT(edev) ((edev)->num_queues)
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#define QEDE_RSS_COUNT(edev) ((edev)->num_queues - (edev)->fp_num_tx)
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#define QEDE_TSS_COUNT(edev) (((edev)->num_queues - (edev)->fp_num_rx) * \
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(edev)->num_tc)
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#define QEDE_TX_IDX(edev, txqidx) ((edev)->fp_num_rx + (txqidx) % \
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QEDE_TSS_COUNT(edev))
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#define QEDE_TC_IDX(edev, txqidx) ((txqidx) / QEDE_TSS_COUNT(edev))
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#define QEDE_TX_QUEUE(edev, txqidx) \
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(&(edev)->fp_array[QEDE_TX_IDX((edev), (txqidx))].txqs[QEDE_TC_IDX(\
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(edev), (txqidx))])
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struct qed_int_info int_info;
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unsigned char primary_mac[ETH_ALEN];
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/* Smaller private varaiant of the RTNL lock */
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struct mutex qede_lock;
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u32 state; /* Protected by qede_lock */
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u16 rx_buf_size;
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u32 rx_copybreak;
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/* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
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#define ETH_OVERHEAD (ETH_HLEN + 8 + 8)
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/* Max supported alignment is 256 (8 shift)
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* minimal alignment shift 6 is optimal for 57xxx HW performance
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*/
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#define QEDE_RX_ALIGN_SHIFT max(6, min(8, L1_CACHE_SHIFT))
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/* We assume skb_build() uses sizeof(struct skb_shared_info) bytes
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* at the end of skb->data, to avoid wasting a full cache line.
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* This reduces memory use (skb->truesize).
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*/
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#define QEDE_FW_RX_ALIGN_END \
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max_t(u64, 1UL << QEDE_RX_ALIGN_SHIFT, \
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SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
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struct qede_stats stats;
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#define QEDE_RSS_INDIR_INITED BIT(0)
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#define QEDE_RSS_KEY_INITED BIT(1)
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#define QEDE_RSS_CAPS_INITED BIT(2)
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u32 rss_params_inited; /* bit-field to track initialized rss params */
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struct qed_update_vport_rss_params rss_params;
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u16 q_num_rx_buffers; /* Must be a power of two */
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u16 q_num_tx_buffers; /* Must be a power of two */
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bool gro_disable;
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struct list_head vlan_list;
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u16 configured_vlans;
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u16 non_configured_vlans;
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bool accept_any_vlan;
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struct delayed_work sp_task;
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unsigned long sp_flags;
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u16 vxlan_dst_port;
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u16 geneve_dst_port;
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struct qede_rdma_dev rdma_info;
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};
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enum QEDE_STATE {
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QEDE_STATE_CLOSED,
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QEDE_STATE_OPEN,
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};
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#define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
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#define MAX_NUM_TC 8
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#define MAX_NUM_PRI 8
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/* The driver supports the new build_skb() API:
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* RX ring buffer contains pointer to kmalloc() data only,
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* skb are built only after the frame was DMA-ed.
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*/
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struct sw_rx_data {
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struct page *data;
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dma_addr_t mapping;
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unsigned int page_offset;
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};
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enum qede_agg_state {
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QEDE_AGG_STATE_NONE = 0,
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QEDE_AGG_STATE_START = 1,
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QEDE_AGG_STATE_ERROR = 2
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};
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struct qede_agg_info {
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struct sw_rx_data replace_buf;
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dma_addr_t replace_buf_mapping;
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struct sw_rx_data start_buf;
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dma_addr_t start_buf_mapping;
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struct eth_fast_path_rx_tpa_start_cqe start_cqe;
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enum qede_agg_state agg_state;
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struct sk_buff *skb;
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int frag_id;
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u16 vlan_tag;
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};
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struct qede_rx_queue {
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__le16 *hw_cons_ptr;
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struct sw_rx_data *sw_rx_ring;
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u16 sw_rx_cons;
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u16 sw_rx_prod;
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struct qed_chain rx_bd_ring;
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struct qed_chain rx_comp_ring;
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void __iomem *hw_rxq_prod_addr;
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/* GRO */
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struct qede_agg_info tpa_info[ETH_TPA_MAX_AGGS_NUM];
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int rx_buf_size;
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unsigned int rx_buf_seg_size;
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u16 num_rx_buffers;
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u16 rxq_id;
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u64 rcv_pkts;
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u64 rx_hw_errors;
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u64 rx_alloc_errors;
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u64 rx_ip_frags;
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};
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union db_prod {
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struct eth_db_data data;
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u32 raw;
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};
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struct sw_tx_bd {
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struct sk_buff *skb;
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u8 flags;
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/* Set on the first BD descriptor when there is a split BD */
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#define QEDE_TSO_SPLIT_BD BIT(0)
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};
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struct qede_tx_queue {
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int index; /* Queue index */
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__le16 *hw_cons_ptr;
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struct sw_tx_bd *sw_tx_ring;
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u16 sw_tx_cons;
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u16 sw_tx_prod;
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struct qed_chain tx_pbl;
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void __iomem *doorbell_addr;
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union db_prod tx_db;
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u16 num_tx_buffers;
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u64 xmit_pkts;
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u64 stopped_cnt;
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bool is_legacy;
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};
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#define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr.hi), \
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le32_to_cpu((bd)->addr.lo))
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#define BD_SET_UNMAP_ADDR_LEN(bd, maddr, len) \
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do { \
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(bd)->addr.hi = cpu_to_le32(upper_32_bits(maddr)); \
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(bd)->addr.lo = cpu_to_le32(lower_32_bits(maddr)); \
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(bd)->nbytes = cpu_to_le16(len); \
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} while (0)
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#define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
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struct qede_fastpath {
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struct qede_dev *edev;
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#define QEDE_FASTPATH_TX BIT(0)
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#define QEDE_FASTPATH_RX BIT(1)
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#define QEDE_FASTPATH_COMBINED (QEDE_FASTPATH_TX | QEDE_FASTPATH_RX)
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u8 type;
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u8 id;
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struct napi_struct napi;
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struct qed_sb_info *sb_info;
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struct qede_rx_queue *rxq;
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struct qede_tx_queue *txqs;
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#define VEC_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8)
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char name[VEC_NAME_SIZE];
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};
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/* Debug print definitions */
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#define DP_NAME(edev) ((edev)->ndev->name)
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#define XMIT_PLAIN 0
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#define XMIT_L4_CSUM BIT(0)
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#define XMIT_LSO BIT(1)
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#define XMIT_ENC BIT(2)
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#define QEDE_CSUM_ERROR BIT(0)
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#define QEDE_CSUM_UNNECESSARY BIT(1)
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#define QEDE_TUNN_CSUM_UNNECESSARY BIT(2)
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#define QEDE_SP_RX_MODE 1
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#define QEDE_SP_VXLAN_PORT_CONFIG 2
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#define QEDE_SP_GENEVE_PORT_CONFIG 3
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union qede_reload_args {
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u16 mtu;
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};
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#ifdef CONFIG_DCB
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void qede_set_dcbnl_ops(struct net_device *ndev);
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#endif
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void qede_config_debug(uint debug, u32 *p_dp_module, u8 *p_dp_level);
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void qede_set_ethtool_ops(struct net_device *netdev);
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void qede_reload(struct qede_dev *edev,
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void (*func)(struct qede_dev *edev,
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union qede_reload_args *args),
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union qede_reload_args *args);
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int qede_change_mtu(struct net_device *dev, int new_mtu);
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void qede_fill_by_demand_stats(struct qede_dev *edev);
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bool qede_has_rx_work(struct qede_rx_queue *rxq);
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int qede_txq_has_work(struct qede_tx_queue *txq);
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void qede_recycle_rx_bd_ring(struct qede_rx_queue *rxq, struct qede_dev *edev,
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u8 count);
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void qede_update_rx_prod(struct qede_dev *edev, struct qede_rx_queue *rxq);
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#define RX_RING_SIZE_POW 13
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#define RX_RING_SIZE ((u16)BIT(RX_RING_SIZE_POW))
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#define NUM_RX_BDS_MAX (RX_RING_SIZE - 1)
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#define NUM_RX_BDS_MIN 128
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#define NUM_RX_BDS_DEF ((u16)BIT(10) - 1)
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#define TX_RING_SIZE_POW 13
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#define TX_RING_SIZE ((u16)BIT(TX_RING_SIZE_POW))
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#define NUM_TX_BDS_MAX (TX_RING_SIZE - 1)
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#define NUM_TX_BDS_MIN 128
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#define NUM_TX_BDS_DEF NUM_TX_BDS_MAX
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#define QEDE_MIN_PKT_LEN 64
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#define QEDE_RX_HDR_SIZE 256
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#define for_each_queue(i) for (i = 0; i < edev->num_queues; i++)
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#endif /* _QEDE_H_ */
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