255 lines
6.2 KiB
C
255 lines
6.2 KiB
C
/* 10G controller driver for Samsung SoCs
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*
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* Copyright (C) 2013 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Author: Siva Reddy Kallam <siva.kallam@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/io.h>
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#include <linux/mii.h>
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#include <linux/netdevice.h>
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#include <linux/platform_device.h>
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#include <linux/phy.h>
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#include <linux/slab.h>
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#include <linux/sxgbe_platform.h>
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#include "sxgbe_common.h"
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#include "sxgbe_reg.h"
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#define SXGBE_SMA_WRITE_CMD 0x01 /* write command */
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#define SXGBE_SMA_PREAD_CMD 0x02 /* post read increament address */
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#define SXGBE_SMA_READ_CMD 0x03 /* read command */
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#define SXGBE_SMA_SKIP_ADDRFRM 0x00040000 /* skip the address frame */
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#define SXGBE_MII_BUSY 0x00400000 /* mii busy */
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static int sxgbe_mdio_busy_wait(void __iomem *ioaddr, unsigned int mii_data)
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{
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unsigned long fin_time = jiffies + 3 * HZ; /* 3 seconds */
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while (!time_after(jiffies, fin_time)) {
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if (!(readl(ioaddr + mii_data) & SXGBE_MII_BUSY))
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return 0;
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cpu_relax();
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}
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return -EBUSY;
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}
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static void sxgbe_mdio_ctrl_data(struct sxgbe_priv_data *sp, u32 cmd,
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u16 phydata)
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{
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u32 reg = phydata;
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reg |= (cmd << 16) | SXGBE_SMA_SKIP_ADDRFRM |
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((sp->clk_csr & 0x7) << 19) | SXGBE_MII_BUSY;
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writel(reg, sp->ioaddr + sp->hw->mii.data);
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}
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static void sxgbe_mdio_c45(struct sxgbe_priv_data *sp, u32 cmd, int phyaddr,
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int phyreg, u16 phydata)
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{
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u32 reg;
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/* set mdio address register */
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reg = ((phyreg >> 16) & 0x1f) << 21;
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reg |= (phyaddr << 16) | (phyreg & 0xffff);
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writel(reg, sp->ioaddr + sp->hw->mii.addr);
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sxgbe_mdio_ctrl_data(sp, cmd, phydata);
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}
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static void sxgbe_mdio_c22(struct sxgbe_priv_data *sp, u32 cmd, int phyaddr,
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int phyreg, u16 phydata)
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{
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u32 reg;
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writel(1 << phyaddr, sp->ioaddr + SXGBE_MDIO_CLAUSE22_PORT_REG);
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/* set mdio address register */
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reg = (phyaddr << 16) | (phyreg & 0x1f);
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writel(reg, sp->ioaddr + sp->hw->mii.addr);
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sxgbe_mdio_ctrl_data(sp, cmd, phydata);
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}
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static int sxgbe_mdio_access(struct sxgbe_priv_data *sp, u32 cmd, int phyaddr,
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int phyreg, u16 phydata)
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{
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const struct mii_regs *mii = &sp->hw->mii;
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int rc;
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rc = sxgbe_mdio_busy_wait(sp->ioaddr, mii->data);
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if (rc < 0)
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return rc;
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if (phyreg & MII_ADDR_C45) {
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sxgbe_mdio_c45(sp, cmd, phyaddr, phyreg, phydata);
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} else {
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/* Ports 0-3 only support C22. */
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if (phyaddr >= 4)
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return -ENODEV;
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sxgbe_mdio_c22(sp, cmd, phyaddr, phyreg, phydata);
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}
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return sxgbe_mdio_busy_wait(sp->ioaddr, mii->data);
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}
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/**
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* sxgbe_mdio_read
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* @bus: points to the mii_bus structure
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* @phyaddr: address of phy port
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* @phyreg: address of register with in phy register
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* Description: this function used for C45 and C22 MDIO Read
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*/
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static int sxgbe_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)
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{
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struct net_device *ndev = bus->priv;
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struct sxgbe_priv_data *priv = netdev_priv(ndev);
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int rc;
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rc = sxgbe_mdio_access(priv, SXGBE_SMA_READ_CMD, phyaddr, phyreg, 0);
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if (rc < 0)
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return rc;
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return readl(priv->ioaddr + priv->hw->mii.data) & 0xffff;
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}
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/**
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* sxgbe_mdio_write
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* @bus: points to the mii_bus structure
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* @phyaddr: address of phy port
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* @phyreg: address of phy registers
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* @phydata: data to be written into phy register
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* Description: this function is used for C45 and C22 MDIO write
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*/
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static int sxgbe_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg,
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u16 phydata)
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{
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struct net_device *ndev = bus->priv;
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struct sxgbe_priv_data *priv = netdev_priv(ndev);
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return sxgbe_mdio_access(priv, SXGBE_SMA_WRITE_CMD, phyaddr, phyreg,
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phydata);
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}
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int sxgbe_mdio_register(struct net_device *ndev)
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{
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struct mii_bus *mdio_bus;
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struct sxgbe_priv_data *priv = netdev_priv(ndev);
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struct sxgbe_mdio_bus_data *mdio_data = priv->plat->mdio_bus_data;
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int err, phy_addr;
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int *irqlist;
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bool phy_found = false;
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bool act;
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/* allocate the new mdio bus */
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mdio_bus = mdiobus_alloc();
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if (!mdio_bus) {
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netdev_err(ndev, "%s: mii bus allocation failed\n", __func__);
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return -ENOMEM;
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}
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if (mdio_data->irqs)
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irqlist = mdio_data->irqs;
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else
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irqlist = priv->mii_irq;
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/* assign mii bus fields */
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mdio_bus->name = "sxgbe";
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mdio_bus->read = &sxgbe_mdio_read;
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mdio_bus->write = &sxgbe_mdio_write;
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snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "%s-%x",
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mdio_bus->name, priv->plat->bus_id);
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mdio_bus->priv = ndev;
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mdio_bus->phy_mask = mdio_data->phy_mask;
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mdio_bus->parent = priv->device;
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/* register with kernel subsystem */
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err = mdiobus_register(mdio_bus);
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if (err != 0) {
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netdev_err(ndev, "mdiobus register failed\n");
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goto mdiobus_err;
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}
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for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
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struct phy_device *phy = mdiobus_get_phy(mdio_bus, phy_addr);
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if (phy) {
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char irq_num[4];
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char *irq_str;
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/* If an IRQ was provided to be assigned after
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* the bus probe, do it here.
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*/
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if ((mdio_data->irqs == NULL) &&
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(mdio_data->probed_phy_irq > 0)) {
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irqlist[phy_addr] = mdio_data->probed_phy_irq;
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phy->irq = mdio_data->probed_phy_irq;
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}
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/* If we're going to bind the MAC to this PHY bus,
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* and no PHY number was provided to the MAC,
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* use the one probed here.
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*/
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if (priv->plat->phy_addr == -1)
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priv->plat->phy_addr = phy_addr;
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act = (priv->plat->phy_addr == phy_addr);
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switch (phy->irq) {
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case PHY_POLL:
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irq_str = "POLL";
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break;
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case PHY_IGNORE_INTERRUPT:
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irq_str = "IGNORE";
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break;
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default:
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sprintf(irq_num, "%d", phy->irq);
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irq_str = irq_num;
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break;
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}
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netdev_info(ndev, "PHY ID %08x at %d IRQ %s (%s)%s\n",
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phy->phy_id, phy_addr, irq_str,
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phydev_name(phy), act ? " active" : "");
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phy_found = true;
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}
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}
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if (!phy_found) {
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netdev_err(ndev, "PHY not found\n");
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goto phyfound_err;
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}
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priv->mii = mdio_bus;
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return 0;
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phyfound_err:
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err = -ENODEV;
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mdiobus_unregister(mdio_bus);
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mdiobus_err:
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mdiobus_free(mdio_bus);
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return err;
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}
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int sxgbe_mdio_unregister(struct net_device *ndev)
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{
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struct sxgbe_priv_data *priv = netdev_priv(ndev);
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if (!priv->mii)
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return 0;
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mdiobus_unregister(priv->mii);
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priv->mii->priv = NULL;
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mdiobus_free(priv->mii);
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priv->mii = NULL;
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return 0;
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}
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