255 lines
6.8 KiB
C
255 lines
6.8 KiB
C
/* 10G controller driver for Samsung SoCs
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*
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* Copyright (C) 2013 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Author: Siva Reddy Kallam <siva.kallam@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/io.h>
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#include <linux/errno.h>
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#include <linux/export.h>
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#include <linux/jiffies.h>
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#include "sxgbe_mtl.h"
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#include "sxgbe_reg.h"
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static void sxgbe_mtl_init(void __iomem *ioaddr, unsigned int etsalg,
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unsigned int raa)
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{
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u32 reg_val;
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reg_val = readl(ioaddr + SXGBE_MTL_OP_MODE_REG);
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reg_val &= ETS_RST;
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/* ETS Algorith */
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switch (etsalg & SXGBE_MTL_OPMODE_ESTMASK) {
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case ETS_WRR:
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reg_val &= ETS_WRR;
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break;
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case ETS_WFQ:
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reg_val |= ETS_WFQ;
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break;
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case ETS_DWRR:
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reg_val |= ETS_DWRR;
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break;
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}
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writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG);
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switch (raa & SXGBE_MTL_OPMODE_RAAMASK) {
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case RAA_SP:
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reg_val &= RAA_SP;
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break;
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case RAA_WSP:
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reg_val |= RAA_WSP;
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break;
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}
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writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG);
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}
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/* For Dynamic DMA channel mapping for Rx queue */
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static void sxgbe_mtl_dma_dm_rxqueue(void __iomem *ioaddr)
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{
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writel(RX_QUEUE_DYNAMIC, ioaddr + SXGBE_MTL_RXQ_DMAMAP0_REG);
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writel(RX_QUEUE_DYNAMIC, ioaddr + SXGBE_MTL_RXQ_DMAMAP1_REG);
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writel(RX_QUEUE_DYNAMIC, ioaddr + SXGBE_MTL_RXQ_DMAMAP2_REG);
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}
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static void sxgbe_mtl_set_txfifosize(void __iomem *ioaddr, int queue_num,
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int queue_fifo)
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{
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u32 fifo_bits, reg_val;
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/* 0 means 256 bytes */
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fifo_bits = (queue_fifo / SXGBE_MTL_TX_FIFO_DIV) - 1;
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reg_val = readl(ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num));
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reg_val |= (fifo_bits << SXGBE_MTL_FIFO_LSHIFT);
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writel(reg_val, ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num));
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}
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static void sxgbe_mtl_set_rxfifosize(void __iomem *ioaddr, int queue_num,
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int queue_fifo)
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{
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u32 fifo_bits, reg_val;
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/* 0 means 256 bytes */
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fifo_bits = (queue_fifo / SXGBE_MTL_RX_FIFO_DIV)-1;
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reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));
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reg_val |= (fifo_bits << SXGBE_MTL_FIFO_LSHIFT);
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writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));
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}
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static void sxgbe_mtl_enable_txqueue(void __iomem *ioaddr, int queue_num)
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{
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u32 reg_val;
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reg_val = readl(ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num));
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reg_val |= SXGBE_MTL_ENABLE_QUEUE;
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writel(reg_val, ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num));
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}
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static void sxgbe_mtl_disable_txqueue(void __iomem *ioaddr, int queue_num)
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{
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u32 reg_val;
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reg_val = readl(ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num));
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reg_val &= ~SXGBE_MTL_ENABLE_QUEUE;
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writel(reg_val, ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num));
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}
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static void sxgbe_mtl_fc_active(void __iomem *ioaddr, int queue_num,
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int threshold)
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{
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u32 reg_val;
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reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));
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reg_val &= ~(SXGBE_MTL_FCMASK << RX_FC_ACTIVE);
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reg_val |= (threshold << RX_FC_ACTIVE);
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writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));
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}
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static void sxgbe_mtl_fc_enable(void __iomem *ioaddr, int queue_num)
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{
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u32 reg_val;
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reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));
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reg_val |= SXGBE_MTL_ENABLE_FC;
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writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));
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}
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static void sxgbe_mtl_fc_deactive(void __iomem *ioaddr, int queue_num,
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int threshold)
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{
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u32 reg_val;
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reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));
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reg_val &= ~(SXGBE_MTL_FCMASK << RX_FC_DEACTIVE);
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reg_val |= (threshold << RX_FC_DEACTIVE);
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writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));
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}
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static void sxgbe_mtl_fep_enable(void __iomem *ioaddr, int queue_num)
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{
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u32 reg_val;
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reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));
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reg_val |= SXGBE_MTL_RXQ_OP_FEP;
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writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));
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}
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static void sxgbe_mtl_fep_disable(void __iomem *ioaddr, int queue_num)
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{
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u32 reg_val;
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reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));
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reg_val &= ~(SXGBE_MTL_RXQ_OP_FEP);
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writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));
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}
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static void sxgbe_mtl_fup_enable(void __iomem *ioaddr, int queue_num)
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{
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u32 reg_val;
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reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));
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reg_val |= SXGBE_MTL_RXQ_OP_FUP;
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writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));
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}
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static void sxgbe_mtl_fup_disable(void __iomem *ioaddr, int queue_num)
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{
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u32 reg_val;
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reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));
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reg_val &= ~(SXGBE_MTL_RXQ_OP_FUP);
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writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));
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}
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static void sxgbe_set_tx_mtl_mode(void __iomem *ioaddr, int queue_num,
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int tx_mode)
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{
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u32 reg_val;
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reg_val = readl(ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num));
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/* TX specific MTL mode settings */
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if (tx_mode == SXGBE_MTL_SFMODE) {
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reg_val |= SXGBE_MTL_SFMODE;
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} else {
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/* set the TTC values */
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if (tx_mode <= 64)
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reg_val |= MTL_CONTROL_TTC_64;
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else if (tx_mode <= 96)
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reg_val |= MTL_CONTROL_TTC_96;
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else if (tx_mode <= 128)
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reg_val |= MTL_CONTROL_TTC_128;
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else if (tx_mode <= 192)
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reg_val |= MTL_CONTROL_TTC_192;
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else if (tx_mode <= 256)
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reg_val |= MTL_CONTROL_TTC_256;
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else if (tx_mode <= 384)
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reg_val |= MTL_CONTROL_TTC_384;
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else
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reg_val |= MTL_CONTROL_TTC_512;
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}
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/* write into TXQ operation register */
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writel(reg_val, ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num));
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}
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static void sxgbe_set_rx_mtl_mode(void __iomem *ioaddr, int queue_num,
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int rx_mode)
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{
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u32 reg_val;
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reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));
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/* RX specific MTL mode settings */
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if (rx_mode == SXGBE_RX_MTL_SFMODE) {
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reg_val |= SXGBE_RX_MTL_SFMODE;
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} else {
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if (rx_mode <= 64)
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reg_val |= MTL_CONTROL_RTC_64;
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else if (rx_mode <= 96)
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reg_val |= MTL_CONTROL_RTC_96;
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else if (rx_mode <= 128)
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reg_val |= MTL_CONTROL_RTC_128;
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}
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/* write into RXQ operation register */
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writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));
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}
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static const struct sxgbe_mtl_ops mtl_ops = {
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.mtl_set_txfifosize = sxgbe_mtl_set_txfifosize,
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.mtl_set_rxfifosize = sxgbe_mtl_set_rxfifosize,
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.mtl_enable_txqueue = sxgbe_mtl_enable_txqueue,
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.mtl_disable_txqueue = sxgbe_mtl_disable_txqueue,
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.mtl_dynamic_dma_rxqueue = sxgbe_mtl_dma_dm_rxqueue,
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.set_tx_mtl_mode = sxgbe_set_tx_mtl_mode,
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.set_rx_mtl_mode = sxgbe_set_rx_mtl_mode,
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.mtl_init = sxgbe_mtl_init,
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.mtl_fc_active = sxgbe_mtl_fc_active,
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.mtl_fc_deactive = sxgbe_mtl_fc_deactive,
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.mtl_fc_enable = sxgbe_mtl_fc_enable,
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.mtl_fep_enable = sxgbe_mtl_fep_enable,
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.mtl_fep_disable = sxgbe_mtl_fep_disable,
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.mtl_fup_enable = sxgbe_mtl_fup_enable,
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.mtl_fup_disable = sxgbe_mtl_fup_disable
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};
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const struct sxgbe_mtl_ops *sxgbe_get_mtl_ops(void)
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{
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return &mtl_ops;
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}
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