600 lines
17 KiB
C
600 lines
17 KiB
C
/*
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* Copyright (c) 2008-2011 Atheros Communications Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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/**
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* DOC: Programming Atheros 802.11n analog front end radios
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*
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* AR5416 MAC based PCI devices and AR518 MAC based PCI-Express
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* devices have either an external AR2133 analog front end radio for single
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* band 2.4 GHz communication or an AR5133 analog front end radio for dual
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* band 2.4 GHz / 5 GHz communication.
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*
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* All devices after the AR5416 and AR5418 family starting with the AR9280
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* have their analog front radios, MAC/BB and host PCIe/USB interface embedded
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* into a single-chip and require less programming.
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*
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* The following single-chips exist with a respective embedded radio:
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*
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* AR9280 - 11n dual-band 2x2 MIMO for PCIe
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* AR9281 - 11n single-band 1x2 MIMO for PCIe
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* AR9285 - 11n single-band 1x1 for PCIe
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* AR9287 - 11n single-band 2x2 MIMO for PCIe
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*
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* AR9220 - 11n dual-band 2x2 MIMO for PCI
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* AR9223 - 11n single-band 2x2 MIMO for PCI
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*
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* AR9287 - 11n single-band 1x1 MIMO for USB
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*/
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#include "hw.h"
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#include "ar9002_phy.h"
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/**
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* ar9002_hw_set_channel - set channel on single-chip device
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* @ah: atheros hardware structure
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* @chan:
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*
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* This is the function to change channel on single-chip devices, that is
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* all devices after ar9280.
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*
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* This function takes the channel value in MHz and sets
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* hardware channel value. Assumes writes have been enabled to analog bus.
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*
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* Actual Expression,
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*
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* For 2GHz channel,
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* Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
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* (freq_ref = 40MHz)
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*
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* For 5GHz channel,
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* Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
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* (freq_ref = 40MHz/(24>>amodeRefSel))
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*/
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static int ar9002_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
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{
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u16 bMode, fracMode, aModeRefSel = 0;
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u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0;
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struct chan_centers centers;
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u32 refDivA = 24;
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ath9k_hw_get_channel_centers(ah, chan, ¢ers);
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freq = centers.synth_center;
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reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL);
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reg32 &= 0xc0000000;
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if (freq < 4800) { /* 2 GHz, fractional mode */
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u32 txctl;
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int regWrites = 0;
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bMode = 1;
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fracMode = 1;
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aModeRefSel = 0;
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channelSel = CHANSEL_2G(freq);
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if (AR_SREV_9287_11_OR_LATER(ah)) {
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if (freq == 2484) {
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/* Enable channel spreading for channel 14 */
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REG_WRITE_ARRAY(&ah->iniCckfirJapan2484,
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1, regWrites);
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} else {
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REG_WRITE_ARRAY(&ah->iniCckfirNormal,
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1, regWrites);
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}
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} else {
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txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
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if (freq == 2484) {
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/* Enable channel spreading for channel 14 */
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REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
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txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
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} else {
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REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
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txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
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}
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}
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} else {
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bMode = 0;
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fracMode = 0;
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switch (ah->eep_ops->get_eeprom(ah, EEP_FRAC_N_5G)) {
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case 0:
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if (IS_CHAN_HALF_RATE(chan) || IS_CHAN_QUARTER_RATE(chan))
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aModeRefSel = 0;
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else if ((freq % 20) == 0)
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aModeRefSel = 3;
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else if ((freq % 10) == 0)
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aModeRefSel = 2;
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if (aModeRefSel)
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break;
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case 1:
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default:
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aModeRefSel = 0;
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/*
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* Enable 2G (fractional) mode for channels
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* which are 5MHz spaced.
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*/
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fracMode = 1;
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refDivA = 1;
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channelSel = CHANSEL_5G(freq);
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/* RefDivA setting */
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ath9k_hw_analog_shift_rmw(ah, AR_AN_SYNTH9,
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AR_AN_SYNTH9_REFDIVA,
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AR_AN_SYNTH9_REFDIVA_S, refDivA);
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}
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if (!fracMode) {
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ndiv = (freq * (refDivA >> aModeRefSel)) / 60;
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channelSel = ndiv & 0x1ff;
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channelFrac = (ndiv & 0xfffffe00) * 2;
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channelSel = (channelSel << 17) | channelFrac;
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}
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}
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reg32 = reg32 |
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(bMode << 29) |
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(fracMode << 28) | (aModeRefSel << 26) | (channelSel);
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REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
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ah->curchan = chan;
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return 0;
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}
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/**
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* ar9002_hw_spur_mitigate - convert baseband spur frequency
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* @ah: atheros hardware structure
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* @chan:
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*
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* For single-chip solutions. Converts to baseband spur frequency given the
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* input channel frequency and compute register settings below.
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*/
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static void ar9002_hw_spur_mitigate(struct ath_hw *ah,
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struct ath9k_channel *chan)
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{
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int bb_spur = AR_NO_SPUR;
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int freq;
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int bin;
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int bb_spur_off, spur_subchannel_sd;
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int spur_freq_sd;
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int spur_delta_phase;
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int denominator;
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int tmp, newVal;
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int i;
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struct chan_centers centers;
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int cur_bb_spur;
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bool is2GHz = IS_CHAN_2GHZ(chan);
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ath9k_hw_get_channel_centers(ah, chan, ¢ers);
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freq = centers.synth_center;
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for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
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cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
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if (AR_NO_SPUR == cur_bb_spur)
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break;
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if (is2GHz)
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cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
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else
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cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
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cur_bb_spur = cur_bb_spur - freq;
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if (IS_CHAN_HT40(chan)) {
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if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
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(cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
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bb_spur = cur_bb_spur;
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break;
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}
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} else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
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(cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
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bb_spur = cur_bb_spur;
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break;
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}
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}
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if (AR_NO_SPUR == bb_spur) {
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REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
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AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
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return;
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} else {
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REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
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AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
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}
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bin = bb_spur * 320;
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tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
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ENABLE_REGWRITE_BUFFER(ah);
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newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
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AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
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AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
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AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
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REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
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newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
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AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
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AR_PHY_SPUR_REG_MASK_RATE_SELECT |
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AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
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SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
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REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
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if (IS_CHAN_HT40(chan)) {
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if (bb_spur < 0) {
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spur_subchannel_sd = 1;
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bb_spur_off = bb_spur + 10;
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} else {
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spur_subchannel_sd = 0;
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bb_spur_off = bb_spur - 10;
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}
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} else {
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spur_subchannel_sd = 0;
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bb_spur_off = bb_spur;
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}
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if (IS_CHAN_HT40(chan))
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spur_delta_phase =
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((bb_spur * 262144) /
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10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
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else
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spur_delta_phase =
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((bb_spur * 524288) /
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10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
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denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
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spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
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newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
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SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
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SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
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REG_WRITE(ah, AR_PHY_TIMING11, newVal);
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newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
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REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
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ar5008_hw_cmn_spur_mitigate(ah, chan, bin);
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REGWRITE_BUFFER_FLUSH(ah);
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}
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static void ar9002_olc_init(struct ath_hw *ah)
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{
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u32 i;
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if (!OLC_FOR_AR9280_20_LATER)
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return;
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if (OLC_FOR_AR9287_10_LATER) {
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REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
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AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
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ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
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AR9287_AN_TXPC0_TXPCMODE,
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AR9287_AN_TXPC0_TXPCMODE_S,
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AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
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udelay(100);
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} else {
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for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
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ah->originalGain[i] =
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MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
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AR_PHY_TX_GAIN);
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ah->PDADCdelta = 0;
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}
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}
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static u32 ar9002_hw_compute_pll_control(struct ath_hw *ah,
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struct ath9k_channel *chan)
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{
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int ref_div = 5;
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int pll_div = 0x2c;
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u32 pll;
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if (chan && IS_CHAN_5GHZ(chan) && !IS_CHAN_A_FAST_CLOCK(ah, chan)) {
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if (AR_SREV_9280_20(ah)) {
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ref_div = 10;
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pll_div = 0x50;
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} else {
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pll_div = 0x28;
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}
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}
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pll = SM(ref_div, AR_RTC_9160_PLL_REFDIV);
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pll |= SM(pll_div, AR_RTC_9160_PLL_DIV);
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if (chan && IS_CHAN_HALF_RATE(chan))
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pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
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else if (chan && IS_CHAN_QUARTER_RATE(chan))
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pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
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return pll;
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}
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static void ar9002_hw_do_getnf(struct ath_hw *ah,
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int16_t nfarray[NUM_NF_READINGS])
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{
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int16_t nf;
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nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
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nfarray[0] = sign_extend32(nf, 8);
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nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR);
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if (IS_CHAN_HT40(ah->curchan))
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nfarray[3] = sign_extend32(nf, 8);
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if (!(ah->rxchainmask & BIT(1)))
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return;
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nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR9280_PHY_CH1_MINCCA_PWR);
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nfarray[1] = sign_extend32(nf, 8);
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nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR9280_PHY_CH1_EXT_MINCCA_PWR);
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if (IS_CHAN_HT40(ah->curchan))
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nfarray[4] = sign_extend32(nf, 8);
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}
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static void ar9002_hw_set_nf_limits(struct ath_hw *ah)
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{
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if (AR_SREV_9285(ah)) {
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ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9285_2GHZ;
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ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9285_2GHZ;
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ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9285_2GHZ;
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} else if (AR_SREV_9287(ah)) {
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ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9287_2GHZ;
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ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9287_2GHZ;
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ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9287_2GHZ;
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} else if (AR_SREV_9271(ah)) {
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ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9271_2GHZ;
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ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9271_2GHZ;
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ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9271_2GHZ;
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} else {
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ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_2GHZ;
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ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_2GHZ;
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ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9280_2GHZ;
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ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_5GHZ;
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ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_5GHZ;
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ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9280_5GHZ;
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}
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}
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static void ar9002_hw_antdiv_comb_conf_get(struct ath_hw *ah,
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struct ath_hw_antcomb_conf *antconf)
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{
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u32 regval;
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regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
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antconf->main_lna_conf = (regval & AR_PHY_9285_ANT_DIV_MAIN_LNACONF) >>
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AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S;
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antconf->alt_lna_conf = (regval & AR_PHY_9285_ANT_DIV_ALT_LNACONF) >>
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AR_PHY_9285_ANT_DIV_ALT_LNACONF_S;
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antconf->fast_div_bias = (regval & AR_PHY_9285_FAST_DIV_BIAS) >>
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AR_PHY_9285_FAST_DIV_BIAS_S;
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antconf->lna1_lna2_switch_delta = -1;
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antconf->lna1_lna2_delta = -3;
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antconf->div_group = 0;
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}
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static void ar9002_hw_antdiv_comb_conf_set(struct ath_hw *ah,
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struct ath_hw_antcomb_conf *antconf)
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{
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u32 regval;
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regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
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regval &= ~(AR_PHY_9285_ANT_DIV_MAIN_LNACONF |
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AR_PHY_9285_ANT_DIV_ALT_LNACONF |
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AR_PHY_9285_FAST_DIV_BIAS);
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regval |= ((antconf->main_lna_conf << AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S)
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& AR_PHY_9285_ANT_DIV_MAIN_LNACONF);
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regval |= ((antconf->alt_lna_conf << AR_PHY_9285_ANT_DIV_ALT_LNACONF_S)
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& AR_PHY_9285_ANT_DIV_ALT_LNACONF);
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regval |= ((antconf->fast_div_bias << AR_PHY_9285_FAST_DIV_BIAS_S)
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& AR_PHY_9285_FAST_DIV_BIAS);
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REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regval);
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}
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#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
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static void ar9002_hw_set_bt_ant_diversity(struct ath_hw *ah, bool enable)
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{
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struct ath_btcoex_hw *btcoex = &ah->btcoex_hw;
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u8 antdiv_ctrl1, antdiv_ctrl2;
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u32 regval;
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if (enable) {
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antdiv_ctrl1 = ATH_BT_COEX_ANTDIV_CONTROL1_ENABLE;
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antdiv_ctrl2 = ATH_BT_COEX_ANTDIV_CONTROL2_ENABLE;
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/*
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* Don't disable BT ant to allow BB to control SWCOM.
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*/
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btcoex->bt_coex_mode2 &= (~(AR_BT_DISABLE_BT_ANT));
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REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex->bt_coex_mode2);
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REG_WRITE(ah, AR_PHY_SWITCH_COM, ATH_BT_COEX_ANT_DIV_SWITCH_COM);
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REG_RMW(ah, AR_PHY_SWITCH_CHAIN_0, 0, 0xf0000000);
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} else {
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/*
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* Disable antenna diversity, use LNA1 only.
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|
*/
|
|
antdiv_ctrl1 = ATH_BT_COEX_ANTDIV_CONTROL1_FIXED_A;
|
|
antdiv_ctrl2 = ATH_BT_COEX_ANTDIV_CONTROL2_FIXED_A;
|
|
|
|
/*
|
|
* Disable BT Ant. to allow concurrent BT and WLAN receive.
|
|
*/
|
|
btcoex->bt_coex_mode2 |= AR_BT_DISABLE_BT_ANT;
|
|
REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex->bt_coex_mode2);
|
|
|
|
/*
|
|
* Program SWCOM table to make sure RF switch always parks
|
|
* at BT side.
|
|
*/
|
|
REG_WRITE(ah, AR_PHY_SWITCH_COM, 0);
|
|
REG_RMW(ah, AR_PHY_SWITCH_CHAIN_0, 0, 0xf0000000);
|
|
}
|
|
|
|
regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
|
|
regval &= (~(AR_PHY_9285_ANT_DIV_CTL_ALL));
|
|
/*
|
|
* Clear ant_fast_div_bias [14:9] since for WB195,
|
|
* the main LNA is always LNA1.
|
|
*/
|
|
regval &= (~(AR_PHY_9285_FAST_DIV_BIAS));
|
|
regval |= SM(antdiv_ctrl1, AR_PHY_9285_ANT_DIV_CTL);
|
|
regval |= SM(antdiv_ctrl2, AR_PHY_9285_ANT_DIV_ALT_LNACONF);
|
|
regval |= SM((antdiv_ctrl2 >> 2), AR_PHY_9285_ANT_DIV_MAIN_LNACONF);
|
|
regval |= SM((antdiv_ctrl1 >> 1), AR_PHY_9285_ANT_DIV_ALT_GAINTB);
|
|
regval |= SM((antdiv_ctrl1 >> 2), AR_PHY_9285_ANT_DIV_MAIN_GAINTB);
|
|
REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regval);
|
|
|
|
regval = REG_READ(ah, AR_PHY_CCK_DETECT);
|
|
regval &= (~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
|
|
regval |= SM((antdiv_ctrl1 >> 3), AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
|
|
REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
|
|
}
|
|
|
|
#endif
|
|
|
|
static void ar9002_hw_spectral_scan_config(struct ath_hw *ah,
|
|
struct ath_spec_scan *param)
|
|
{
|
|
u32 repeat_bit;
|
|
u8 count;
|
|
|
|
if (!param->enabled) {
|
|
REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN,
|
|
AR_PHY_SPECTRAL_SCAN_ENABLE);
|
|
return;
|
|
}
|
|
REG_SET_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_FFT_ENA);
|
|
REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE);
|
|
|
|
if (AR_SREV_9280(ah))
|
|
repeat_bit = AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT;
|
|
else
|
|
repeat_bit = AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_KIWI;
|
|
|
|
if (param->short_repeat)
|
|
REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, repeat_bit);
|
|
else
|
|
REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN, repeat_bit);
|
|
|
|
/* on AR92xx, the highest bit of count will make the the chip send
|
|
* spectral samples endlessly. Check if this really was intended,
|
|
* and fix otherwise.
|
|
*/
|
|
count = param->count;
|
|
if (param->endless) {
|
|
if (AR_SREV_9280(ah))
|
|
count = 0x80;
|
|
else
|
|
count = 0;
|
|
} else if (count & 0x80)
|
|
count = 0x7f;
|
|
else if (!count)
|
|
count = 1;
|
|
|
|
if (AR_SREV_9280(ah)) {
|
|
REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
|
|
AR_PHY_SPECTRAL_SCAN_COUNT, count);
|
|
} else {
|
|
REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
|
|
AR_PHY_SPECTRAL_SCAN_COUNT_KIWI, count);
|
|
REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
|
|
AR_PHY_SPECTRAL_SCAN_PHYERR_MASK_SELECT);
|
|
}
|
|
|
|
REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
|
|
AR_PHY_SPECTRAL_SCAN_PERIOD, param->period);
|
|
REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
|
|
AR_PHY_SPECTRAL_SCAN_FFT_PERIOD, param->fft_period);
|
|
|
|
return;
|
|
}
|
|
|
|
static void ar9002_hw_spectral_scan_trigger(struct ath_hw *ah)
|
|
{
|
|
REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE);
|
|
/* Activate spectral scan */
|
|
REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
|
|
AR_PHY_SPECTRAL_SCAN_ACTIVE);
|
|
}
|
|
|
|
static void ar9002_hw_spectral_scan_wait(struct ath_hw *ah)
|
|
{
|
|
struct ath_common *common = ath9k_hw_common(ah);
|
|
|
|
/* Poll for spectral scan complete */
|
|
if (!ath9k_hw_wait(ah, AR_PHY_SPECTRAL_SCAN,
|
|
AR_PHY_SPECTRAL_SCAN_ACTIVE,
|
|
0, AH_WAIT_TIMEOUT)) {
|
|
ath_err(common, "spectral scan wait failed\n");
|
|
return;
|
|
}
|
|
}
|
|
|
|
static void ar9002_hw_tx99_start(struct ath_hw *ah, u32 qnum)
|
|
{
|
|
REG_SET_BIT(ah, 0x9864, 0x7f000);
|
|
REG_SET_BIT(ah, 0x9924, 0x7f00fe);
|
|
REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
|
|
REG_WRITE(ah, AR_CR, AR_CR_RXD);
|
|
REG_WRITE(ah, AR_DLCL_IFS(qnum), 0);
|
|
REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20);
|
|
REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20);
|
|
REG_WRITE(ah, AR_D_FPCTL, 0x10|qnum);
|
|
REG_WRITE(ah, AR_TIME_OUT, 0x00000400);
|
|
REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff);
|
|
REG_SET_BIT(ah, AR_QMISC(qnum), AR_Q_MISC_DCU_EARLY_TERM_REQ);
|
|
}
|
|
|
|
static void ar9002_hw_tx99_stop(struct ath_hw *ah)
|
|
{
|
|
REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
|
|
}
|
|
|
|
void ar9002_hw_attach_phy_ops(struct ath_hw *ah)
|
|
{
|
|
struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
|
|
struct ath_hw_ops *ops = ath9k_hw_ops(ah);
|
|
|
|
priv_ops->set_rf_regs = NULL;
|
|
priv_ops->rf_set_freq = ar9002_hw_set_channel;
|
|
priv_ops->spur_mitigate_freq = ar9002_hw_spur_mitigate;
|
|
priv_ops->olc_init = ar9002_olc_init;
|
|
priv_ops->compute_pll_control = ar9002_hw_compute_pll_control;
|
|
priv_ops->do_getnf = ar9002_hw_do_getnf;
|
|
|
|
ops->antdiv_comb_conf_get = ar9002_hw_antdiv_comb_conf_get;
|
|
ops->antdiv_comb_conf_set = ar9002_hw_antdiv_comb_conf_set;
|
|
ops->spectral_scan_config = ar9002_hw_spectral_scan_config;
|
|
ops->spectral_scan_trigger = ar9002_hw_spectral_scan_trigger;
|
|
ops->spectral_scan_wait = ar9002_hw_spectral_scan_wait;
|
|
|
|
#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
|
|
ops->set_bt_ant_diversity = ar9002_hw_set_bt_ant_diversity;
|
|
#endif
|
|
ops->tx99_start = ar9002_hw_tx99_start;
|
|
ops->tx99_stop = ar9002_hw_tx99_stop;
|
|
|
|
ar9002_hw_set_nf_limits(ah);
|
|
}
|