393 lines
13 KiB
C
393 lines
13 KiB
C
/*
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* Copyright (c) 2010-2011 Atheros Communications Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef AR9003_MCI_H
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#define AR9003_MCI_H
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#define MCI_FLAG_DISABLE_TIMESTAMP 0x00000001 /* Disable time stamp */
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#define MCI_RECOVERY_DUR_TSF (100 * 1000) /* 100 ms */
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/* Default remote BT device MCI COEX version */
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#define MCI_GPM_COEX_MAJOR_VERSION_DEFAULT 3
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#define MCI_GPM_COEX_MINOR_VERSION_DEFAULT 0
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/* Local WLAN MCI COEX version */
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#define MCI_GPM_COEX_MAJOR_VERSION_WLAN 3
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#define MCI_GPM_COEX_MINOR_VERSION_WLAN 0
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enum mci_gpm_coex_query_type {
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MCI_GPM_COEX_QUERY_BT_ALL_INFO = BIT(0),
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MCI_GPM_COEX_QUERY_BT_TOPOLOGY = BIT(1),
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MCI_GPM_COEX_QUERY_BT_DEBUG = BIT(2),
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};
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enum mci_gpm_coex_halt_bt_gpm {
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MCI_GPM_COEX_BT_GPM_UNHALT,
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MCI_GPM_COEX_BT_GPM_HALT
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};
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enum mci_gpm_coex_bt_update_flags_op {
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MCI_GPM_COEX_BT_FLAGS_READ,
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MCI_GPM_COEX_BT_FLAGS_SET,
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MCI_GPM_COEX_BT_FLAGS_CLEAR
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};
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#define MCI_NUM_BT_CHANNELS 79
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#define MCI_BT_MCI_FLAGS_UPDATE_CORR 0x00000002
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#define MCI_BT_MCI_FLAGS_UPDATE_HDR 0x00000004
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#define MCI_BT_MCI_FLAGS_UPDATE_PLD 0x00000008
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#define MCI_BT_MCI_FLAGS_LNA_CTRL 0x00000010
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#define MCI_BT_MCI_FLAGS_DEBUG 0x00000020
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#define MCI_BT_MCI_FLAGS_SCHED_MSG 0x00000040
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#define MCI_BT_MCI_FLAGS_CONT_MSG 0x00000080
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#define MCI_BT_MCI_FLAGS_COEX_GPM 0x00000100
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#define MCI_BT_MCI_FLAGS_CPU_INT_MSG 0x00000200
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#define MCI_BT_MCI_FLAGS_MCI_MODE 0x00000400
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#define MCI_BT_MCI_FLAGS_AR9462_MODE 0x00001000
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#define MCI_BT_MCI_FLAGS_OTHER 0x00010000
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#define MCI_DEFAULT_BT_MCI_FLAGS 0x00011dde
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#define MCI_TOGGLE_BT_MCI_FLAGS (MCI_BT_MCI_FLAGS_UPDATE_CORR | \
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MCI_BT_MCI_FLAGS_UPDATE_HDR | \
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MCI_BT_MCI_FLAGS_UPDATE_PLD | \
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MCI_BT_MCI_FLAGS_MCI_MODE)
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#define MCI_2G_FLAGS_CLEAR_MASK 0x00000000
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#define MCI_2G_FLAGS_SET_MASK MCI_TOGGLE_BT_MCI_FLAGS
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#define MCI_2G_FLAGS MCI_DEFAULT_BT_MCI_FLAGS
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#define MCI_5G_FLAGS_CLEAR_MASK MCI_TOGGLE_BT_MCI_FLAGS
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#define MCI_5G_FLAGS_SET_MASK 0x00000000
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#define MCI_5G_FLAGS (MCI_DEFAULT_BT_MCI_FLAGS & \
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~MCI_TOGGLE_BT_MCI_FLAGS)
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/*
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* Default value for AR9462 is 0x00002201
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*/
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#define ATH_MCI_CONFIG_CONCUR_TX 0x00000003
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#define ATH_MCI_CONFIG_MCI_OBS_MCI 0x00000004
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#define ATH_MCI_CONFIG_MCI_OBS_TXRX 0x00000008
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#define ATH_MCI_CONFIG_MCI_OBS_BT 0x00000010
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#define ATH_MCI_CONFIG_DISABLE_MCI_CAL 0x00000020
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#define ATH_MCI_CONFIG_DISABLE_OSLA 0x00000040
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#define ATH_MCI_CONFIG_DISABLE_FTP_STOMP 0x00000080
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#define ATH_MCI_CONFIG_AGGR_THRESH 0x00000700
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#define ATH_MCI_CONFIG_AGGR_THRESH_S 8
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#define ATH_MCI_CONFIG_DISABLE_AGGR_THRESH 0x00000800
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#define ATH_MCI_CONFIG_CLK_DIV 0x00003000
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#define ATH_MCI_CONFIG_CLK_DIV_S 12
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#define ATH_MCI_CONFIG_DISABLE_TUNING 0x00004000
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#define ATH_MCI_CONFIG_DISABLE_AIC 0x00008000
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#define ATH_MCI_CONFIG_AIC_CAL_NUM_CHAN 0x007f0000
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#define ATH_MCI_CONFIG_AIC_CAL_NUM_CHAN_S 16
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#define ATH_MCI_CONFIG_NO_QUIET_ACK 0x00800000
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#define ATH_MCI_CONFIG_NO_QUIET_ACK_S 23
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#define ATH_MCI_CONFIG_ANT_ARCH 0x07000000
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#define ATH_MCI_CONFIG_ANT_ARCH_S 24
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#define ATH_MCI_CONFIG_FORCE_QUIET_ACK 0x08000000
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#define ATH_MCI_CONFIG_FORCE_QUIET_ACK_S 27
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#define ATH_MCI_CONFIG_FORCE_2CHAIN_ACK 0x10000000
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#define ATH_MCI_CONFIG_MCI_STAT_DBG 0x20000000
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#define ATH_MCI_CONFIG_MCI_WEIGHT_DBG 0x40000000
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#define ATH_MCI_CONFIG_DISABLE_MCI 0x80000000
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#define ATH_MCI_CONFIG_MCI_OBS_MASK (ATH_MCI_CONFIG_MCI_OBS_MCI | \
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ATH_MCI_CONFIG_MCI_OBS_TXRX | \
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ATH_MCI_CONFIG_MCI_OBS_BT)
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#define ATH_MCI_CONFIG_MCI_OBS_GPIO 0x0000002F
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#define ATH_MCI_ANT_ARCH_1_ANT_PA_LNA_NON_SHARED 0x00
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#define ATH_MCI_ANT_ARCH_1_ANT_PA_LNA_SHARED 0x01
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#define ATH_MCI_ANT_ARCH_2_ANT_PA_LNA_NON_SHARED 0x02
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#define ATH_MCI_ANT_ARCH_2_ANT_PA_LNA_SHARED 0x03
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#define ATH_MCI_ANT_ARCH_3_ANT 0x04
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#define MCI_ANT_ARCH_PA_LNA_SHARED(mci) \
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((MS(mci->config, ATH_MCI_CONFIG_ANT_ARCH) == ATH_MCI_ANT_ARCH_1_ANT_PA_LNA_SHARED) || \
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(MS(mci->config, ATH_MCI_CONFIG_ANT_ARCH) == ATH_MCI_ANT_ARCH_2_ANT_PA_LNA_SHARED))
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enum mci_message_header { /* length of payload */
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MCI_LNA_CTRL = 0x10, /* len = 0 */
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MCI_CONT_NACK = 0x20, /* len = 0 */
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MCI_CONT_INFO = 0x30, /* len = 4 */
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MCI_CONT_RST = 0x40, /* len = 0 */
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MCI_SCHD_INFO = 0x50, /* len = 16 */
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MCI_CPU_INT = 0x60, /* len = 4 */
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MCI_SYS_WAKING = 0x70, /* len = 0 */
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MCI_GPM = 0x80, /* len = 16 */
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MCI_LNA_INFO = 0x90, /* len = 1 */
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MCI_LNA_STATE = 0x94,
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MCI_LNA_TAKE = 0x98,
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MCI_LNA_TRANS = 0x9c,
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MCI_SYS_SLEEPING = 0xa0, /* len = 0 */
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MCI_REQ_WAKE = 0xc0, /* len = 0 */
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MCI_DEBUG_16 = 0xfe, /* len = 2 */
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MCI_REMOTE_RESET = 0xff /* len = 16 */
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};
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enum ath_mci_gpm_coex_profile_type {
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MCI_GPM_COEX_PROFILE_UNKNOWN,
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MCI_GPM_COEX_PROFILE_RFCOMM,
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MCI_GPM_COEX_PROFILE_A2DP,
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MCI_GPM_COEX_PROFILE_HID,
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MCI_GPM_COEX_PROFILE_BNEP,
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MCI_GPM_COEX_PROFILE_VOICE,
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MCI_GPM_COEX_PROFILE_A2DPVO,
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MCI_GPM_COEX_PROFILE_MAX
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};
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/* MCI GPM/Coex opcode/type definitions */
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enum {
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MCI_GPM_COEX_W_GPM_PAYLOAD = 1,
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MCI_GPM_COEX_B_GPM_TYPE = 4,
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MCI_GPM_COEX_B_GPM_OPCODE = 5,
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/* MCI_GPM_WLAN_CAL_REQ, MCI_GPM_WLAN_CAL_DONE */
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MCI_GPM_WLAN_CAL_W_SEQUENCE = 2,
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/* MCI_GPM_COEX_VERSION_QUERY */
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/* MCI_GPM_COEX_VERSION_RESPONSE */
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MCI_GPM_COEX_B_MAJOR_VERSION = 6,
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MCI_GPM_COEX_B_MINOR_VERSION = 7,
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/* MCI_GPM_COEX_STATUS_QUERY */
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MCI_GPM_COEX_B_BT_BITMAP = 6,
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MCI_GPM_COEX_B_WLAN_BITMAP = 7,
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/* MCI_GPM_COEX_HALT_BT_GPM */
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MCI_GPM_COEX_B_HALT_STATE = 6,
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/* MCI_GPM_COEX_WLAN_CHANNELS */
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MCI_GPM_COEX_B_CHANNEL_MAP = 6,
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/* MCI_GPM_COEX_BT_PROFILE_INFO */
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MCI_GPM_COEX_B_PROFILE_TYPE = 6,
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MCI_GPM_COEX_B_PROFILE_LINKID = 7,
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MCI_GPM_COEX_B_PROFILE_STATE = 8,
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MCI_GPM_COEX_B_PROFILE_ROLE = 9,
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MCI_GPM_COEX_B_PROFILE_RATE = 10,
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MCI_GPM_COEX_B_PROFILE_VOTYPE = 11,
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MCI_GPM_COEX_H_PROFILE_T = 12,
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MCI_GPM_COEX_B_PROFILE_W = 14,
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MCI_GPM_COEX_B_PROFILE_A = 15,
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/* MCI_GPM_COEX_BT_STATUS_UPDATE */
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MCI_GPM_COEX_B_STATUS_TYPE = 6,
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MCI_GPM_COEX_B_STATUS_LINKID = 7,
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MCI_GPM_COEX_B_STATUS_STATE = 8,
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/* MCI_GPM_COEX_BT_UPDATE_FLAGS */
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MCI_GPM_COEX_W_BT_FLAGS = 6,
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MCI_GPM_COEX_B_BT_FLAGS_OP = 10
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};
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enum mci_gpm_subtype {
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MCI_GPM_BT_CAL_REQ = 0,
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MCI_GPM_BT_CAL_GRANT = 1,
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MCI_GPM_BT_CAL_DONE = 2,
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MCI_GPM_WLAN_CAL_REQ = 3,
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MCI_GPM_WLAN_CAL_GRANT = 4,
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MCI_GPM_WLAN_CAL_DONE = 5,
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MCI_GPM_COEX_AGENT = 0x0c,
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MCI_GPM_RSVD_PATTERN = 0xfe,
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MCI_GPM_RSVD_PATTERN32 = 0xfefefefe,
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MCI_GPM_BT_DEBUG = 0xff
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};
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enum mci_bt_state {
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MCI_BT_SLEEP,
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MCI_BT_AWAKE,
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MCI_BT_CAL_START,
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MCI_BT_CAL
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};
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enum mci_ps_state {
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MCI_PS_DISABLE,
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MCI_PS_ENABLE,
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MCI_PS_ENABLE_OFF,
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MCI_PS_ENABLE_ON
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};
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/* Type of state query */
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enum mci_state_type {
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MCI_STATE_ENABLE,
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MCI_STATE_INIT_GPM_OFFSET,
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MCI_STATE_CHECK_GPM_OFFSET,
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MCI_STATE_NEXT_GPM_OFFSET,
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MCI_STATE_LAST_GPM_OFFSET,
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MCI_STATE_BT,
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MCI_STATE_SET_BT_SLEEP,
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MCI_STATE_SET_BT_AWAKE,
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MCI_STATE_SET_BT_CAL_START,
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MCI_STATE_SET_BT_CAL,
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MCI_STATE_LAST_SCHD_MSG_OFFSET,
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MCI_STATE_REMOTE_SLEEP,
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MCI_STATE_CONT_STATUS,
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MCI_STATE_RESET_REQ_WAKE,
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MCI_STATE_SEND_WLAN_COEX_VERSION,
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MCI_STATE_SET_BT_COEX_VERSION,
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MCI_STATE_SEND_WLAN_CHANNELS,
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MCI_STATE_SEND_VERSION_QUERY,
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MCI_STATE_SEND_STATUS_QUERY,
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MCI_STATE_NEED_FLUSH_BT_INFO,
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MCI_STATE_SET_CONCUR_TX_PRI,
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MCI_STATE_RECOVER_RX,
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MCI_STATE_NEED_FTP_STOMP,
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MCI_STATE_NEED_TUNING,
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MCI_STATE_NEED_STAT_DEBUG,
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MCI_STATE_SHARED_CHAIN_CONCUR_TX,
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MCI_STATE_AIC_CAL,
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MCI_STATE_AIC_START,
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MCI_STATE_AIC_CAL_RESET,
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MCI_STATE_AIC_CAL_SINGLE,
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MCI_STATE_IS_AR9462,
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MCI_STATE_IS_AR9565_1ANT,
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MCI_STATE_IS_AR9565_2ANT,
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MCI_STATE_WLAN_WEAK_SIGNAL,
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MCI_STATE_SET_WLAN_PS_STATE,
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MCI_STATE_GET_WLAN_PS_STATE,
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MCI_STATE_DEBUG,
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MCI_STATE_STAT_DEBUG,
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MCI_STATE_ALLOW_FCS,
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MCI_STATE_SET_2G_CONTENTION,
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MCI_STATE_MAX
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};
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enum mci_gpm_coex_opcode {
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MCI_GPM_COEX_VERSION_QUERY,
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MCI_GPM_COEX_VERSION_RESPONSE,
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MCI_GPM_COEX_STATUS_QUERY,
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MCI_GPM_COEX_HALT_BT_GPM,
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MCI_GPM_COEX_WLAN_CHANNELS,
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MCI_GPM_COEX_BT_PROFILE_INFO,
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MCI_GPM_COEX_BT_STATUS_UPDATE,
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MCI_GPM_COEX_BT_UPDATE_FLAGS,
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MCI_GPM_COEX_NOOP,
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};
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#define MCI_GPM_NOMORE 0
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#define MCI_GPM_MORE 1
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#define MCI_GPM_INVALID 0xffffffff
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#define MCI_GPM_RECYCLE(_p_gpm) do { \
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*(((u32 *)_p_gpm) + MCI_GPM_COEX_W_GPM_PAYLOAD) = \
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MCI_GPM_RSVD_PATTERN32; \
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} while (0)
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#define MCI_GPM_TYPE(_p_gpm) \
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(*(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) & 0xff)
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#define MCI_GPM_OPCODE(_p_gpm) \
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(*(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_OPCODE) & 0xff)
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#define MCI_GPM_SET_CAL_TYPE(_p_gpm, _cal_type) do { \
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*(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) = (_cal_type) & 0xff;\
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} while (0)
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#define MCI_GPM_SET_TYPE_OPCODE(_p_gpm, _type, _opcode) do { \
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*(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) = (_type) & 0xff; \
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*(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_OPCODE) = (_opcode) & 0xff;\
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} while (0)
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#define MCI_GPM_IS_CAL_TYPE(_type) ((_type) <= MCI_GPM_WLAN_CAL_DONE)
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/*
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* Functions that are available to the MCI driver core.
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*/
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bool ar9003_mci_send_message(struct ath_hw *ah, u8 header, u32 flag,
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u32 *payload, u8 len, bool wait_done,
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bool check_bt);
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u32 ar9003_mci_state(struct ath_hw *ah, u32 state_type);
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int ar9003_mci_setup(struct ath_hw *ah, u32 gpm_addr, void *gpm_buf,
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u16 len, u32 sched_addr);
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void ar9003_mci_cleanup(struct ath_hw *ah);
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void ar9003_mci_get_interrupt(struct ath_hw *ah, u32 *raw_intr,
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u32 *rx_msg_intr);
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u32 ar9003_mci_get_next_gpm_offset(struct ath_hw *ah, u32 *more);
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void ar9003_mci_set_bt_version(struct ath_hw *ah, u8 major, u8 minor);
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void ar9003_mci_send_wlan_channels(struct ath_hw *ah);
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/*
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* These functions are used by ath9k_hw.
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*/
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#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
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void ar9003_mci_stop_bt(struct ath_hw *ah, bool save_fullsleep);
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void ar9003_mci_init_cal_req(struct ath_hw *ah, bool *is_reusable);
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void ar9003_mci_init_cal_done(struct ath_hw *ah);
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void ar9003_mci_set_full_sleep(struct ath_hw *ah);
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void ar9003_mci_2g5g_switch(struct ath_hw *ah, bool force);
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void ar9003_mci_check_bt(struct ath_hw *ah);
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bool ar9003_mci_start_reset(struct ath_hw *ah, struct ath9k_channel *chan);
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int ar9003_mci_end_reset(struct ath_hw *ah, struct ath9k_channel *chan,
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struct ath9k_hw_cal_data *caldata);
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int ar9003_mci_reset(struct ath_hw *ah, bool en_int, bool is_2g,
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bool is_full_sleep);
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void ar9003_mci_get_isr(struct ath_hw *ah, enum ath9k_int *masked);
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void ar9003_mci_bt_gain_ctrl(struct ath_hw *ah);
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void ar9003_mci_set_power_awake(struct ath_hw *ah);
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void ar9003_mci_check_gpm_offset(struct ath_hw *ah);
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u16 ar9003_mci_get_max_txpower(struct ath_hw *ah, u8 ctlmode);
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#else
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static inline void ar9003_mci_stop_bt(struct ath_hw *ah, bool save_fullsleep)
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{
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}
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static inline void ar9003_mci_init_cal_req(struct ath_hw *ah, bool *is_reusable)
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{
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}
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static inline void ar9003_mci_init_cal_done(struct ath_hw *ah)
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{
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}
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static inline void ar9003_mci_set_full_sleep(struct ath_hw *ah)
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{
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}
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static inline void ar9003_mci_2g5g_switch(struct ath_hw *ah, bool wait_done)
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{
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}
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static inline void ar9003_mci_check_bt(struct ath_hw *ah)
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{
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}
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static inline bool ar9003_mci_start_reset(struct ath_hw *ah, struct ath9k_channel *chan)
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{
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return false;
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}
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static inline int ar9003_mci_end_reset(struct ath_hw *ah, struct ath9k_channel *chan,
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struct ath9k_hw_cal_data *caldata)
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{
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return 0;
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}
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static inline void ar9003_mci_reset(struct ath_hw *ah, bool en_int, bool is_2g,
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bool is_full_sleep)
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{
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}
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static inline void ar9003_mci_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
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{
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}
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static inline void ar9003_mci_bt_gain_ctrl(struct ath_hw *ah)
|
|
{
|
|
}
|
|
static inline void ar9003_mci_set_power_awake(struct ath_hw *ah)
|
|
{
|
|
}
|
|
static inline void ar9003_mci_check_gpm_offset(struct ath_hw *ah)
|
|
{
|
|
}
|
|
static inline u16 ar9003_mci_get_max_txpower(struct ath_hw *ah, u8 ctlmode)
|
|
{
|
|
return -1;
|
|
}
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|
#endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */
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|
|
|
#endif
|