478 lines
16 KiB
C
478 lines
16 KiB
C
/******************************************************************************
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*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
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* Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
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* Copyright(c) 2015 - 2016 Intel Deutschland GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
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* USA
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*
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* The full GNU General Public License is included in this distribution
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* in the file called COPYING.
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*
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* Contact Information:
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* Intel Linux Wireless <linuxwifi@intel.com>
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* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*
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* BSD LICENSE
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*
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* Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
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* Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
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* Copyright(c) 2015 - 2016 Intel Deutschland GmbH
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*****************************************************************************/
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#ifndef __fw_api_rx_h__
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#define __fw_api_rx_h__
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/* API for pre-9000 hardware */
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#define IWL_RX_INFO_PHY_CNT 8
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#define IWL_RX_INFO_ENERGY_ANT_ABC_IDX 1
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#define IWL_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff
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#define IWL_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00
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#define IWL_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000
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#define IWL_RX_INFO_ENERGY_ANT_A_POS 0
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#define IWL_RX_INFO_ENERGY_ANT_B_POS 8
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#define IWL_RX_INFO_ENERGY_ANT_C_POS 16
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enum iwl_mac_context_info {
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MAC_CONTEXT_INFO_NONE,
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MAC_CONTEXT_INFO_GSCAN,
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};
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/**
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* struct iwl_rx_phy_info - phy info
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* (REPLY_RX_PHY_CMD = 0xc0)
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* @non_cfg_phy_cnt: non configurable DSP phy data byte count
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* @cfg_phy_cnt: configurable DSP phy data byte count
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* @stat_id: configurable DSP phy data set ID
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* @reserved1:
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* @system_timestamp: GP2 at on air rise
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* @timestamp: TSF at on air rise
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* @beacon_time_stamp: beacon at on-air rise
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* @phy_flags: general phy flags: band, modulation, ...
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* @channel: channel number
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* @non_cfg_phy_buf: for various implementations of non_cfg_phy
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* @rate_n_flags: RATE_MCS_*
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* @byte_count: frame's byte-count
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* @frame_time: frame's time on the air, based on byte count and frame rate
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* calculation
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* @mac_active_msk: what MACs were active when the frame was received
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* @mac_context_info: additional info on the context in which the frame was
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* received as defined in &enum iwl_mac_context_info
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*
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* Before each Rx, the device sends this data. It contains PHY information
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* about the reception of the packet.
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*/
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struct iwl_rx_phy_info {
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u8 non_cfg_phy_cnt;
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u8 cfg_phy_cnt;
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u8 stat_id;
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u8 reserved1;
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__le32 system_timestamp;
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__le64 timestamp;
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__le32 beacon_time_stamp;
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__le16 phy_flags;
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__le16 channel;
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__le32 non_cfg_phy[IWL_RX_INFO_PHY_CNT];
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__le32 rate_n_flags;
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__le32 byte_count;
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u8 mac_active_msk;
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u8 mac_context_info;
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__le16 frame_time;
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} __packed;
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/*
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* TCP offload Rx assist info
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*
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* bits 0:3 - reserved
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* bits 4:7 - MIC CRC length
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* bits 8:12 - MAC header length
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* bit 13 - Padding indication
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* bit 14 - A-AMSDU indication
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* bit 15 - Offload enabled
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*/
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enum iwl_csum_rx_assist_info {
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CSUM_RXA_RESERVED_MASK = 0x000f,
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CSUM_RXA_MICSIZE_MASK = 0x00f0,
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CSUM_RXA_HEADERLEN_MASK = 0x1f00,
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CSUM_RXA_PADD = BIT(13),
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CSUM_RXA_AMSDU = BIT(14),
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CSUM_RXA_ENA = BIT(15)
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};
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/**
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* struct iwl_rx_mpdu_res_start - phy info
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* @assist: see CSUM_RX_ASSIST_ above
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*/
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struct iwl_rx_mpdu_res_start {
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__le16 byte_count;
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__le16 assist;
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} __packed; /* _RX_MPDU_RES_START_API_S_VER_2 */
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/**
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* enum iwl_rx_phy_flags - to parse %iwl_rx_phy_info phy_flags
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* @RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band
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* @RX_RES_PHY_FLAGS_MOD_CCK:
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* @RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short
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* @RX_RES_PHY_FLAGS_NARROW_BAND:
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* @RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received
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* @RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU
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* @RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame
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* @RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble
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* @RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame
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*/
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enum iwl_rx_phy_flags {
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RX_RES_PHY_FLAGS_BAND_24 = BIT(0),
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RX_RES_PHY_FLAGS_MOD_CCK = BIT(1),
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RX_RES_PHY_FLAGS_SHORT_PREAMBLE = BIT(2),
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RX_RES_PHY_FLAGS_NARROW_BAND = BIT(3),
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RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4),
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RX_RES_PHY_FLAGS_ANTENNA_POS = 4,
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RX_RES_PHY_FLAGS_AGG = BIT(7),
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RX_RES_PHY_FLAGS_OFDM_HT = BIT(8),
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RX_RES_PHY_FLAGS_OFDM_GF = BIT(9),
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RX_RES_PHY_FLAGS_OFDM_VHT = BIT(10),
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};
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/**
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* enum iwl_mvm_rx_status - written by fw for each Rx packet
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* @RX_MPDU_RES_STATUS_CRC_OK: CRC is fine
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* @RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow
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* @RX_MPDU_RES_STATUS_SRC_STA_FOUND:
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* @RX_MPDU_RES_STATUS_KEY_VALID:
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* @RX_MPDU_RES_STATUS_KEY_PARAM_OK:
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* @RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed
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* @RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked
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* in the driver.
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* @RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine
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* @RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or
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* alg = CCM only. Checks replay attack for 11w frames. Relevant only if
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* %RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set.
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* @RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted
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* @RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP
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* @RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM
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* @RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP
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* @RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC
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* @RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted
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* @RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm
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* @RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted
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* @RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP:
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* @RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP:
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* @RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT:
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* @RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame
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* @RX_MPDU_RES_STATUS_CSUM_DONE: checksum was done by the hw
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* @RX_MPDU_RES_STATUS_CSUM_OK: checksum found no errors
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* @RX_MPDU_RES_STATUS_HASH_INDEX_MSK:
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* @RX_MPDU_RES_STATUS_STA_ID_MSK:
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* @RX_MPDU_RES_STATUS_RRF_KILL:
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* @RX_MPDU_RES_STATUS_FILTERING_MSK:
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* @RX_MPDU_RES_STATUS2_FILTERING_MSK:
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*/
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enum iwl_mvm_rx_status {
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RX_MPDU_RES_STATUS_CRC_OK = BIT(0),
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RX_MPDU_RES_STATUS_OVERRUN_OK = BIT(1),
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RX_MPDU_RES_STATUS_SRC_STA_FOUND = BIT(2),
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RX_MPDU_RES_STATUS_KEY_VALID = BIT(3),
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RX_MPDU_RES_STATUS_KEY_PARAM_OK = BIT(4),
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RX_MPDU_RES_STATUS_ICV_OK = BIT(5),
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RX_MPDU_RES_STATUS_MIC_OK = BIT(6),
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RX_MPDU_RES_STATUS_TTAK_OK = BIT(7),
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RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = BIT(7),
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RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8),
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RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8),
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RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8),
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RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8),
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RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8),
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RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC = (6 << 8),
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RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8),
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RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8),
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RX_MPDU_RES_STATUS_DEC_DONE = BIT(11),
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RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP = BIT(12),
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RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP = BIT(13),
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RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT = BIT(14),
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RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME = BIT(15),
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RX_MPDU_RES_STATUS_CSUM_DONE = BIT(16),
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RX_MPDU_RES_STATUS_CSUM_OK = BIT(17),
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RX_MPDU_RES_STATUS_HASH_INDEX_MSK = (0x3F0000),
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RX_MDPU_RES_STATUS_STA_ID_SHIFT = 24,
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RX_MPDU_RES_STATUS_STA_ID_MSK = 0x1f << RX_MDPU_RES_STATUS_STA_ID_SHIFT,
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RX_MPDU_RES_STATUS_RRF_KILL = BIT(29),
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RX_MPDU_RES_STATUS_FILTERING_MSK = (0xc00000),
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RX_MPDU_RES_STATUS2_FILTERING_MSK = (0xc0000000),
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};
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/* 9000 series API */
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enum iwl_rx_mpdu_mac_flags1 {
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IWL_RX_MDPU_MFLG1_ADDRTYPE_MASK = 0x03,
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IWL_RX_MPDU_MFLG1_MIC_CRC_LEN_MASK = 0xf0,
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/* shift should be 4, but the length is measured in 2-byte
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* words, so shifting only by 3 gives a byte result
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*/
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IWL_RX_MPDU_MFLG1_MIC_CRC_LEN_SHIFT = 3,
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};
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enum iwl_rx_mpdu_mac_flags2 {
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/* in 2-byte words */
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IWL_RX_MPDU_MFLG2_HDR_LEN_MASK = 0x1f,
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IWL_RX_MPDU_MFLG2_PAD = 0x20,
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IWL_RX_MPDU_MFLG2_AMSDU = 0x40,
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};
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enum iwl_rx_mpdu_amsdu_info {
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IWL_RX_MPDU_AMSDU_SUBFRAME_IDX_MASK = 0x7f,
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IWL_RX_MPDU_AMSDU_LAST_SUBFRAME = 0x80,
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};
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enum iwl_rx_l3_proto_values {
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IWL_RX_L3_TYPE_NONE,
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IWL_RX_L3_TYPE_IPV4,
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IWL_RX_L3_TYPE_IPV4_FRAG,
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IWL_RX_L3_TYPE_IPV6_FRAG,
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IWL_RX_L3_TYPE_IPV6,
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IWL_RX_L3_TYPE_IPV6_IN_IPV4,
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IWL_RX_L3_TYPE_ARP,
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IWL_RX_L3_TYPE_EAPOL,
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};
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#define IWL_RX_L3_PROTO_POS 4
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enum iwl_rx_l3l4_flags {
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IWL_RX_L3L4_IP_HDR_CSUM_OK = BIT(0),
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IWL_RX_L3L4_TCP_UDP_CSUM_OK = BIT(1),
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IWL_RX_L3L4_TCP_FIN_SYN_RST_PSH = BIT(2),
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IWL_RX_L3L4_TCP_ACK = BIT(3),
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IWL_RX_L3L4_L3_PROTO_MASK = 0xf << IWL_RX_L3_PROTO_POS,
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IWL_RX_L3L4_L4_PROTO_MASK = 0xf << 8,
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IWL_RX_L3L4_RSS_HASH_MASK = 0xf << 12,
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};
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enum iwl_rx_mpdu_status {
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IWL_RX_MPDU_STATUS_CRC_OK = BIT(0),
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IWL_RX_MPDU_STATUS_OVERRUN_OK = BIT(1),
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IWL_RX_MPDU_STATUS_SRC_STA_FOUND = BIT(2),
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IWL_RX_MPDU_STATUS_KEY_VALID = BIT(3),
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IWL_RX_MPDU_STATUS_KEY_PARAM_OK = BIT(4),
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IWL_RX_MPDU_STATUS_ICV_OK = BIT(5),
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IWL_RX_MPDU_STATUS_MIC_OK = BIT(6),
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IWL_RX_MPDU_RES_STATUS_TTAK_OK = BIT(7),
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IWL_RX_MPDU_STATUS_SEC_MASK = 0x7 << 8,
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IWL_RX_MPDU_STATUS_SEC_NONE = 0x0 << 8,
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IWL_RX_MPDU_STATUS_SEC_WEP = 0x1 << 8,
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IWL_RX_MPDU_STATUS_SEC_CCM = 0x2 << 8,
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IWL_RX_MPDU_STATUS_SEC_TKIP = 0x3 << 8,
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IWL_RX_MPDU_STATUS_SEC_EXT_ENC = 0x4 << 8,
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IWL_RX_MPDU_STATUS_SEC_GCM = 0x5 << 8,
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IWL_RX_MPDU_STATUS_DECRYPTED = BIT(11),
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IWL_RX_MPDU_STATUS_WEP_MATCH = BIT(12),
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IWL_RX_MPDU_STATUS_EXT_IV_MATCH = BIT(13),
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IWL_RX_MPDU_STATUS_KEY_ID_MATCH = BIT(14),
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IWL_RX_MPDU_STATUS_ROBUST_MNG_FRAME = BIT(15),
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};
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enum iwl_rx_mpdu_hash_filter {
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IWL_RX_MPDU_HF_A1_HASH_MASK = 0x3f,
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IWL_RX_MPDU_HF_FILTER_STATUS_MASK = 0xc0,
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};
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enum iwl_rx_mpdu_sta_id_flags {
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IWL_RX_MPDU_SIF_STA_ID_MASK = 0x1f,
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IWL_RX_MPDU_SIF_RRF_ABORT = 0x20,
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IWL_RX_MPDU_SIF_FILTER_STATUS_MASK = 0xc0,
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};
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#define IWL_RX_REORDER_DATA_INVALID_BAID 0x7f
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enum iwl_rx_mpdu_reorder_data {
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IWL_RX_MPDU_REORDER_NSSN_MASK = 0x00000fff,
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IWL_RX_MPDU_REORDER_SN_MASK = 0x00fff000,
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IWL_RX_MPDU_REORDER_SN_SHIFT = 12,
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IWL_RX_MPDU_REORDER_BAID_MASK = 0x7f000000,
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IWL_RX_MPDU_REORDER_BAID_SHIFT = 24,
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IWL_RX_MPDU_REORDER_BA_OLD_SN = 0x80000000,
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};
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enum iwl_rx_mpdu_phy_info {
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IWL_RX_MPDU_PHY_AMPDU = BIT(5),
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IWL_RX_MPDU_PHY_AMPDU_TOGGLE = BIT(6),
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IWL_RX_MPDU_PHY_SHORT_PREAMBLE = BIT(7),
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IWL_RX_MPDU_PHY_TSF_OVERLOAD = BIT(8),
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};
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enum iwl_rx_mpdu_mac_info {
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IWL_RX_MPDU_PHY_MAC_INDEX_MASK = 0x0f,
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IWL_RX_MPDU_PHY_PHY_INDEX_MASK = 0xf0,
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};
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struct iwl_rx_mpdu_desc {
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/* DW2 */
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__le16 mpdu_len;
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u8 mac_flags1;
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u8 mac_flags2;
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/* DW3 */
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u8 amsdu_info;
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__le16 phy_info;
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u8 mac_phy_idx;
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/* DW4 - carries csum data only when rpa_en == 1 */
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__le16 raw_csum; /* alledgedly unreliable */
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__le16 l3l4_flags;
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/* DW5 */
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__le16 status;
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u8 hash_filter;
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u8 sta_id_flags;
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/* DW6 */
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__le32 reorder_data;
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/* DW7 - carries rss_hash only when rpa_en == 1 */
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__le32 rss_hash;
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/* DW8 - carries filter_match only when rpa_en == 1 */
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__le32 filter_match;
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/* DW9 */
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__le32 rate_n_flags;
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/* DW10 */
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u8 energy_a, energy_b, channel, mac_context;
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/* DW11 */
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__le32 gp2_on_air_rise;
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/* DW12 & DW13 - carries TSF only TSF_OVERLOAD bit == 0 */
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__le64 tsf_on_air_rise;
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} __packed;
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struct iwl_frame_release {
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u8 baid;
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u8 reserved;
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__le16 nssn;
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};
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enum iwl_rss_hash_func_en {
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IWL_RSS_HASH_TYPE_IPV4_TCP,
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IWL_RSS_HASH_TYPE_IPV4_UDP,
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IWL_RSS_HASH_TYPE_IPV4_PAYLOAD,
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IWL_RSS_HASH_TYPE_IPV6_TCP,
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IWL_RSS_HASH_TYPE_IPV6_UDP,
|
|
IWL_RSS_HASH_TYPE_IPV6_PAYLOAD,
|
|
};
|
|
|
|
#define IWL_RSS_HASH_KEY_CNT 10
|
|
#define IWL_RSS_INDIRECTION_TABLE_SIZE 128
|
|
#define IWL_RSS_ENABLE 1
|
|
|
|
/**
|
|
* struct iwl_rss_config_cmd - RSS (Receive Side Scaling) configuration
|
|
*
|
|
* @flags: 1 - enable, 0 - disable
|
|
* @hash_mask: Type of RSS to use. Values are from %iwl_rss_hash_func_en
|
|
* @secret_key: 320 bit input of random key configuration from driver
|
|
* @indirection_table: indirection table
|
|
*/
|
|
struct iwl_rss_config_cmd {
|
|
__le32 flags;
|
|
u8 hash_mask;
|
|
u8 reserved[3];
|
|
__le32 secret_key[IWL_RSS_HASH_KEY_CNT];
|
|
u8 indirection_table[IWL_RSS_INDIRECTION_TABLE_SIZE];
|
|
} __packed; /* RSS_CONFIG_CMD_API_S_VER_1 */
|
|
|
|
#define IWL_MULTI_QUEUE_SYNC_MSG_MAX_SIZE 128
|
|
#define IWL_MULTI_QUEUE_SYNC_SENDER_POS 0
|
|
#define IWL_MULTI_QUEUE_SYNC_SENDER_MSK 0xf
|
|
|
|
/**
|
|
* struct iwl_rxq_sync_cmd - RXQ notification trigger
|
|
*
|
|
* @flags: flags of the notification. bit 0:3 are the sender queue
|
|
* @rxq_mask: rx queues to send the notification on
|
|
* @count: number of bytes in payload, should be DWORD aligned
|
|
* @payload: data to send to rx queues
|
|
*/
|
|
struct iwl_rxq_sync_cmd {
|
|
__le32 flags;
|
|
__le32 rxq_mask;
|
|
__le32 count;
|
|
u8 payload[];
|
|
} __packed; /* MULTI_QUEUE_DRV_SYNC_HDR_CMD_API_S_VER_1 */
|
|
|
|
/**
|
|
* struct iwl_rxq_sync_notification - Notification triggered by RXQ
|
|
* sync command
|
|
*
|
|
* @count: number of bytes in payload
|
|
* @payload: data to send to rx queues
|
|
*/
|
|
struct iwl_rxq_sync_notification {
|
|
__le32 count;
|
|
u8 payload[];
|
|
} __packed; /* MULTI_QUEUE_DRV_SYNC_HDR_CMD_API_S_VER_1 */
|
|
|
|
/**
|
|
* Internal message identifier
|
|
*
|
|
* @IWL_MVM_RXQ_EMPTY: empty sync notification
|
|
* @IWL_MVM_RXQ_NOTIF_DEL_BA: notify RSS queues of delBA
|
|
*/
|
|
enum iwl_mvm_rxq_notif_type {
|
|
IWL_MVM_RXQ_EMPTY,
|
|
IWL_MVM_RXQ_NOTIF_DEL_BA,
|
|
};
|
|
|
|
/**
|
|
* struct iwl_mvm_internal_rxq_notif - Internal representation of the data sent
|
|
* in &iwl_rxq_sync_cmd. Should be DWORD aligned.
|
|
* FW is agnostic to the payload, so there are no endianity requirements.
|
|
*
|
|
* @type: value from &iwl_mvm_rxq_notif_type
|
|
* @sync: ctrl path is waiting for all notifications to be received
|
|
* @cookie: internal cookie to identify old notifications
|
|
* @data: payload
|
|
*/
|
|
struct iwl_mvm_internal_rxq_notif {
|
|
u16 type;
|
|
u16 sync;
|
|
u32 cookie;
|
|
u8 data[];
|
|
} __packed;
|
|
|
|
#endif /* __fw_api_rx_h__ */
|