253 lines
6.4 KiB
C
253 lines
6.4 KiB
C
/*
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* phy-max16984-cdp.c -- MAXIM MAX16984 CDP PHY Driver
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*
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* This driver abstracts MAX16984 chip as a PHY which can be used
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* specifically for USB controller driver to turn on CDP (charging
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* downstream port) support of this chip.
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*
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* Copyright (c) 2016-2017, NVIDIA Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/gpio.h>
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#include <linux/module.h>
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#include <linux/of_gpio.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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/* soc config for different Tegra chips */
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struct max16984_tegra_soc_config {
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unsigned int num_phy;
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};
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/* MAX16984 control pins for each port */
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struct cdp_phy_port {
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int cd0_gpio;
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int cd1_gpio; /* not used for now */
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};
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/* MAX16984 as a external chip for CDP */
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struct max16984_cdp {
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struct device *dev;
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const struct max16984_tegra_soc_config *soc_config;
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struct phy_provider *provider;
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struct phy **cdp_phys;
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struct cdp_phy_port *cdp_ports;
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};
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static int phy_to_port(struct phy *phy)
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{
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struct max16984_cdp *cdp = phy_get_drvdata(phy);
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unsigned int i;
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for (i = 0; i < cdp->soc_config->num_phy; i++) {
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if (phy == cdp->cdp_phys[i])
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return i;
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}
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WARN_ON(1);
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return -EINVAL;
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}
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static int max16984_set_cdp(struct phy *phy, bool enable)
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{
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struct max16984_cdp *cdp = phy_get_drvdata(phy);
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int port = phy_to_port(phy);
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int gpio = cdp->cdp_ports[port].cd0_gpio;
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if (gpio_is_valid(gpio)) {
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dev_info(cdp->dev, "setting CD0 gpio %d of port %d = %d\n",
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gpio, port, enable ? 1 : 0);
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gpio_set_value(gpio, enable ? 1 : 0);
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} else {
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dev_warn(cdp->dev, "CD0 gpio %d of port %d invalid\n", gpio,
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port);
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return -EINVAL;
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}
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return 0;
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}
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static int max16984_cdp_phy_power_on(struct phy *phy)
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{
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return max16984_set_cdp(phy, true);
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}
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static int max16984_cdp_phy_power_off(struct phy *phy)
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{
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return max16984_set_cdp(phy, false);
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}
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static const struct phy_ops cdp_phy_ops = {
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.power_on = max16984_cdp_phy_power_on,
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.power_off = max16984_cdp_phy_power_off,
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.owner = THIS_MODULE,
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};
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static struct phy *max16984_phy_xlate(struct device *dev,
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struct of_phandle_args *args)
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{
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struct max16984_cdp *cdp = dev_get_drvdata(dev);
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unsigned int index;
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if (args->args_count <= 0)
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return ERR_PTR(-EINVAL);
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index = args->args[0];
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dev_dbg(dev, "%s index %d\n", __func__, index);
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if (index < cdp->soc_config->num_phy)
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return cdp->cdp_phys[index];
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return ERR_PTR(-EINVAL);
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}
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static const struct max16984_tegra_soc_config tegra210_soc_config = {
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.num_phy = 4,
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};
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static const struct max16984_tegra_soc_config tegra186_soc_config = {
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.num_phy = 3,
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};
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static const struct of_device_id max16984_of_match[] = {
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{ .compatible = "maxim,max16984-tegra210-cdp-phy",
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.data = &tegra210_soc_config },
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{ .compatible = "maxim,max16984-tegra186-cdp-phy",
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.data = &tegra186_soc_config },
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{}
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};
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MODULE_DEVICE_TABLE(of, max16984_of_match);
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static int max16984_probe(struct platform_device *pdev)
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{
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struct max16984_cdp *cdp;
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struct device *dev = &pdev->dev;
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const struct of_device_id *match;
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struct device_node *np = dev->of_node;
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int err;
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unsigned int i;
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cdp = devm_kzalloc(dev, sizeof(*cdp), GFP_KERNEL);
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if (!cdp)
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return -ENOMEM;
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platform_set_drvdata(pdev, cdp);
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cdp->dev = dev;
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match = of_match_node(max16984_of_match, np);
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if (!match)
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return -ENODEV;
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cdp->soc_config = match->data;
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WARN_ON(cdp->soc_config->num_phy == 0);
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cdp->cdp_phys = devm_kcalloc(dev, cdp->soc_config->num_phy,
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sizeof(struct phy *), GFP_KERNEL);
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if (!cdp->cdp_phys)
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return -ENOMEM;
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cdp->cdp_ports = devm_kcalloc(dev, cdp->soc_config->num_phy,
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sizeof(struct cdp_phy_port), GFP_KERNEL);
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if (!cdp->cdp_ports)
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return -ENOMEM;
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for (i = 0; i < cdp->soc_config->num_phy; i++) {
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char prop[128];
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int gpio;
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/* get CD0 gpio */
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snprintf(prop, sizeof(prop),
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"max,cdp-port%d-cd0-gpio", i);
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gpio = of_get_named_gpio(np, prop, 0);
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dev_dbg(dev, "max16984 port %d CD0 gpio [%s]: %d\n", i, prop,
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gpio);
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if (gpio == -EPROBE_DEFER)
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return -EPROBE_DEFER;
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if (gpio > 0) {
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err = devm_gpio_request_one(dev, gpio,
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GPIOF_DIR_OUT | GPIOF_INIT_HIGH,
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dev_name(dev));
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if (err < 0)
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dev_err(dev, "CDP port %d CD0 gpio %d request failed: %d\n",
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i, gpio, err);
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else
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cdp->cdp_ports[i].cd0_gpio = gpio;
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}
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/* get CD1 gpio */
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snprintf(prop, sizeof(prop),
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"max,cdp-port%d-cd1-gpio", i);
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gpio = of_get_named_gpio(np, prop, 0);
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dev_dbg(dev, "max16984 port %d CD1 gpio [%s]: %d\n", i, prop,
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gpio);
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if (gpio == -EPROBE_DEFER)
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return -EPROBE_DEFER;
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if (gpio > 0) {
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err = devm_gpio_request_one(dev, gpio,
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GPIOF_DIR_OUT | GPIOF_INIT_HIGH,
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dev_name(dev));
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if (err < 0)
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dev_err(dev, "CDP port %d CD1 gpio %d request failed: %d\n",
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i, gpio, err);
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else
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cdp->cdp_ports[i].cd1_gpio = gpio;
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}
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/* create phy for each UTMI port */
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cdp->cdp_phys[i] = devm_phy_create(dev, NULL, &cdp_phy_ops);
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if (IS_ERR(cdp->cdp_phys[i])) {
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err = PTR_ERR(cdp->cdp_phys[i]);
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dev_err(dev, "CDP phy %d create failed: %d\n", i, err);
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return err;
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}
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phy_set_drvdata(cdp->cdp_phys[i], cdp);
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}
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/* register as phy provider */
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cdp->provider = devm_of_phy_provider_register(dev, max16984_phy_xlate);
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if (IS_ERR(cdp->provider)) {
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err = PTR_ERR(cdp->provider);
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dev_err(dev, "failed to register PHYs: %d\n", err);
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return err;
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}
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return 0;
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}
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static struct platform_driver max16984_cdp_phy_driver = {
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.probe = max16984_probe,
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.driver = {
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.name = "max16984-cdp-phy",
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.of_match_table = max16984_of_match,
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.owner = THIS_MODULE,
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},
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};
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static int __init max16984_pinctrl_init(void)
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{
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return platform_driver_register(&max16984_cdp_phy_driver);
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}
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subsys_initcall(max16984_pinctrl_init);
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static void __exit max16984_pinctrl_exit(void)
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{
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platform_driver_unregister(&max16984_cdp_phy_driver);
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}
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module_exit(max16984_pinctrl_exit);
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MODULE_DESCRIPTION("Max16984 CDP PHY driver");
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MODULE_AUTHOR("Mark Kuo<mkuo@nvidia.com>");
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MODULE_ALIAS("platform:max16984-cdp-phy");
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MODULE_LICENSE("GPL v2");
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