377 lines
10 KiB
C
377 lines
10 KiB
C
/*
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* Copyright (c) 2015 Neil Armstrong <narmstrong@baylibre.com>
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* Copyright (c) 2014 Joachim Eastwood <manabian@gmail.com>
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* Copyright (c) 2012 NeilBrown <neilb@suse.de>
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* Heavily based on earlier code which is:
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* Copyright (c) 2010 Grant Erickson <marathon96@gmail.com>
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*
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* Also based on pwm-samsung.c
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* Description:
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* This file is the core OMAP support for the generic, Linux
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* PWM driver / controller, using the OMAP's dual-mode timers.
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*/
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/platform_data/pwm_omap_dmtimer.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/pwm.h>
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#include <linux/slab.h>
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#include <linux/time.h>
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#define DM_TIMER_LOAD_MIN 0xfffffffe
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#define DM_TIMER_MAX 0xffffffff
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struct pwm_omap_dmtimer_chip {
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struct pwm_chip chip;
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struct mutex mutex;
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pwm_omap_dmtimer *dm_timer;
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struct pwm_omap_dmtimer_pdata *pdata;
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struct platform_device *dm_timer_pdev;
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};
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static inline struct pwm_omap_dmtimer_chip *
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to_pwm_omap_dmtimer_chip(struct pwm_chip *chip)
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{
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return container_of(chip, struct pwm_omap_dmtimer_chip, chip);
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}
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static u32 pwm_omap_dmtimer_get_clock_cycles(unsigned long clk_rate, int ns)
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{
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return DIV_ROUND_CLOSEST_ULL((u64)clk_rate * ns, NSEC_PER_SEC);
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}
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static void pwm_omap_dmtimer_start(struct pwm_omap_dmtimer_chip *omap)
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{
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/*
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* According to OMAP 4 TRM section 22.2.4.10 the counter should be
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* started at 0xFFFFFFFE when overflow and match is used to ensure
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* that the PWM line is toggled on the first event.
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*
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* Note that omap_dm_timer_enable/disable is for register access and
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* not the timer counter itself.
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*/
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omap->pdata->enable(omap->dm_timer);
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omap->pdata->write_counter(omap->dm_timer, DM_TIMER_LOAD_MIN);
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omap->pdata->disable(omap->dm_timer);
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omap->pdata->start(omap->dm_timer);
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}
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static int pwm_omap_dmtimer_enable(struct pwm_chip *chip,
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struct pwm_device *pwm)
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{
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struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
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mutex_lock(&omap->mutex);
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pwm_omap_dmtimer_start(omap);
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mutex_unlock(&omap->mutex);
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return 0;
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}
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static void pwm_omap_dmtimer_disable(struct pwm_chip *chip,
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struct pwm_device *pwm)
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{
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struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
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mutex_lock(&omap->mutex);
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omap->pdata->stop(omap->dm_timer);
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mutex_unlock(&omap->mutex);
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}
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static int pwm_omap_dmtimer_config(struct pwm_chip *chip,
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struct pwm_device *pwm,
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int duty_ns, int period_ns)
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{
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struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
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u32 period_cycles, duty_cycles;
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u32 load_value, match_value;
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struct clk *fclk;
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unsigned long clk_rate;
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bool timer_active;
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dev_dbg(chip->dev, "requested duty cycle: %d ns, period: %d ns\n",
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duty_ns, period_ns);
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mutex_lock(&omap->mutex);
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if (duty_ns == pwm_get_duty_cycle(pwm) &&
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period_ns == pwm_get_period(pwm)) {
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/* No change - don't cause any transients. */
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mutex_unlock(&omap->mutex);
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return 0;
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}
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fclk = omap->pdata->get_fclk(omap->dm_timer);
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if (!fclk) {
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dev_err(chip->dev, "invalid pmtimer fclk\n");
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goto err_einval;
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}
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clk_rate = clk_get_rate(fclk);
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if (!clk_rate) {
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dev_err(chip->dev, "invalid pmtimer fclk rate\n");
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goto err_einval;
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}
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dev_dbg(chip->dev, "clk rate: %luHz\n", clk_rate);
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/*
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* Calculate the appropriate load and match values based on the
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* specified period and duty cycle. The load value determines the
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* period time and the match value determines the duty time.
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*
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* The period lasts for (DM_TIMER_MAX-load_value+1) clock cycles.
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* Similarly, the active time lasts (match_value-load_value+1) cycles.
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* The non-active time is the remainder: (DM_TIMER_MAX-match_value)
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* clock cycles.
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*
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* NOTE: It is required that: load_value <= match_value < DM_TIMER_MAX
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*
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* References:
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* OMAP4430/60/70 TRM sections 22.2.4.10 and 22.2.4.11
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* AM335x Sitara TRM sections 20.1.3.5 and 20.1.3.6
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*/
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period_cycles = pwm_omap_dmtimer_get_clock_cycles(clk_rate, period_ns);
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duty_cycles = pwm_omap_dmtimer_get_clock_cycles(clk_rate, duty_ns);
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if (period_cycles < 2) {
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dev_info(chip->dev,
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"period %d ns too short for clock rate %lu Hz\n",
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period_ns, clk_rate);
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goto err_einval;
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}
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if (duty_cycles < 1) {
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dev_dbg(chip->dev,
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"duty cycle %d ns is too short for clock rate %lu Hz\n",
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duty_ns, clk_rate);
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dev_dbg(chip->dev, "using minimum of 1 clock cycle\n");
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duty_cycles = 1;
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} else if (duty_cycles >= period_cycles) {
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dev_dbg(chip->dev,
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"duty cycle %d ns is too long for period %d ns at clock rate %lu Hz\n",
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duty_ns, period_ns, clk_rate);
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dev_dbg(chip->dev, "using maximum of 1 clock cycle less than period\n");
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duty_cycles = period_cycles - 1;
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}
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dev_dbg(chip->dev, "effective duty cycle: %lld ns, period: %lld ns\n",
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DIV_ROUND_CLOSEST_ULL((u64)NSEC_PER_SEC * duty_cycles,
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clk_rate),
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DIV_ROUND_CLOSEST_ULL((u64)NSEC_PER_SEC * period_cycles,
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clk_rate));
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load_value = (DM_TIMER_MAX - period_cycles) + 1;
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match_value = load_value + duty_cycles - 1;
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/*
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* We MUST stop the associated dual-mode timer before attempting to
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* write its registers, but calls to omap_dm_timer_start/stop must
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* be balanced so check if timer is active before calling timer_stop.
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*/
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timer_active = pm_runtime_active(&omap->dm_timer_pdev->dev);
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if (timer_active)
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omap->pdata->stop(omap->dm_timer);
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omap->pdata->set_load(omap->dm_timer, true, load_value);
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omap->pdata->set_match(omap->dm_timer, true, match_value);
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dev_dbg(chip->dev, "load value: %#08x (%d), match value: %#08x (%d)\n",
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load_value, load_value, match_value, match_value);
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omap->pdata->set_pwm(omap->dm_timer,
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pwm_get_polarity(pwm) == PWM_POLARITY_INVERSED,
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true,
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PWM_OMAP_DMTIMER_TRIGGER_OVERFLOW_AND_COMPARE);
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/* If config was called while timer was running it must be reenabled. */
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if (timer_active)
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pwm_omap_dmtimer_start(omap);
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mutex_unlock(&omap->mutex);
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return 0;
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err_einval:
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mutex_unlock(&omap->mutex);
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return -EINVAL;
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}
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static int pwm_omap_dmtimer_set_polarity(struct pwm_chip *chip,
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struct pwm_device *pwm,
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enum pwm_polarity polarity)
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{
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struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
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/*
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* PWM core will not call set_polarity while PWM is enabled so it's
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* safe to reconfigure the timer here without stopping it first.
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*/
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mutex_lock(&omap->mutex);
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omap->pdata->set_pwm(omap->dm_timer,
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polarity == PWM_POLARITY_INVERSED,
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true,
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PWM_OMAP_DMTIMER_TRIGGER_OVERFLOW_AND_COMPARE);
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mutex_unlock(&omap->mutex);
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return 0;
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}
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static const struct pwm_ops pwm_omap_dmtimer_ops = {
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.enable = pwm_omap_dmtimer_enable,
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.disable = pwm_omap_dmtimer_disable,
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.config = pwm_omap_dmtimer_config,
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.set_polarity = pwm_omap_dmtimer_set_polarity,
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.owner = THIS_MODULE,
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};
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static int pwm_omap_dmtimer_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct device_node *timer;
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struct pwm_omap_dmtimer_chip *omap;
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struct pwm_omap_dmtimer_pdata *pdata;
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pwm_omap_dmtimer *dm_timer;
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u32 v;
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int status;
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pdata = dev_get_platdata(&pdev->dev);
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if (!pdata) {
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dev_err(&pdev->dev, "Missing dmtimer platform data\n");
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return -EINVAL;
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}
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if (!pdata->request_by_node ||
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!pdata->free ||
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!pdata->enable ||
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!pdata->disable ||
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!pdata->get_fclk ||
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!pdata->start ||
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!pdata->stop ||
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!pdata->set_load ||
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!pdata->set_match ||
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!pdata->set_pwm ||
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!pdata->set_prescaler ||
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!pdata->write_counter) {
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dev_err(&pdev->dev, "Incomplete dmtimer pdata structure\n");
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return -EINVAL;
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}
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timer = of_parse_phandle(np, "ti,timers", 0);
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if (!timer)
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return -ENODEV;
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if (!of_get_property(timer, "ti,timer-pwm", NULL)) {
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dev_err(&pdev->dev, "Missing ti,timer-pwm capability\n");
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return -ENODEV;
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}
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dm_timer = pdata->request_by_node(timer);
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if (!dm_timer)
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return -EPROBE_DEFER;
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omap = devm_kzalloc(&pdev->dev, sizeof(*omap), GFP_KERNEL);
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if (!omap) {
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pdata->free(dm_timer);
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return -ENOMEM;
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}
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omap->pdata = pdata;
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omap->dm_timer = dm_timer;
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omap->dm_timer_pdev = of_find_device_by_node(timer);
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if (!omap->dm_timer_pdev) {
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dev_err(&pdev->dev, "Unable to find timer pdev\n");
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omap->pdata->free(dm_timer);
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return -EINVAL;
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}
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/*
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* Ensure that the timer is stopped before we allow PWM core to call
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* pwm_enable.
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*/
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if (pm_runtime_active(&omap->dm_timer_pdev->dev))
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omap->pdata->stop(omap->dm_timer);
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if (!of_property_read_u32(pdev->dev.of_node, "ti,prescaler", &v))
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omap->pdata->set_prescaler(omap->dm_timer, v);
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/* setup dmtimer clock source */
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if (!of_property_read_u32(pdev->dev.of_node, "ti,clock-source", &v))
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omap->pdata->set_source(omap->dm_timer, v);
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omap->chip.dev = &pdev->dev;
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omap->chip.ops = &pwm_omap_dmtimer_ops;
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omap->chip.base = -1;
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omap->chip.npwm = 1;
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omap->chip.of_xlate = of_pwm_xlate_with_flags;
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omap->chip.of_pwm_n_cells = 3;
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mutex_init(&omap->mutex);
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status = pwmchip_add(&omap->chip);
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if (status < 0) {
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dev_err(&pdev->dev, "failed to register PWM\n");
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omap->pdata->free(omap->dm_timer);
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return status;
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}
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platform_set_drvdata(pdev, omap);
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return 0;
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}
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static int pwm_omap_dmtimer_remove(struct platform_device *pdev)
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{
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struct pwm_omap_dmtimer_chip *omap = platform_get_drvdata(pdev);
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int ret;
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ret = pwmchip_remove(&omap->chip);
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if (ret)
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return ret;
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if (pm_runtime_active(&omap->dm_timer_pdev->dev))
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omap->pdata->stop(omap->dm_timer);
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omap->pdata->free(omap->dm_timer);
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mutex_destroy(&omap->mutex);
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return 0;
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}
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static const struct of_device_id pwm_omap_dmtimer_of_match[] = {
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{.compatible = "ti,omap-dmtimer-pwm"},
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{}
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};
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MODULE_DEVICE_TABLE(of, pwm_omap_dmtimer_of_match);
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static struct platform_driver pwm_omap_dmtimer_driver = {
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.driver = {
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.name = "omap-dmtimer-pwm",
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.of_match_table = of_match_ptr(pwm_omap_dmtimer_of_match),
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},
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.probe = pwm_omap_dmtimer_probe,
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.remove = pwm_omap_dmtimer_remove,
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};
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module_platform_driver(pwm_omap_dmtimer_driver);
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MODULE_AUTHOR("Grant Erickson <marathon96@gmail.com>");
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MODULE_AUTHOR("NeilBrown <neilb@suse.de>");
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MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("OMAP PWM Driver using Dual-mode Timers");
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