236 lines
6.1 KiB
C
236 lines
6.1 KiB
C
/*
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* Copyright 2008 Cisco Systems, Inc. All rights reserved.
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* Copyright 2007 Nuova Systems, Inc. All rights reserved.
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*
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* This program is free software; you may redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef _VNIC_RQ_H_
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#define _VNIC_RQ_H_
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#include <linux/pci.h>
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#include "vnic_dev.h"
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#include "vnic_cq.h"
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/*
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* These defines avoid symbol clash between fnic and enic (Cisco 10G Eth
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* Driver) when both are built with CONFIG options =y
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*/
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#define vnic_rq_desc_avail fnic_rq_desc_avail
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#define vnic_rq_desc_used fnic_rq_desc_used
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#define vnic_rq_next_desc fnic_rq_next_desc
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#define vnic_rq_next_index fnic_rq_next_index
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#define vnic_rq_next_buf_index fnic_rq_next_buf_index
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#define vnic_rq_post fnic_rq_post
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#define vnic_rq_posting_soon fnic_rq_posting_soon
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#define vnic_rq_return_descs fnic_rq_return_descs
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#define vnic_rq_service fnic_rq_service
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#define vnic_rq_fill fnic_rq_fill
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#define vnic_rq_free fnic_rq_free
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#define vnic_rq_alloc fnic_rq_alloc
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#define vnic_rq_init fnic_rq_init
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#define vnic_rq_error_status fnic_rq_error_status
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#define vnic_rq_enable fnic_rq_enable
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#define vnic_rq_disable fnic_rq_disable
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#define vnic_rq_clean fnic_rq_clean
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/* Receive queue control */
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struct vnic_rq_ctrl {
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u64 ring_base; /* 0x00 */
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u32 ring_size; /* 0x08 */
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u32 pad0;
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u32 posted_index; /* 0x10 */
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u32 pad1;
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u32 cq_index; /* 0x18 */
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u32 pad2;
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u32 enable; /* 0x20 */
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u32 pad3;
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u32 running; /* 0x28 */
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u32 pad4;
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u32 fetch_index; /* 0x30 */
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u32 pad5;
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u32 error_interrupt_enable; /* 0x38 */
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u32 pad6;
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u32 error_interrupt_offset; /* 0x40 */
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u32 pad7;
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u32 error_status; /* 0x48 */
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u32 pad8;
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u32 dropped_packet_count; /* 0x50 */
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u32 pad9;
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u32 dropped_packet_count_rc; /* 0x58 */
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u32 pad10;
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};
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/* Break the vnic_rq_buf allocations into blocks of 64 entries */
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#define VNIC_RQ_BUF_BLK_ENTRIES 64
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#define VNIC_RQ_BUF_BLK_SZ \
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(VNIC_RQ_BUF_BLK_ENTRIES * sizeof(struct vnic_rq_buf))
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#define VNIC_RQ_BUF_BLKS_NEEDED(entries) \
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DIV_ROUND_UP(entries, VNIC_RQ_BUF_BLK_ENTRIES)
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#define VNIC_RQ_BUF_BLKS_MAX VNIC_RQ_BUF_BLKS_NEEDED(4096)
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struct vnic_rq_buf {
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struct vnic_rq_buf *next;
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dma_addr_t dma_addr;
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void *os_buf;
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unsigned int os_buf_index;
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unsigned int len;
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unsigned int index;
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void *desc;
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};
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struct vnic_rq {
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unsigned int index;
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struct vnic_dev *vdev;
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struct vnic_rq_ctrl __iomem *ctrl; /* memory-mapped */
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struct vnic_dev_ring ring;
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struct vnic_rq_buf *bufs[VNIC_RQ_BUF_BLKS_MAX];
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struct vnic_rq_buf *to_use;
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struct vnic_rq_buf *to_clean;
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void *os_buf_head;
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unsigned int buf_index;
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unsigned int pkts_outstanding;
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};
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static inline unsigned int vnic_rq_desc_avail(struct vnic_rq *rq)
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{
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/* how many does SW own? */
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return rq->ring.desc_avail;
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}
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static inline unsigned int vnic_rq_desc_used(struct vnic_rq *rq)
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{
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/* how many does HW own? */
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return rq->ring.desc_count - rq->ring.desc_avail - 1;
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}
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static inline void *vnic_rq_next_desc(struct vnic_rq *rq)
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{
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return rq->to_use->desc;
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}
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static inline unsigned int vnic_rq_next_index(struct vnic_rq *rq)
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{
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return rq->to_use->index;
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}
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static inline unsigned int vnic_rq_next_buf_index(struct vnic_rq *rq)
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{
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return rq->buf_index++;
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}
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static inline void vnic_rq_post(struct vnic_rq *rq,
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void *os_buf, unsigned int os_buf_index,
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dma_addr_t dma_addr, unsigned int len)
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{
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struct vnic_rq_buf *buf = rq->to_use;
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buf->os_buf = os_buf;
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buf->os_buf_index = os_buf_index;
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buf->dma_addr = dma_addr;
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buf->len = len;
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buf = buf->next;
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rq->to_use = buf;
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rq->ring.desc_avail--;
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/* Move the posted_index every nth descriptor
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*/
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#ifndef VNIC_RQ_RETURN_RATE
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#define VNIC_RQ_RETURN_RATE 0xf /* keep 2^n - 1 */
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#endif
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if ((buf->index & VNIC_RQ_RETURN_RATE) == 0) {
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/* Adding write memory barrier prevents compiler and/or CPU
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* reordering, thus avoiding descriptor posting before
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* descriptor is initialized. Otherwise, hardware can read
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* stale descriptor fields.
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*/
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wmb();
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iowrite32(buf->index, &rq->ctrl->posted_index);
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}
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}
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static inline int vnic_rq_posting_soon(struct vnic_rq *rq)
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{
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return (rq->to_use->index & VNIC_RQ_RETURN_RATE) == 0;
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}
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static inline void vnic_rq_return_descs(struct vnic_rq *rq, unsigned int count)
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{
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rq->ring.desc_avail += count;
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}
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enum desc_return_options {
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VNIC_RQ_RETURN_DESC,
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VNIC_RQ_DEFER_RETURN_DESC,
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};
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static inline void vnic_rq_service(struct vnic_rq *rq,
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struct cq_desc *cq_desc, u16 completed_index,
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int desc_return, void (*buf_service)(struct vnic_rq *rq,
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struct cq_desc *cq_desc, struct vnic_rq_buf *buf,
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int skipped, void *opaque), void *opaque)
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{
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struct vnic_rq_buf *buf;
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int skipped;
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buf = rq->to_clean;
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while (1) {
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skipped = (buf->index != completed_index);
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(*buf_service)(rq, cq_desc, buf, skipped, opaque);
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if (desc_return == VNIC_RQ_RETURN_DESC)
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rq->ring.desc_avail++;
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rq->to_clean = buf->next;
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if (!skipped)
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break;
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buf = rq->to_clean;
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}
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}
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static inline int vnic_rq_fill(struct vnic_rq *rq,
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int (*buf_fill)(struct vnic_rq *rq))
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{
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int err;
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while (vnic_rq_desc_avail(rq) > 1) {
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err = (*buf_fill)(rq);
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if (err)
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return err;
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}
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return 0;
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}
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void vnic_rq_free(struct vnic_rq *rq);
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int vnic_rq_alloc(struct vnic_dev *vdev, struct vnic_rq *rq, unsigned int index,
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unsigned int desc_count, unsigned int desc_size);
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void vnic_rq_init(struct vnic_rq *rq, unsigned int cq_index,
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unsigned int error_interrupt_enable,
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unsigned int error_interrupt_offset);
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unsigned int vnic_rq_error_status(struct vnic_rq *rq);
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void vnic_rq_enable(struct vnic_rq *rq);
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int vnic_rq_disable(struct vnic_rq *rq);
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void vnic_rq_clean(struct vnic_rq *rq,
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void (*buf_clean)(struct vnic_rq *rq, struct vnic_rq_buf *buf));
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#endif /* _VNIC_RQ_H_ */
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