315 lines
8.8 KiB
C
315 lines
8.8 KiB
C
/*
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* Copyright (c) 2013-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/device.h>
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#include <linux/kernel.h>
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#include <linux/bug.h>
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#include <soc/tegra/fuse.h>
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#include "fuse.h"
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#define CPU_PROCESS_CORNERS 2
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#define GPU_PROCESS_CORNERS 2
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#define SOC_PROCESS_CORNERS 3
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#define FUSE_CPU_SPEEDO_0 0x014
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#define FUSE_CPU_SPEEDO_1 0x02c
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#define FUSE_CPU_SPEEDO_2 0x030
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#define FUSE_SOC_SPEEDO_0 0x034
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#define FUSE_SOC_SPEEDO_1 0x038
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#define FUSE_SOC_SPEEDO_2 0x03c
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#define FUSE_CPU_IDDQ 0x018
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#define FUSE_SOC_IDDQ 0x040
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#define FUSE_GPU_IDDQ 0x128
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#define FUSE_FT_REV 0x028
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enum {
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THRESHOLD_INDEX_0,
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THRESHOLD_INDEX_1,
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THRESHOLD_INDEX_2,
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THRESHOLD_INDEX_COUNT,
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};
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static const u32 __initconst cpu_process_speedos[][CPU_PROCESS_CORNERS] = {
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{ 2119, UINT_MAX },
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{ 2119, UINT_MAX },
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{ 1650, UINT_MAX },
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};
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static const u32 __initconst gpu_process_speedos[][GPU_PROCESS_CORNERS] = {
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{ UINT_MAX, UINT_MAX },
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{ UINT_MAX, UINT_MAX },
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{ UINT_MAX, UINT_MAX },
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};
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static const u32 __initconst soc_process_speedos[][SOC_PROCESS_CORNERS] = {
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{ 1950, 2073, UINT_MAX },
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{ UINT_MAX, UINT_MAX, UINT_MAX },
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{ 1598, 1709, UINT_MAX },
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};
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static u8 __init get_speedo_revision(void)
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{
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return tegra_fuse_read_spare(4) << 2 |
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tegra_fuse_read_spare(3) << 1 |
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tegra_fuse_read_spare(2) << 0;
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}
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static void __init rev_t210sku_to_speedo_ids(struct tegra_sku_info *sku_info,
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u8 speedo_rev, int *threshold)
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{
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int sku = sku_info->sku_id;
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int rev = sku_info->revision;
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bool a02 = (rev != TEGRA_REVISION_A01) && (rev != TEGRA_REVISION_A01q) &&
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(rev != TEGRA_REVISION_UNKNOWN);
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bool vcm31_sku = false;
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bool always_on = false;
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/* Assign to default */
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sku_info->cpu_speedo_id = 0;
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sku_info->soc_speedo_id = 0;
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sku_info->gpu_speedo_id = 0;
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sku_info->ucm = TEGRA_UCM1;
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*threshold = THRESHOLD_INDEX_0;
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#ifdef CONFIG_OF
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vcm31_sku = of_property_read_bool(of_chosen, "nvidia,t210-vcm31-sku");
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always_on = of_property_read_bool(of_chosen,
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"nvidia,tegra-always-on-personality");
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#endif
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switch (sku) {
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case 0x00: /* Engineering SKU */
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case 0x01: /* Engineering SKU */
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case 0x13:
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if (a02) {
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sku_info->cpu_speedo_id = 5;
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sku_info->gpu_speedo_id = 2;
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break;
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}
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/* fall through for a01 */
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case 0x07:
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case 0x17:
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case 0x1F:
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if (vcm31_sku && sku == 0x17) {
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sku_info->cpu_speedo_id = 4;
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sku_info->soc_speedo_id = 1;
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sku_info->gpu_speedo_id = 4;
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*threshold = THRESHOLD_INDEX_1;
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break;
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}
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if (a02) {
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sku_info->cpu_speedo_id = 7;
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sku_info->gpu_speedo_id = 2;
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if (always_on) {
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sku_info->cpu_speedo_id = 8;
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sku_info->ucm = TEGRA_UCM2;
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}
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break;
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}
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/* fall through for a01 */
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case 0x27:
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if (a02) {
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sku_info->cpu_speedo_id = 1;
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sku_info->gpu_speedo_id = 2;
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break;
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}
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sku_info->gpu_speedo_id = 1;
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break;
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case 0x57:
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sku_info->cpu_speedo_id = 4;
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sku_info->soc_speedo_id = 1;
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sku_info->gpu_speedo_id = 4;
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*threshold = THRESHOLD_INDEX_1;
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break;
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case 0x83:
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if (a02) {
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sku_info->cpu_speedo_id = 3;
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sku_info->gpu_speedo_id = 3;
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break;
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}
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/* fall through for a01 */
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case 0x87:
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if (a02) {
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sku_info->cpu_speedo_id = 2;
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sku_info->gpu_speedo_id = 1;
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break;
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}
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/* fall through for a01 */
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case 0x8F:
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if (a02 && always_on) {
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sku_info->cpu_speedo_id = 9;
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sku_info->gpu_speedo_id = 2;
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sku_info->ucm = TEGRA_UCM2;
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break;
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}
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default:
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pr_err("Tegra210: invalid combination of SKU/revision/mode:\n");
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pr_err("Tegra210: SKU %#04x, rev %d, vcm31 %d, always_on %d\n",
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sku, rev, vcm31_sku, always_on);
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/* Using the default for the error case */
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break;
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}
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}
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static void __init rev_t210b01sku_to_speedo_ids(struct tegra_sku_info *sku_info,
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u8 speedo_rev, int *threshold)
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{
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int sku = sku_info->sku_id;
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int rev = sku_info->revision;
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/* Assign to default */
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sku_info->cpu_speedo_id = 0;
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sku_info->soc_speedo_id = 0;
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sku_info->gpu_speedo_id = 1; /* T210b01 GPC PLL default NA mode */
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sku_info->ucm = TEGRA_UCM1;
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*threshold = THRESHOLD_INDEX_2;
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switch (sku) {
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case 0x00: /* Engineering SKU */
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case 0x01: /* Engineering SKU */
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case 0x83:
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break;
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case 0x87:
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sku_info->cpu_speedo_id = 3;
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break;
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default:
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pr_err("Tegra210b01: invalid combination of SKU/revision/mode:\n");
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pr_err("Tegra210b01: SKU %#04x, rev %d\n", sku, rev);
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/* Using the default for the error case */
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break;
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}
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}
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static bool __init is_t210b01_sku(struct tegra_sku_info *sku_info)
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{
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switch (sku_info->id_and_rev) {
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case TEGRA210B01_REVISION_A01:
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return true;
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default:
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break;
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}
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return false;
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}
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static void __init rev_sku_to_speedo_ids(struct tegra_sku_info *sku_info,
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u8 speedo_rev, int *threshold)
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{
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if (is_t210b01_sku(sku_info))
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rev_t210b01sku_to_speedo_ids(sku_info, speedo_rev, threshold);
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else
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rev_t210sku_to_speedo_ids(sku_info, speedo_rev, threshold);
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}
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static int get_process_id(int value, const u32 *speedos, unsigned int num)
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{
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unsigned int i;
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for (i = 0; i < num; i++)
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if (value < speedos[i])
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return i;
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return -EINVAL;
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}
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void __init tegra210_init_speedo_data(struct tegra_sku_info *sku_info)
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{
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int cpu_speedo[3], soc_speedo[3];
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unsigned int index;
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u8 speedo_revision = 0;
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BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) !=
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THRESHOLD_INDEX_COUNT);
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BUILD_BUG_ON(ARRAY_SIZE(gpu_process_speedos) !=
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THRESHOLD_INDEX_COUNT);
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BUILD_BUG_ON(ARRAY_SIZE(soc_process_speedos) !=
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THRESHOLD_INDEX_COUNT);
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/* Read speedo/IDDQ fuses */
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cpu_speedo[0] = tegra_fuse_read_early(FUSE_CPU_SPEEDO_0);
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cpu_speedo[1] = tegra_fuse_read_early(FUSE_CPU_SPEEDO_1);
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cpu_speedo[2] = tegra_fuse_read_early(FUSE_CPU_SPEEDO_2);
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soc_speedo[0] = tegra_fuse_read_early(FUSE_SOC_SPEEDO_0);
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soc_speedo[1] = tegra_fuse_read_early(FUSE_SOC_SPEEDO_1);
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soc_speedo[2] = tegra_fuse_read_early(FUSE_CPU_SPEEDO_2);
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sku_info->cpu_iddq_value = tegra_fuse_read_early(FUSE_CPU_IDDQ) * 4;
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sku_info->soc_iddq_value = tegra_fuse_read_early(FUSE_SOC_IDDQ) * 4;
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sku_info->gpu_iddq_value = tegra_fuse_read_early(FUSE_GPU_IDDQ) * 5;
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/*
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* Determine CPU, GPU and SoC speedo values depending on speedo fusing
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* revision. Note that GPU speedo value is fused in CPU_SPEEDO_2.
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*/
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speedo_revision = get_speedo_revision();
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sku_info->speedo_rev = speedo_revision;
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if (is_t210b01_sku(sku_info)) {
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sku_info->cpu_speedo_value = cpu_speedo[0];
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sku_info->gpu_speedo_value = cpu_speedo[2];
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sku_info->soc_speedo_value = soc_speedo[0];
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} else {
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if (speedo_revision >= 3) {
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sku_info->cpu_speedo_value = cpu_speedo[0];
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sku_info->gpu_speedo_value = cpu_speedo[2];
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sku_info->soc_speedo_value = soc_speedo[0];
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} else if (speedo_revision == 2) {
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sku_info->cpu_speedo_value =
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(-1938 + (1095 * cpu_speedo[0] / 100)) / 10;
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sku_info->gpu_speedo_value =
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(-1662 + (1082 * cpu_speedo[2] / 100)) / 10;
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sku_info->soc_speedo_value =
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(-705 + (1037 * soc_speedo[0] / 100)) / 10;
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} else {
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sku_info->cpu_speedo_value = 2100;
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sku_info->gpu_speedo_value = cpu_speedo[2] - 75;
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sku_info->soc_speedo_value = 1900;
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}
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}
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if ((sku_info->cpu_speedo_value <= 0) ||
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(sku_info->gpu_speedo_value <= 0) ||
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(sku_info->soc_speedo_value <= 0)) {
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WARN(1, "speedo value not fused\n");
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return;
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}
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rev_sku_to_speedo_ids(sku_info, speedo_revision, &index);
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sku_info->gpu_process_id = get_process_id(sku_info->gpu_speedo_value,
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gpu_process_speedos[index],
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GPU_PROCESS_CORNERS);
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sku_info->cpu_process_id = get_process_id(sku_info->cpu_speedo_value,
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cpu_process_speedos[index],
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CPU_PROCESS_CORNERS);
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sku_info->soc_process_id = get_process_id(sku_info->soc_speedo_value,
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soc_process_speedos[index],
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SOC_PROCESS_CORNERS);
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pr_info("Tegra Speedo/IDDQ fuse revision %u\n", speedo_revision);
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pr_info("Tegra: CPU Speedo ID %d, SoC Speedo ID %d, GPU Speedo ID %d\n",
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sku_info->cpu_speedo_id, sku_info->soc_speedo_id, sku_info->gpu_speedo_id);
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pr_info("Tegra: CPU Process ID %d, SoC Process ID %d, GPU Process ID %d\n",
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sku_info->cpu_process_id, sku_info->soc_process_id, sku_info->gpu_process_id);
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pr_info("Tegra: CPU Speedo Value %d, SoC Speedo Value %d, GPU Speedo Value %d\n",
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sku_info->cpu_speedo_value, sku_info->soc_speedo_value, sku_info->gpu_speedo_value);
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pr_info("Tegra: CPU IDDQ Value %d, SoC IDDQ Value %d, GPU IDDQ Value %d\n",
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sku_info->cpu_iddq_value, sku_info->soc_iddq_value, sku_info->gpu_iddq_value);
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}
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