746 lines
26 KiB
C
746 lines
26 KiB
C
/*
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*
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* Hardware accelerated Matrox Millennium I, II, Mystique, G100, G200 and G400
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*
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* (c) 1998-2002 Petr Vandrovec <vandrove@vc.cvut.cz>
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*
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* Portions Copyright (c) 2001 Matrox Graphics Inc.
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*
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* Version: 1.65 2002/08/14
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*
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* MTRR stuff: 1998 Tom Rini <trini@kernel.crashing.org>
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*
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* Contributors: "menion?" <menion@mindless.com>
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* Betatesting, fixes, ideas
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*
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* "Kurt Garloff" <garloff@suse.de>
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* Betatesting, fixes, ideas, videomodes, videomodes timmings
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*
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* "Tom Rini" <trini@kernel.crashing.org>
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* MTRR stuff, PPC cleanups, betatesting, fixes, ideas
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*
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* "Bibek Sahu" <scorpio@dodds.net>
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* Access device through readb|w|l and write b|w|l
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* Extensive debugging stuff
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*
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* "Daniel Haun" <haund@usa.net>
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* Testing, hardware cursor fixes
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*
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* "Scott Wood" <sawst46+@pitt.edu>
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* Fixes
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*
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* "Gerd Knorr" <kraxel@goldbach.isdn.cs.tu-berlin.de>
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* Betatesting
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*
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* "Kelly French" <targon@hazmat.com>
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* "Fernando Herrera" <fherrera@eurielec.etsit.upm.es>
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* Betatesting, bug reporting
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*
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* "Pablo Bianucci" <pbian@pccp.com.ar>
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* Fixes, ideas, betatesting
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*
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* "Inaky Perez Gonzalez" <inaky@peloncho.fis.ucm.es>
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* Fixes, enhandcements, ideas, betatesting
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*
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* "Ryuichi Oikawa" <roikawa@rr.iiij4u.or.jp>
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* PPC betatesting, PPC support, backward compatibility
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*
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* "Paul Womar" <Paul@pwomar.demon.co.uk>
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* "Owen Waller" <O.Waller@ee.qub.ac.uk>
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* PPC betatesting
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*
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* "Thomas Pornin" <pornin@bolet.ens.fr>
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* Alpha betatesting
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*
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* "Pieter van Leuven" <pvl@iae.nl>
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* "Ulf Jaenicke-Roessler" <ujr@physik.phy.tu-dresden.de>
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* G100 testing
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*
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* "H. Peter Arvin" <hpa@transmeta.com>
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* Ideas
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*
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* "Cort Dougan" <cort@cs.nmt.edu>
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* CHRP fixes and PReP cleanup
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*
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* "Mark Vojkovich" <mvojkovi@ucsd.edu>
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* G400 support
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*
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* (following author is not in any relation with this code, but his code
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* is included in this driver)
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*
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* Based on framebuffer driver for VBE 2.0 compliant graphic boards
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* (c) 1998 Gerd Knorr <kraxel@cs.tu-berlin.de>
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*
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* (following author is not in any relation with this code, but his ideas
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* were used when writing this driver)
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*
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* FreeVBE/AF (Matrox), "Shawn Hargreaves" <shawn@talula.demon.co.uk>
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*
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*/
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#include "matroxfb_Ti3026.h"
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#include "matroxfb_misc.h"
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#include "matroxfb_accel.h"
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#include <linux/matroxfb.h>
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#ifdef CONFIG_FB_MATROX_MILLENIUM
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#define outTi3026 matroxfb_DAC_out
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#define inTi3026 matroxfb_DAC_in
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#define TVP3026_INDEX 0x00
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#define TVP3026_PALWRADD 0x00
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#define TVP3026_PALDATA 0x01
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#define TVP3026_PIXRDMSK 0x02
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#define TVP3026_PALRDADD 0x03
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#define TVP3026_CURCOLWRADD 0x04
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#define TVP3026_CLOVERSCAN 0x00
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#define TVP3026_CLCOLOR0 0x01
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#define TVP3026_CLCOLOR1 0x02
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#define TVP3026_CLCOLOR2 0x03
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#define TVP3026_CURCOLDATA 0x05
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#define TVP3026_CURCOLRDADD 0x07
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#define TVP3026_CURCTRL 0x09
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#define TVP3026_X_DATAREG 0x0A
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#define TVP3026_CURRAMDATA 0x0B
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#define TVP3026_CURPOSXL 0x0C
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#define TVP3026_CURPOSXH 0x0D
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#define TVP3026_CURPOSYL 0x0E
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#define TVP3026_CURPOSYH 0x0F
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#define TVP3026_XSILICONREV 0x01
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#define TVP3026_XCURCTRL 0x06
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#define TVP3026_XCURCTRL_DIS 0x00 /* transparent, transparent, transparent, transparent */
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#define TVP3026_XCURCTRL_3COLOR 0x01 /* transparent, 0, 1, 2 */
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#define TVP3026_XCURCTRL_XGA 0x02 /* 0, 1, transparent, complement */
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#define TVP3026_XCURCTRL_XWIN 0x03 /* transparent, transparent, 0, 1 */
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#define TVP3026_XCURCTRL_BLANK2048 0x00
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#define TVP3026_XCURCTRL_BLANK4096 0x10
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#define TVP3026_XCURCTRL_INTERLACED 0x20
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#define TVP3026_XCURCTRL_ODD 0x00 /* ext.signal ODD/\EVEN */
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#define TVP3026_XCURCTRL_EVEN 0x40 /* ext.signal EVEN/\ODD */
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#define TVP3026_XCURCTRL_INDIRECT 0x00
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#define TVP3026_XCURCTRL_DIRECT 0x80
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#define TVP3026_XLATCHCTRL 0x0F
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#define TVP3026_XLATCHCTRL_1_1 0x06
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#define TVP3026_XLATCHCTRL_2_1 0x07
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#define TVP3026_XLATCHCTRL_4_1 0x06
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#define TVP3026_XLATCHCTRL_8_1 0x06
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#define TVP3026_XLATCHCTRL_16_1 0x06
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#define TVP3026A_XLATCHCTRL_4_3 0x06 /* ??? do not understand... but it works... !!! */
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#define TVP3026A_XLATCHCTRL_8_3 0x07
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#define TVP3026B_XLATCHCTRL_4_3 0x08
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#define TVP3026B_XLATCHCTRL_8_3 0x06 /* ??? do not understand... but it works... !!! */
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#define TVP3026_XTRUECOLORCTRL 0x18
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#define TVP3026_XTRUECOLORCTRL_VRAM_SHIFT_ACCEL 0x00
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#define TVP3026_XTRUECOLORCTRL_VRAM_SHIFT_TVP 0x20
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#define TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR 0x80
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#define TVP3026_XTRUECOLORCTRL_TRUECOLOR 0x40 /* paletized */
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#define TVP3026_XTRUECOLORCTRL_DIRECTCOLOR 0x00
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#define TVP3026_XTRUECOLORCTRL_24_ALTERNATE 0x08 /* 5:4/5:2 instead of 4:3/8:3 */
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#define TVP3026_XTRUECOLORCTRL_RGB_888 0x16 /* 4:3/8:3 (or 5:4/5:2) */
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#define TVP3026_XTRUECOLORCTRL_BGR_888 0x17
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#define TVP3026_XTRUECOLORCTRL_ORGB_8888 0x06
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#define TVP3026_XTRUECOLORCTRL_BGRO_8888 0x07
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#define TVP3026_XTRUECOLORCTRL_RGB_565 0x05
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#define TVP3026_XTRUECOLORCTRL_ORGB_1555 0x04
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#define TVP3026_XTRUECOLORCTRL_RGB_664 0x03
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#define TVP3026_XTRUECOLORCTRL_RGBO_4444 0x01
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#define TVP3026_XMUXCTRL 0x19
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#define TVP3026_XMUXCTRL_MEMORY_8BIT 0x01 /* - */
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#define TVP3026_XMUXCTRL_MEMORY_16BIT 0x02 /* - */
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#define TVP3026_XMUXCTRL_MEMORY_32BIT 0x03 /* 2MB RAM, 512K * 4 */
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#define TVP3026_XMUXCTRL_MEMORY_64BIT 0x04 /* >2MB RAM, 512K * 8 & more */
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#define TVP3026_XMUXCTRL_PIXEL_4BIT 0x40 /* L0,H0,L1,H1... */
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#define TVP3026_XMUXCTRL_PIXEL_4BIT_SWAPPED 0x60 /* H0,L0,H1,L1... */
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#define TVP3026_XMUXCTRL_PIXEL_8BIT 0x48
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#define TVP3026_XMUXCTRL_PIXEL_16BIT 0x50
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#define TVP3026_XMUXCTRL_PIXEL_32BIT 0x58
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#define TVP3026_XMUXCTRL_VGA 0x98 /* VGA MEMORY, 8BIT PIXEL */
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#define TVP3026_XCLKCTRL 0x1A
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#define TVP3026_XCLKCTRL_DIV1 0x00
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#define TVP3026_XCLKCTRL_DIV2 0x10
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#define TVP3026_XCLKCTRL_DIV4 0x20
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#define TVP3026_XCLKCTRL_DIV8 0x30
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#define TVP3026_XCLKCTRL_DIV16 0x40
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#define TVP3026_XCLKCTRL_DIV32 0x50
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#define TVP3026_XCLKCTRL_DIV64 0x60
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#define TVP3026_XCLKCTRL_CLKSTOPPED 0x70
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#define TVP3026_XCLKCTRL_SRC_CLK0 0x00
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#define TVP3026_XCLKCTRL_SRC_CLK1 0x01
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#define TVP3026_XCLKCTRL_SRC_CLK2 0x02 /* CLK2 is TTL source*/
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#define TVP3026_XCLKCTRL_SRC_NCLK2 0x03 /* not CLK2 is TTL source */
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#define TVP3026_XCLKCTRL_SRC_ECLK2 0x04 /* CLK2 and not CLK2 is ECL source */
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#define TVP3026_XCLKCTRL_SRC_PLL 0x05
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#define TVP3026_XCLKCTRL_SRC_DIS 0x06 /* disable & poweroff internal clock */
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#define TVP3026_XCLKCTRL_SRC_CLK0VGA 0x07
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#define TVP3026_XPALETTEPAGE 0x1C
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#define TVP3026_XGENCTRL 0x1D
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#define TVP3026_XGENCTRL_HSYNC_POS 0x00
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#define TVP3026_XGENCTRL_HSYNC_NEG 0x01
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#define TVP3026_XGENCTRL_VSYNC_POS 0x00
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#define TVP3026_XGENCTRL_VSYNC_NEG 0x02
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#define TVP3026_XGENCTRL_LITTLE_ENDIAN 0x00
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#define TVP3026_XGENCTRL_BIG_ENDIAN 0x08
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#define TVP3026_XGENCTRL_BLACK_0IRE 0x00
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#define TVP3026_XGENCTRL_BLACK_75IRE 0x10
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#define TVP3026_XGENCTRL_NO_SYNC_ON_GREEN 0x00
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#define TVP3026_XGENCTRL_SYNC_ON_GREEN 0x20
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#define TVP3026_XGENCTRL_OVERSCAN_DIS 0x00
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#define TVP3026_XGENCTRL_OVERSCAN_EN 0x40
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#define TVP3026_XMISCCTRL 0x1E
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#define TVP3026_XMISCCTRL_DAC_PUP 0x00
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#define TVP3026_XMISCCTRL_DAC_PDOWN 0x01
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#define TVP3026_XMISCCTRL_DAC_EXT 0x00 /* or 8, bit 3 is ignored */
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#define TVP3026_XMISCCTRL_DAC_6BIT 0x04
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#define TVP3026_XMISCCTRL_DAC_8BIT 0x0C
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#define TVP3026_XMISCCTRL_PSEL_DIS 0x00
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#define TVP3026_XMISCCTRL_PSEL_EN 0x10
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#define TVP3026_XMISCCTRL_PSEL_LOW 0x00 /* PSEL high selects directcolor */
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#define TVP3026_XMISCCTRL_PSEL_HIGH 0x20 /* PSEL high selects truecolor or pseudocolor */
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#define TVP3026_XGENIOCTRL 0x2A
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#define TVP3026_XGENIODATA 0x2B
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#define TVP3026_XPLLADDR 0x2C
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#define TVP3026_XPLLADDR_X(LOOP,MCLK,PIX) (((LOOP)<<4) | ((MCLK)<<2) | (PIX))
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#define TVP3026_XPLLDATA_N 0x00
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#define TVP3026_XPLLDATA_M 0x01
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#define TVP3026_XPLLDATA_P 0x02
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#define TVP3026_XPLLDATA_STAT 0x03
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#define TVP3026_XPIXPLLDATA 0x2D
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#define TVP3026_XMEMPLLDATA 0x2E
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#define TVP3026_XLOOPPLLDATA 0x2F
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#define TVP3026_XCOLKEYOVRMIN 0x30
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#define TVP3026_XCOLKEYOVRMAX 0x31
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#define TVP3026_XCOLKEYREDMIN 0x32
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#define TVP3026_XCOLKEYREDMAX 0x33
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#define TVP3026_XCOLKEYGREENMIN 0x34
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#define TVP3026_XCOLKEYGREENMAX 0x35
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#define TVP3026_XCOLKEYBLUEMIN 0x36
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#define TVP3026_XCOLKEYBLUEMAX 0x37
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#define TVP3026_XCOLKEYCTRL 0x38
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#define TVP3026_XCOLKEYCTRL_OVR_EN 0x01
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#define TVP3026_XCOLKEYCTRL_RED_EN 0x02
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#define TVP3026_XCOLKEYCTRL_GREEN_EN 0x04
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#define TVP3026_XCOLKEYCTRL_BLUE_EN 0x08
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#define TVP3026_XCOLKEYCTRL_NEGATE 0x10
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#define TVP3026_XCOLKEYCTRL_ZOOM1 0x00
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#define TVP3026_XCOLKEYCTRL_ZOOM2 0x20
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#define TVP3026_XCOLKEYCTRL_ZOOM4 0x40
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#define TVP3026_XCOLKEYCTRL_ZOOM8 0x60
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#define TVP3026_XCOLKEYCTRL_ZOOM16 0x80
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#define TVP3026_XCOLKEYCTRL_ZOOM32 0xA0
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#define TVP3026_XMEMPLLCTRL 0x39
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#define TVP3026_XMEMPLLCTRL_DIV(X) (((X)-1)>>1) /* 2,4,6,8,10,12,14,16, division applied to LOOP PLL after divide by 2^P */
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#define TVP3026_XMEMPLLCTRL_STROBEMKC4 0x08
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#define TVP3026_XMEMPLLCTRL_MCLK_DOTCLOCK 0x00 /* MKC4 */
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#define TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL 0x10 /* MKC4 */
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#define TVP3026_XMEMPLLCTRL_RCLK_PIXPLL 0x00
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#define TVP3026_XMEMPLLCTRL_RCLK_LOOPPLL 0x20
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#define TVP3026_XMEMPLLCTRL_RCLK_DOTDIVN 0x40 /* dot clock divided by loop pclk N prescaler */
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#define TVP3026_XSENSETEST 0x3A
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#define TVP3026_XTESTMODEDATA 0x3B
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#define TVP3026_XCRCREML 0x3C
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#define TVP3026_XCRCREMH 0x3D
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#define TVP3026_XCRCBITSEL 0x3E
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#define TVP3026_XID 0x3F
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static const unsigned char DACseq[] =
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{ TVP3026_XLATCHCTRL, TVP3026_XTRUECOLORCTRL,
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TVP3026_XMUXCTRL, TVP3026_XCLKCTRL,
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TVP3026_XPALETTEPAGE,
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TVP3026_XGENCTRL,
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TVP3026_XMISCCTRL,
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TVP3026_XGENIOCTRL,
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TVP3026_XGENIODATA,
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TVP3026_XCOLKEYOVRMIN, TVP3026_XCOLKEYOVRMAX, TVP3026_XCOLKEYREDMIN, TVP3026_XCOLKEYREDMAX,
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TVP3026_XCOLKEYGREENMIN, TVP3026_XCOLKEYGREENMAX, TVP3026_XCOLKEYBLUEMIN, TVP3026_XCOLKEYBLUEMAX,
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TVP3026_XCOLKEYCTRL,
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TVP3026_XMEMPLLCTRL, TVP3026_XSENSETEST, TVP3026_XCURCTRL };
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#define POS3026_XLATCHCTRL 0
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#define POS3026_XTRUECOLORCTRL 1
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#define POS3026_XMUXCTRL 2
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#define POS3026_XCLKCTRL 3
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#define POS3026_XGENCTRL 5
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#define POS3026_XMISCCTRL 6
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#define POS3026_XMEMPLLCTRL 18
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#define POS3026_XCURCTRL 20
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static const unsigned char MGADACbpp32[] =
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{ TVP3026_XLATCHCTRL_2_1, TVP3026_XTRUECOLORCTRL_DIRECTCOLOR | TVP3026_XTRUECOLORCTRL_ORGB_8888,
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0x00, TVP3026_XCLKCTRL_DIV1 | TVP3026_XCLKCTRL_SRC_PLL,
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0x00,
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TVP3026_XGENCTRL_HSYNC_POS | TVP3026_XGENCTRL_VSYNC_POS | TVP3026_XGENCTRL_LITTLE_ENDIAN | TVP3026_XGENCTRL_BLACK_0IRE | TVP3026_XGENCTRL_NO_SYNC_ON_GREEN | TVP3026_XGENCTRL_OVERSCAN_DIS,
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TVP3026_XMISCCTRL_DAC_PUP | TVP3026_XMISCCTRL_DAC_8BIT | TVP3026_XMISCCTRL_PSEL_DIS | TVP3026_XMISCCTRL_PSEL_HIGH,
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0x00,
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0x1E,
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0xFF, 0xFF, 0xFF, 0xFF,
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0xFF, 0xFF, 0xFF, 0xFF,
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TVP3026_XCOLKEYCTRL_ZOOM1,
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0x00, 0x00, TVP3026_XCURCTRL_DIS };
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static int Ti3026_calcclock(const struct matrox_fb_info *minfo,
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unsigned int freq, unsigned int fmax, int *in,
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int *feed, int *post)
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{
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unsigned int fvco;
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unsigned int lin, lfeed, lpost;
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DBG(__func__)
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fvco = PLL_calcclock(minfo, freq, fmax, &lin, &lfeed, &lpost);
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fvco >>= (*post = lpost);
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*in = 64 - lin;
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*feed = 64 - lfeed;
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return fvco;
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}
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static int Ti3026_setpclk(struct matrox_fb_info *minfo, int clk)
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{
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unsigned int f_pll;
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unsigned int pixfeed, pixin, pixpost;
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struct matrox_hw_state *hw = &minfo->hw;
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DBG(__func__)
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f_pll = Ti3026_calcclock(minfo, clk, minfo->max_pixel_clock, &pixin, &pixfeed, &pixpost);
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hw->DACclk[0] = pixin | 0xC0;
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hw->DACclk[1] = pixfeed;
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hw->DACclk[2] = pixpost | 0xB0;
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{
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unsigned int loopfeed, loopin, looppost, loopdiv, z;
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unsigned int Bpp;
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Bpp = minfo->curr.final_bppShift;
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if (minfo->fbcon.var.bits_per_pixel == 24) {
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loopfeed = 3; /* set lm to any possible value */
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loopin = 3 * 32 / Bpp;
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} else {
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loopfeed = 4;
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loopin = 4 * 32 / Bpp;
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}
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z = (110000 * loopin) / (f_pll * loopfeed);
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loopdiv = 0; /* div 2 */
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if (z < 2)
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looppost = 0;
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else if (z < 4)
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looppost = 1;
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else if (z < 8)
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looppost = 2;
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else {
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looppost = 3;
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loopdiv = z/16;
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}
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if (minfo->fbcon.var.bits_per_pixel == 24) {
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hw->DACclk[3] = ((65 - loopin) & 0x3F) | 0xC0;
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hw->DACclk[4] = (65 - loopfeed) | 0x80;
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if (minfo->accel.ramdac_rev > 0x20) {
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if (isInterleave(minfo))
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hw->DACreg[POS3026_XLATCHCTRL] = TVP3026B_XLATCHCTRL_8_3;
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else {
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hw->DACclk[4] &= ~0xC0;
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hw->DACreg[POS3026_XLATCHCTRL] = TVP3026B_XLATCHCTRL_4_3;
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}
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} else {
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if (isInterleave(minfo))
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; /* default... */
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else {
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hw->DACclk[4] ^= 0xC0; /* change from 0x80 to 0x40 */
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hw->DACreg[POS3026_XLATCHCTRL] = TVP3026A_XLATCHCTRL_4_3;
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}
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}
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hw->DACclk[5] = looppost | 0xF8;
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if (minfo->devflags.mga_24bpp_fix)
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hw->DACclk[5] ^= 0x40;
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} else {
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hw->DACclk[3] = ((65 - loopin) & 0x3F) | 0xC0;
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hw->DACclk[4] = 65 - loopfeed;
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hw->DACclk[5] = looppost | 0xF0;
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}
|
|
hw->DACreg[POS3026_XMEMPLLCTRL] = loopdiv | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL | TVP3026_XMEMPLLCTRL_RCLK_LOOPPLL;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int Ti3026_init(struct matrox_fb_info *minfo, struct my_timming *m)
|
|
{
|
|
u_int8_t muxctrl = isInterleave(minfo) ? TVP3026_XMUXCTRL_MEMORY_64BIT : TVP3026_XMUXCTRL_MEMORY_32BIT;
|
|
struct matrox_hw_state *hw = &minfo->hw;
|
|
|
|
DBG(__func__)
|
|
|
|
memcpy(hw->DACreg, MGADACbpp32, sizeof(MGADACbpp32));
|
|
switch (minfo->fbcon.var.bits_per_pixel) {
|
|
case 4: hw->DACreg[POS3026_XLATCHCTRL] = TVP3026_XLATCHCTRL_16_1; /* or _8_1, they are same */
|
|
hw->DACreg[POS3026_XTRUECOLORCTRL] = TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR;
|
|
hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_4BIT;
|
|
hw->DACreg[POS3026_XCLKCTRL] = TVP3026_XCLKCTRL_SRC_PLL | TVP3026_XCLKCTRL_DIV8;
|
|
hw->DACreg[POS3026_XMISCCTRL] = TVP3026_XMISCCTRL_DAC_PUP | TVP3026_XMISCCTRL_DAC_8BIT | TVP3026_XMISCCTRL_PSEL_DIS | TVP3026_XMISCCTRL_PSEL_LOW;
|
|
break;
|
|
case 8: hw->DACreg[POS3026_XLATCHCTRL] = TVP3026_XLATCHCTRL_8_1; /* or _4_1, they are same */
|
|
hw->DACreg[POS3026_XTRUECOLORCTRL] = TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR;
|
|
hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_8BIT;
|
|
hw->DACreg[POS3026_XCLKCTRL] = TVP3026_XCLKCTRL_SRC_PLL | TVP3026_XCLKCTRL_DIV4;
|
|
hw->DACreg[POS3026_XMISCCTRL] = TVP3026_XMISCCTRL_DAC_PUP | TVP3026_XMISCCTRL_DAC_8BIT | TVP3026_XMISCCTRL_PSEL_DIS | TVP3026_XMISCCTRL_PSEL_LOW;
|
|
break;
|
|
case 16:
|
|
/* XLATCHCTRL should be _4_1 / _2_1... Why is not? (_2_1 is used every time) */
|
|
hw->DACreg[POS3026_XTRUECOLORCTRL] = (minfo->fbcon.var.green.length == 5) ? (TVP3026_XTRUECOLORCTRL_DIRECTCOLOR | TVP3026_XTRUECOLORCTRL_ORGB_1555) : (TVP3026_XTRUECOLORCTRL_DIRECTCOLOR | TVP3026_XTRUECOLORCTRL_RGB_565);
|
|
hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_16BIT;
|
|
hw->DACreg[POS3026_XCLKCTRL] = TVP3026_XCLKCTRL_SRC_PLL | TVP3026_XCLKCTRL_DIV2;
|
|
break;
|
|
case 24:
|
|
/* XLATCHCTRL is: for (A) use _4_3 (?_8_3 is same? TBD), for (B) it is set in setpclk */
|
|
hw->DACreg[POS3026_XTRUECOLORCTRL] = TVP3026_XTRUECOLORCTRL_DIRECTCOLOR | TVP3026_XTRUECOLORCTRL_RGB_888;
|
|
hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_32BIT;
|
|
hw->DACreg[POS3026_XCLKCTRL] = TVP3026_XCLKCTRL_SRC_PLL | TVP3026_XCLKCTRL_DIV4;
|
|
break;
|
|
case 32:
|
|
/* XLATCHCTRL should be _2_1 / _1_1... Why is not? (_2_1 is used every time) */
|
|
hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_32BIT;
|
|
break;
|
|
default:
|
|
return 1; /* TODO: failed */
|
|
}
|
|
if (matroxfb_vgaHWinit(minfo, m)) return 1;
|
|
|
|
/* set SYNC */
|
|
hw->MiscOutReg = 0xCB;
|
|
if (m->sync & FB_SYNC_HOR_HIGH_ACT)
|
|
hw->DACreg[POS3026_XGENCTRL] |= TVP3026_XGENCTRL_HSYNC_NEG;
|
|
if (m->sync & FB_SYNC_VERT_HIGH_ACT)
|
|
hw->DACreg[POS3026_XGENCTRL] |= TVP3026_XGENCTRL_VSYNC_NEG;
|
|
if (m->sync & FB_SYNC_ON_GREEN)
|
|
hw->DACreg[POS3026_XGENCTRL] |= TVP3026_XGENCTRL_SYNC_ON_GREEN;
|
|
|
|
/* set DELAY */
|
|
if (minfo->video.len < 0x400000)
|
|
hw->CRTCEXT[3] |= 0x08;
|
|
else if (minfo->video.len > 0x400000)
|
|
hw->CRTCEXT[3] |= 0x10;
|
|
|
|
/* set HWCURSOR */
|
|
if (m->interlaced) {
|
|
hw->DACreg[POS3026_XCURCTRL] |= TVP3026_XCURCTRL_INTERLACED;
|
|
}
|
|
if (m->HTotal >= 1536)
|
|
hw->DACreg[POS3026_XCURCTRL] |= TVP3026_XCURCTRL_BLANK4096;
|
|
|
|
/* set interleaving */
|
|
hw->MXoptionReg &= ~0x00001000;
|
|
if (isInterleave(minfo)) hw->MXoptionReg |= 0x00001000;
|
|
|
|
/* set DAC */
|
|
Ti3026_setpclk(minfo, m->pixclock);
|
|
return 0;
|
|
}
|
|
|
|
static void ti3026_setMCLK(struct matrox_fb_info *minfo, int fout)
|
|
{
|
|
unsigned int f_pll;
|
|
unsigned int pclk_m, pclk_n, pclk_p;
|
|
unsigned int mclk_m, mclk_n, mclk_p;
|
|
unsigned int rfhcnt, mclk_ctl;
|
|
int tmout;
|
|
|
|
DBG(__func__)
|
|
|
|
f_pll = Ti3026_calcclock(minfo, fout, minfo->max_pixel_clock, &mclk_n, &mclk_m, &mclk_p);
|
|
|
|
/* save pclk */
|
|
outTi3026(minfo, TVP3026_XPLLADDR, 0xFC);
|
|
pclk_n = inTi3026(minfo, TVP3026_XPIXPLLDATA);
|
|
outTi3026(minfo, TVP3026_XPLLADDR, 0xFD);
|
|
pclk_m = inTi3026(minfo, TVP3026_XPIXPLLDATA);
|
|
outTi3026(minfo, TVP3026_XPLLADDR, 0xFE);
|
|
pclk_p = inTi3026(minfo, TVP3026_XPIXPLLDATA);
|
|
|
|
/* stop pclk */
|
|
outTi3026(minfo, TVP3026_XPLLADDR, 0xFE);
|
|
outTi3026(minfo, TVP3026_XPIXPLLDATA, 0x00);
|
|
|
|
/* set pclk to new mclk */
|
|
outTi3026(minfo, TVP3026_XPLLADDR, 0xFC);
|
|
outTi3026(minfo, TVP3026_XPIXPLLDATA, mclk_n | 0xC0);
|
|
outTi3026(minfo, TVP3026_XPIXPLLDATA, mclk_m);
|
|
outTi3026(minfo, TVP3026_XPIXPLLDATA, mclk_p | 0xB0);
|
|
|
|
/* wait for PLL to lock */
|
|
for (tmout = 500000; tmout; tmout--) {
|
|
if (inTi3026(minfo, TVP3026_XPIXPLLDATA) & 0x40)
|
|
break;
|
|
udelay(10);
|
|
}
|
|
if (!tmout)
|
|
printk(KERN_ERR "matroxfb: Temporary pixel PLL not locked after 5 secs\n");
|
|
|
|
/* output pclk on mclk pin */
|
|
mclk_ctl = inTi3026(minfo, TVP3026_XMEMPLLCTRL);
|
|
outTi3026(minfo, TVP3026_XMEMPLLCTRL, mclk_ctl & 0xE7);
|
|
outTi3026(minfo, TVP3026_XMEMPLLCTRL, (mclk_ctl & 0xE7) | TVP3026_XMEMPLLCTRL_STROBEMKC4);
|
|
|
|
/* stop MCLK */
|
|
outTi3026(minfo, TVP3026_XPLLADDR, 0xFB);
|
|
outTi3026(minfo, TVP3026_XMEMPLLDATA, 0x00);
|
|
|
|
/* set mclk to new freq */
|
|
outTi3026(minfo, TVP3026_XPLLADDR, 0xF3);
|
|
outTi3026(minfo, TVP3026_XMEMPLLDATA, mclk_n | 0xC0);
|
|
outTi3026(minfo, TVP3026_XMEMPLLDATA, mclk_m);
|
|
outTi3026(minfo, TVP3026_XMEMPLLDATA, mclk_p | 0xB0);
|
|
|
|
/* wait for PLL to lock */
|
|
for (tmout = 500000; tmout; tmout--) {
|
|
if (inTi3026(minfo, TVP3026_XMEMPLLDATA) & 0x40)
|
|
break;
|
|
udelay(10);
|
|
}
|
|
if (!tmout)
|
|
printk(KERN_ERR "matroxfb: Memory PLL not locked after 5 secs\n");
|
|
|
|
f_pll = f_pll * 333 / (10000 << mclk_p);
|
|
if (isMilleniumII(minfo)) {
|
|
rfhcnt = (f_pll - 128) / 256;
|
|
if (rfhcnt > 15)
|
|
rfhcnt = 15;
|
|
} else {
|
|
rfhcnt = (f_pll - 64) / 128;
|
|
if (rfhcnt > 15)
|
|
rfhcnt = 0;
|
|
}
|
|
minfo->hw.MXoptionReg = (minfo->hw.MXoptionReg & ~0x000F0000) | (rfhcnt << 16);
|
|
pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg);
|
|
|
|
/* output MCLK to MCLK pin */
|
|
outTi3026(minfo, TVP3026_XMEMPLLCTRL, (mclk_ctl & 0xE7) | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL);
|
|
outTi3026(minfo, TVP3026_XMEMPLLCTRL, (mclk_ctl ) | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL | TVP3026_XMEMPLLCTRL_STROBEMKC4);
|
|
|
|
/* stop PCLK */
|
|
outTi3026(minfo, TVP3026_XPLLADDR, 0xFE);
|
|
outTi3026(minfo, TVP3026_XPIXPLLDATA, 0x00);
|
|
|
|
/* restore pclk */
|
|
outTi3026(minfo, TVP3026_XPLLADDR, 0xFC);
|
|
outTi3026(minfo, TVP3026_XPIXPLLDATA, pclk_n);
|
|
outTi3026(minfo, TVP3026_XPIXPLLDATA, pclk_m);
|
|
outTi3026(minfo, TVP3026_XPIXPLLDATA, pclk_p);
|
|
|
|
/* wait for PLL to lock */
|
|
for (tmout = 500000; tmout; tmout--) {
|
|
if (inTi3026(minfo, TVP3026_XPIXPLLDATA) & 0x40)
|
|
break;
|
|
udelay(10);
|
|
}
|
|
if (!tmout)
|
|
printk(KERN_ERR "matroxfb: Pixel PLL not locked after 5 secs\n");
|
|
}
|
|
|
|
static void ti3026_ramdac_init(struct matrox_fb_info *minfo)
|
|
{
|
|
DBG(__func__)
|
|
|
|
minfo->features.pll.vco_freq_min = 110000;
|
|
minfo->features.pll.ref_freq = 114545;
|
|
minfo->features.pll.feed_div_min = 2;
|
|
minfo->features.pll.feed_div_max = 24;
|
|
minfo->features.pll.in_div_min = 2;
|
|
minfo->features.pll.in_div_max = 63;
|
|
minfo->features.pll.post_shift_max = 3;
|
|
if (minfo->devflags.noinit)
|
|
return;
|
|
ti3026_setMCLK(minfo, 60000);
|
|
}
|
|
|
|
static void Ti3026_restore(struct matrox_fb_info *minfo)
|
|
{
|
|
int i;
|
|
unsigned char progdac[6];
|
|
struct matrox_hw_state *hw = &minfo->hw;
|
|
CRITFLAGS
|
|
|
|
DBG(__func__)
|
|
|
|
#ifdef DEBUG
|
|
dprintk(KERN_INFO "EXTVGA regs: ");
|
|
for (i = 0; i < 6; i++)
|
|
dprintk("%02X:", hw->CRTCEXT[i]);
|
|
dprintk("\n");
|
|
#endif
|
|
|
|
CRITBEGIN
|
|
|
|
pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
|
|
|
|
CRITEND
|
|
|
|
matroxfb_vgaHWrestore(minfo);
|
|
|
|
CRITBEGIN
|
|
|
|
minfo->crtc1.panpos = -1;
|
|
for (i = 0; i < 6; i++)
|
|
mga_setr(M_EXTVGA_INDEX, i, hw->CRTCEXT[i]);
|
|
|
|
for (i = 0; i < 21; i++) {
|
|
outTi3026(minfo, DACseq[i], hw->DACreg[i]);
|
|
}
|
|
|
|
outTi3026(minfo, TVP3026_XPLLADDR, 0x00);
|
|
progdac[0] = inTi3026(minfo, TVP3026_XPIXPLLDATA);
|
|
progdac[3] = inTi3026(minfo, TVP3026_XLOOPPLLDATA);
|
|
outTi3026(minfo, TVP3026_XPLLADDR, 0x15);
|
|
progdac[1] = inTi3026(minfo, TVP3026_XPIXPLLDATA);
|
|
progdac[4] = inTi3026(minfo, TVP3026_XLOOPPLLDATA);
|
|
outTi3026(minfo, TVP3026_XPLLADDR, 0x2A);
|
|
progdac[2] = inTi3026(minfo, TVP3026_XPIXPLLDATA);
|
|
progdac[5] = inTi3026(minfo, TVP3026_XLOOPPLLDATA);
|
|
|
|
CRITEND
|
|
if (memcmp(hw->DACclk, progdac, 6)) {
|
|
/* agrhh... setting up PLL is very slow on Millennium... */
|
|
/* Mystique PLL is locked in few ms, but Millennium PLL lock takes about 0.15 s... */
|
|
/* Maybe even we should call schedule() ? */
|
|
|
|
CRITBEGIN
|
|
outTi3026(minfo, TVP3026_XCLKCTRL, hw->DACreg[POS3026_XCLKCTRL]);
|
|
outTi3026(minfo, TVP3026_XPLLADDR, 0x2A);
|
|
outTi3026(minfo, TVP3026_XLOOPPLLDATA, 0);
|
|
outTi3026(minfo, TVP3026_XPIXPLLDATA, 0);
|
|
|
|
outTi3026(minfo, TVP3026_XPLLADDR, 0x00);
|
|
for (i = 0; i < 3; i++)
|
|
outTi3026(minfo, TVP3026_XPIXPLLDATA, hw->DACclk[i]);
|
|
/* wait for PLL only if PLL clock requested (always for PowerMode, never for VGA) */
|
|
if (hw->MiscOutReg & 0x08) {
|
|
int tmout;
|
|
outTi3026(minfo, TVP3026_XPLLADDR, 0x3F);
|
|
for (tmout = 500000; tmout; --tmout) {
|
|
if (inTi3026(minfo, TVP3026_XPIXPLLDATA) & 0x40)
|
|
break;
|
|
udelay(10);
|
|
}
|
|
|
|
CRITEND
|
|
|
|
if (!tmout)
|
|
printk(KERN_ERR "matroxfb: Pixel PLL not locked after 5 secs\n");
|
|
else
|
|
dprintk(KERN_INFO "PixelPLL: %d\n", 500000-tmout);
|
|
CRITBEGIN
|
|
}
|
|
outTi3026(minfo, TVP3026_XMEMPLLCTRL, hw->DACreg[POS3026_XMEMPLLCTRL]);
|
|
outTi3026(minfo, TVP3026_XPLLADDR, 0x00);
|
|
for (i = 3; i < 6; i++)
|
|
outTi3026(minfo, TVP3026_XLOOPPLLDATA, hw->DACclk[i]);
|
|
CRITEND
|
|
if ((hw->MiscOutReg & 0x08) && ((hw->DACclk[5] & 0x80) == 0x80)) {
|
|
int tmout;
|
|
|
|
CRITBEGIN
|
|
outTi3026(minfo, TVP3026_XPLLADDR, 0x3F);
|
|
for (tmout = 500000; tmout; --tmout) {
|
|
if (inTi3026(minfo, TVP3026_XLOOPPLLDATA) & 0x40)
|
|
break;
|
|
udelay(10);
|
|
}
|
|
CRITEND
|
|
if (!tmout)
|
|
printk(KERN_ERR "matroxfb: Loop PLL not locked after 5 secs\n");
|
|
else
|
|
dprintk(KERN_INFO "LoopPLL: %d\n", 500000-tmout);
|
|
}
|
|
}
|
|
|
|
#ifdef DEBUG
|
|
dprintk(KERN_DEBUG "3026DACregs ");
|
|
for (i = 0; i < 21; i++) {
|
|
dprintk("R%02X=%02X ", DACseq[i], hw->DACreg[i]);
|
|
if ((i & 0x7) == 0x7) dprintk(KERN_DEBUG "continuing... ");
|
|
}
|
|
dprintk(KERN_DEBUG "DACclk ");
|
|
for (i = 0; i < 6; i++)
|
|
dprintk("C%02X=%02X ", i, hw->DACclk[i]);
|
|
dprintk("\n");
|
|
#endif
|
|
}
|
|
|
|
static void Ti3026_reset(struct matrox_fb_info *minfo)
|
|
{
|
|
DBG(__func__)
|
|
|
|
ti3026_ramdac_init(minfo);
|
|
}
|
|
|
|
static struct matrox_altout ti3026_output = {
|
|
.name = "Primary output",
|
|
};
|
|
|
|
static int Ti3026_preinit(struct matrox_fb_info *minfo)
|
|
{
|
|
static const int vxres_mill2[] = { 512, 640, 768, 800, 832, 960,
|
|
1024, 1152, 1280, 1600, 1664, 1920,
|
|
2048, 0};
|
|
static const int vxres_mill1[] = { 640, 768, 800, 960,
|
|
1024, 1152, 1280, 1600, 1920,
|
|
2048, 0};
|
|
struct matrox_hw_state *hw = &minfo->hw;
|
|
|
|
DBG(__func__)
|
|
|
|
minfo->millenium = 1;
|
|
minfo->milleniumII = (minfo->pcidev->device != PCI_DEVICE_ID_MATROX_MIL);
|
|
minfo->capable.cfb4 = 1;
|
|
minfo->capable.text = 1; /* isMilleniumII(minfo); */
|
|
minfo->capable.vxres = isMilleniumII(minfo) ? vxres_mill2 : vxres_mill1;
|
|
|
|
minfo->outputs[0].data = minfo;
|
|
minfo->outputs[0].output = &ti3026_output;
|
|
minfo->outputs[0].src = minfo->outputs[0].default_src;
|
|
minfo->outputs[0].mode = MATROXFB_OUTPUT_MODE_MONITOR;
|
|
|
|
if (minfo->devflags.noinit)
|
|
return 0;
|
|
/* preserve VGA I/O, BIOS and PPC */
|
|
hw->MXoptionReg &= 0xC0000100;
|
|
hw->MXoptionReg |= 0x002C0000;
|
|
if (minfo->devflags.novga)
|
|
hw->MXoptionReg &= ~0x00000100;
|
|
if (minfo->devflags.nobios)
|
|
hw->MXoptionReg &= ~0x40000000;
|
|
if (minfo->devflags.nopciretry)
|
|
hw->MXoptionReg |= 0x20000000;
|
|
pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
|
|
|
|
minfo->accel.ramdac_rev = inTi3026(minfo, TVP3026_XSILICONREV);
|
|
|
|
outTi3026(minfo, TVP3026_XCLKCTRL, TVP3026_XCLKCTRL_SRC_CLK0VGA | TVP3026_XCLKCTRL_CLKSTOPPED);
|
|
outTi3026(minfo, TVP3026_XTRUECOLORCTRL, TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR);
|
|
outTi3026(minfo, TVP3026_XMUXCTRL, TVP3026_XMUXCTRL_VGA);
|
|
|
|
outTi3026(minfo, TVP3026_XPLLADDR, 0x2A);
|
|
outTi3026(minfo, TVP3026_XLOOPPLLDATA, 0x00);
|
|
outTi3026(minfo, TVP3026_XPIXPLLDATA, 0x00);
|
|
|
|
mga_outb(M_MISC_REG, 0x67);
|
|
|
|
outTi3026(minfo, TVP3026_XMEMPLLCTRL, TVP3026_XMEMPLLCTRL_STROBEMKC4 | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL);
|
|
|
|
mga_outl(M_RESET, 1);
|
|
udelay(250);
|
|
mga_outl(M_RESET, 0);
|
|
udelay(250);
|
|
mga_outl(M_MACCESS, 0x00008000);
|
|
udelay(10);
|
|
return 0;
|
|
}
|
|
|
|
struct matrox_switch matrox_millennium = {
|
|
Ti3026_preinit, Ti3026_reset, Ti3026_init, Ti3026_restore
|
|
};
|
|
EXPORT_SYMBOL(matrox_millennium);
|
|
#endif
|
|
MODULE_LICENSE("GPL");
|