1019 lines
25 KiB
C
1019 lines
25 KiB
C
/*
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* Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef MLX5_DRIVER_H
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#define MLX5_DRIVER_H
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#include <linux/kernel.h>
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#include <linux/completion.h>
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#include <linux/pci.h>
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#include <linux/spinlock_types.h>
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#include <linux/semaphore.h>
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#include <linux/slab.h>
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#include <linux/vmalloc.h>
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#include <linux/radix-tree.h>
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#include <linux/workqueue.h>
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#include <linux/interrupt.h>
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#include <linux/thermal.h>
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#include <linux/mlx5/device.h>
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#include <linux/mlx5/doorbell.h>
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#include <linux/mlx5/srq.h>
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enum {
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MLX5_BOARD_ID_LEN = 64,
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MLX5_MAX_NAME_LEN = 16,
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};
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enum {
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/* one minute for the sake of bringup. Generally, commands must always
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* complete and we may need to increase this timeout value
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*/
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MLX5_CMD_TIMEOUT_MSEC = 60 * 1000,
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MLX5_CMD_WQ_MAX_NAME = 32,
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};
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enum {
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CMD_OWNER_SW = 0x0,
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CMD_OWNER_HW = 0x1,
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CMD_STATUS_SUCCESS = 0,
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};
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enum mlx5_sqp_t {
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MLX5_SQP_SMI = 0,
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MLX5_SQP_GSI = 1,
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MLX5_SQP_IEEE_1588 = 2,
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MLX5_SQP_SNIFFER = 3,
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MLX5_SQP_SYNC_UMR = 4,
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};
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enum {
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MLX5_MAX_PORTS = 2,
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};
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enum {
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MLX5_EQ_VEC_PAGES = 0,
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MLX5_EQ_VEC_CMD = 1,
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MLX5_EQ_VEC_ASYNC = 2,
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MLX5_EQ_VEC_COMP_BASE,
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};
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enum {
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MLX5_MAX_IRQ_NAME = 32
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};
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enum {
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MLX5_ATOMIC_MODE_IB_COMP = 1 << 16,
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MLX5_ATOMIC_MODE_CX = 2 << 16,
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MLX5_ATOMIC_MODE_8B = 3 << 16,
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MLX5_ATOMIC_MODE_16B = 4 << 16,
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MLX5_ATOMIC_MODE_32B = 5 << 16,
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MLX5_ATOMIC_MODE_64B = 6 << 16,
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MLX5_ATOMIC_MODE_128B = 7 << 16,
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MLX5_ATOMIC_MODE_256B = 8 << 16,
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};
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enum {
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MLX5_REG_QETCR = 0x4005,
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MLX5_REG_QTCT = 0x400a,
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MLX5_REG_PCAP = 0x5001,
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MLX5_REG_PMTU = 0x5003,
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MLX5_REG_PTYS = 0x5004,
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MLX5_REG_PAOS = 0x5006,
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MLX5_REG_PFCC = 0x5007,
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MLX5_REG_PPCNT = 0x5008,
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MLX5_REG_PMAOS = 0x5012,
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MLX5_REG_PUDE = 0x5009,
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MLX5_REG_PMPE = 0x5010,
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MLX5_REG_PELC = 0x500e,
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MLX5_REG_PVLC = 0x500f,
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MLX5_REG_PCMR = 0x5041,
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MLX5_REG_PMLP = 0x5002,
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MLX5_REG_NODE_DESC = 0x6001,
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MLX5_REG_HOST_ENDIANNESS = 0x7004,
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MLX5_REG_MTMP = 0x900A,
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MLX5_REG_MCIA = 0x9014,
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MLX5_REG_MLCR = 0x902b,
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};
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enum {
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MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0,
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MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1,
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};
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enum mlx5_page_fault_resume_flags {
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MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
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MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1,
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MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2,
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MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7,
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};
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enum dbg_rsc_type {
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MLX5_DBG_RSC_QP,
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MLX5_DBG_RSC_EQ,
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MLX5_DBG_RSC_CQ,
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};
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struct mlx5_field_desc {
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struct dentry *dent;
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int i;
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};
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struct mlx5_rsc_debug {
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struct mlx5_core_dev *dev;
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void *object;
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enum dbg_rsc_type type;
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struct dentry *root;
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struct mlx5_field_desc fields[0];
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};
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enum mlx5_dev_event {
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MLX5_DEV_EVENT_SYS_ERROR,
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MLX5_DEV_EVENT_PORT_UP,
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MLX5_DEV_EVENT_PORT_DOWN,
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MLX5_DEV_EVENT_PORT_INITIALIZED,
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MLX5_DEV_EVENT_LID_CHANGE,
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MLX5_DEV_EVENT_PKEY_CHANGE,
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MLX5_DEV_EVENT_GUID_CHANGE,
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MLX5_DEV_EVENT_CLIENT_REREG,
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};
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enum mlx5_port_status {
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MLX5_PORT_UP = 1,
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MLX5_PORT_DOWN = 2,
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};
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struct mlx5_uuar_info {
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struct mlx5_uar *uars;
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int num_uars;
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int num_low_latency_uuars;
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unsigned long *bitmap;
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unsigned int *count;
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struct mlx5_bf *bfs;
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/*
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* protect uuar allocation data structs
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*/
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struct mutex lock;
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u32 ver;
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};
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struct mlx5_bf {
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void __iomem *reg;
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void __iomem *regreg;
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int buf_size;
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struct mlx5_uar *uar;
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unsigned long offset;
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int need_lock;
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/* protect blue flame buffer selection when needed
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*/
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spinlock_t lock;
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/* serialize 64 bit writes when done as two 32 bit accesses
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*/
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spinlock_t lock32;
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int uuarn;
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};
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struct mlx5_cmd_first {
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__be32 data[4];
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};
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struct mlx5_cmd_msg {
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struct list_head list;
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struct cache_ent *cache;
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u32 len;
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struct mlx5_cmd_first first;
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struct mlx5_cmd_mailbox *next;
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};
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struct mlx5_cmd_debug {
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struct dentry *dbg_root;
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struct dentry *dbg_in;
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struct dentry *dbg_out;
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struct dentry *dbg_outlen;
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struct dentry *dbg_status;
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struct dentry *dbg_run;
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void *in_msg;
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void *out_msg;
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u8 status;
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u16 inlen;
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u16 outlen;
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};
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struct cache_ent {
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/* protect block chain allocations
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*/
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spinlock_t lock;
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struct list_head head;
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};
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struct cmd_msg_cache {
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struct cache_ent large;
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struct cache_ent med;
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};
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struct mlx5_cmd_stats {
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u64 sum;
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u64 n;
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struct dentry *root;
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struct dentry *avg;
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struct dentry *count;
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/* protect command average calculations */
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spinlock_t lock;
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};
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struct mlx5_cmd {
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void *cmd_alloc_buf;
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dma_addr_t alloc_dma;
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int alloc_size;
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void *cmd_buf;
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dma_addr_t dma;
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u16 cmdif_rev;
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u8 log_sz;
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u8 log_stride;
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int max_reg_cmds;
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int events;
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u32 __iomem *vector;
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/* protect command queue allocations
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*/
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spinlock_t alloc_lock;
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/* protect token allocations
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*/
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spinlock_t token_lock;
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u8 token;
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unsigned long bitmask;
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char wq_name[MLX5_CMD_WQ_MAX_NAME];
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struct workqueue_struct *wq;
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struct semaphore sem;
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struct semaphore pages_sem;
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int mode;
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struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
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struct pci_pool *pool;
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struct mlx5_cmd_debug dbg;
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struct cmd_msg_cache cache;
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int checksum_disabled;
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struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
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};
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struct mlx5_port_caps {
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int gid_table_len;
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int pkey_table_len;
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u8 ext_port_cap;
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};
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struct mlx5_cmd_mailbox {
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void *buf;
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dma_addr_t dma;
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struct mlx5_cmd_mailbox *next;
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};
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struct mlx5_buf_list {
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void *buf;
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dma_addr_t map;
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};
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struct mlx5_buf {
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struct mlx5_buf_list direct;
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int npages;
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int size;
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u8 page_shift;
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};
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struct mlx5_eq_tasklet {
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struct list_head list;
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struct list_head process_list;
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struct tasklet_struct task;
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/* lock on completion tasklet list */
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spinlock_t lock;
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};
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struct mlx5_eq {
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struct mlx5_core_dev *dev;
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__be32 __iomem *doorbell;
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u32 cons_index;
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struct mlx5_buf buf;
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int size;
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unsigned int irqn;
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u8 eqn;
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int nent;
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u64 mask;
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struct list_head list;
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int index;
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struct mlx5_rsc_debug *dbg;
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struct mlx5_eq_tasklet tasklet_ctx;
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};
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struct mlx5_core_psv {
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u32 psv_idx;
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struct psv_layout {
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u32 pd;
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u16 syndrome;
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u16 reserved;
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u16 bg;
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u16 app_tag;
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u32 ref_tag;
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} psv;
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};
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struct mlx5_core_sig_ctx {
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struct mlx5_core_psv psv_memory;
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struct mlx5_core_psv psv_wire;
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struct ib_sig_err err_item;
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bool sig_status_checked;
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bool sig_err_exists;
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u32 sigerr_count;
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};
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struct mlx5_core_mkey {
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u64 iova;
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u64 size;
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u32 key;
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u32 pd;
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};
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enum mlx5_res_type {
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MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP,
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MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ,
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MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ,
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MLX5_RES_SRQ = 3,
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MLX5_RES_XSRQ = 4,
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};
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struct mlx5_core_rsc_common {
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enum mlx5_res_type res;
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atomic_t refcount;
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struct completion free;
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};
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struct mlx5_core_srq {
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struct mlx5_core_rsc_common common; /* must be first */
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u32 srqn;
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int max;
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size_t max_gs;
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size_t max_avail_gather;
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int wqe_shift;
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void (*event) (struct mlx5_core_srq *, enum mlx5_event);
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atomic_t refcount;
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struct completion free;
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};
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struct mlx5_eq_table {
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void __iomem *update_ci;
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void __iomem *update_arm_ci;
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struct list_head comp_eqs_list;
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struct mlx5_eq pages_eq;
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struct mlx5_eq async_eq;
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struct mlx5_eq cmd_eq;
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int num_comp_vectors;
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/* protect EQs list
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*/
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spinlock_t lock;
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};
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struct mlx5_uar {
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u32 index;
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struct list_head bf_list;
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unsigned free_bf_bmap;
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void __iomem *bf_map;
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void __iomem *map;
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};
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struct mlx5_core_health {
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struct health_buffer __iomem *health;
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__be32 __iomem *health_counter;
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struct timer_list timer;
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u32 prev;
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int miss_counter;
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bool sick;
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/* wq spinlock to synchronize draining */
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spinlock_t wq_lock;
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struct workqueue_struct *wq;
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unsigned long flags;
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struct work_struct work;
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struct delayed_work recover_work;
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};
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struct mlx5_cq_table {
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/* protect radix tree
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*/
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spinlock_t lock;
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struct radix_tree_root tree;
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};
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struct mlx5_qp_table {
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/* protect radix tree
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*/
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spinlock_t lock;
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struct radix_tree_root tree;
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};
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struct mlx5_srq_table {
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/* protect radix tree
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*/
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spinlock_t lock;
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struct radix_tree_root tree;
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};
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struct mlx5_mkey_table {
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/* protect radix tree
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*/
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rwlock_t lock;
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struct radix_tree_root tree;
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};
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struct mlx5_vf_context {
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int enabled;
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};
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struct mlx5_core_sriov {
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struct mlx5_vf_context *vfs_ctx;
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int num_vfs;
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int enabled_vfs;
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};
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struct mlx5_irq_info {
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cpumask_var_t mask;
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char name[MLX5_MAX_IRQ_NAME];
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};
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struct mlx5_fc_stats {
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struct rb_root counters;
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struct list_head addlist;
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/* protect addlist add/splice operations */
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spinlock_t addlist_lock;
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struct workqueue_struct *wq;
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struct delayed_work work;
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unsigned long next_query;
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};
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struct mlx5_eswitch;
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struct mlx5_lag;
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struct mlx5_rl_entry {
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u32 rate;
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u16 index;
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u16 refcount;
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};
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struct mlx5_rl_table {
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/* protect rate limit table */
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struct mutex rl_lock;
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u16 max_size;
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u32 max_rate;
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u32 min_rate;
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struct mlx5_rl_entry *rl_entry;
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};
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struct mlx5_priv {
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char name[MLX5_MAX_NAME_LEN];
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struct mlx5_eq_table eq_table;
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struct msix_entry *msix_arr;
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struct mlx5_irq_info *irq_info;
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struct mlx5_uuar_info uuari;
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MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock);
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/* pages stuff */
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struct workqueue_struct *pg_wq;
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struct rb_root page_root;
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int fw_pages;
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atomic_t reg_pages;
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struct list_head free_list;
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int vfs_pages;
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struct mlx5_core_health health;
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struct mlx5_srq_table srq_table;
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/* start: qp staff */
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struct mlx5_qp_table qp_table;
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struct dentry *qp_debugfs;
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struct dentry *eq_debugfs;
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struct dentry *cq_debugfs;
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struct dentry *cmdif_debugfs;
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/* end: qp staff */
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/* start: cq staff */
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struct mlx5_cq_table cq_table;
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/* end: cq staff */
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/* start: mkey staff */
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struct mlx5_mkey_table mkey_table;
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/* end: mkey staff */
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/* start: alloc staff */
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/* protect buffer alocation according to numa node */
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struct mutex alloc_mutex;
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int numa_node;
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struct mutex pgdir_mutex;
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struct list_head pgdir_list;
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/* end: alloc staff */
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struct dentry *dbg_root;
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/* protect mkey key part */
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spinlock_t mkey_lock;
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u8 mkey_key;
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|
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struct list_head dev_list;
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struct list_head ctx_list;
|
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spinlock_t ctx_lock;
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|
|
struct mlx5_flow_steering *steering;
|
|
struct mlx5_eswitch *eswitch;
|
|
struct mlx5_core_sriov sriov;
|
|
struct mlx5_lag *lag;
|
|
unsigned long pci_dev_data;
|
|
struct mlx5_fc_stats fc_stats;
|
|
struct mlx5_rl_table rl_table;
|
|
};
|
|
|
|
enum mlx5_device_state {
|
|
MLX5_DEVICE_STATE_UP,
|
|
MLX5_DEVICE_STATE_INTERNAL_ERROR,
|
|
};
|
|
|
|
enum mlx5_interface_state {
|
|
MLX5_INTERFACE_STATE_DOWN = BIT(0),
|
|
MLX5_INTERFACE_STATE_UP = BIT(1),
|
|
MLX5_INTERFACE_STATE_SHUTDOWN = BIT(2),
|
|
};
|
|
|
|
enum mlx5_pci_status {
|
|
MLX5_PCI_STATUS_DISABLED,
|
|
MLX5_PCI_STATUS_ENABLED,
|
|
};
|
|
|
|
struct mlx5_td {
|
|
/* protects tirs list changes while tirs refresh */
|
|
struct mutex list_lock;
|
|
struct list_head tirs_list;
|
|
u32 tdn;
|
|
};
|
|
|
|
struct mlx5e_resources {
|
|
struct mlx5_uar cq_uar;
|
|
u32 pdn;
|
|
struct mlx5_td td;
|
|
struct mlx5_core_mkey mkey;
|
|
};
|
|
|
|
struct mlx5_thermal;
|
|
struct mlx5_core_dev {
|
|
struct pci_dev *pdev;
|
|
/* sync pci state */
|
|
struct mutex pci_status_mutex;
|
|
enum mlx5_pci_status pci_status;
|
|
u8 rev_id;
|
|
char board_id[MLX5_BOARD_ID_LEN];
|
|
struct mlx5_cmd cmd;
|
|
struct mlx5_port_caps port_caps[MLX5_MAX_PORTS];
|
|
u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
|
|
u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
|
|
phys_addr_t iseg_base;
|
|
struct mlx5_init_seg __iomem *iseg;
|
|
enum mlx5_device_state state;
|
|
/* sync interface state */
|
|
struct mutex intf_state_mutex;
|
|
unsigned long intf_state;
|
|
void (*event) (struct mlx5_core_dev *dev,
|
|
enum mlx5_dev_event event,
|
|
unsigned long param);
|
|
struct mlx5_priv priv;
|
|
struct mlx5_profile *profile;
|
|
atomic_t num_qps;
|
|
u32 issi;
|
|
struct mlx5e_resources mlx5e_res;
|
|
#ifdef CONFIG_RFS_ACCEL
|
|
struct cpu_rmap *rmap;
|
|
#endif
|
|
struct mlx5_thermal *thermal;
|
|
|
|
};
|
|
|
|
struct mlx5_db {
|
|
__be32 *db;
|
|
union {
|
|
struct mlx5_db_pgdir *pgdir;
|
|
struct mlx5_ib_user_db_page *user_page;
|
|
} u;
|
|
dma_addr_t dma;
|
|
int index;
|
|
};
|
|
|
|
enum {
|
|
MLX5_COMP_EQ_SIZE = 1024,
|
|
};
|
|
|
|
enum {
|
|
MLX5_PTYS_IB = 1 << 0,
|
|
MLX5_PTYS_EN = 1 << 2,
|
|
};
|
|
|
|
typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
|
|
|
|
enum {
|
|
MLX5_CMD_ENT_STATE_PENDING_COMP,
|
|
};
|
|
|
|
struct mlx5_cmd_work_ent {
|
|
unsigned long state;
|
|
struct mlx5_cmd_msg *in;
|
|
struct mlx5_cmd_msg *out;
|
|
void *uout;
|
|
int uout_size;
|
|
mlx5_cmd_cbk_t callback;
|
|
struct delayed_work cb_timeout_work;
|
|
void *context;
|
|
int idx;
|
|
struct completion handling;
|
|
struct completion done;
|
|
struct mlx5_cmd *cmd;
|
|
struct work_struct work;
|
|
struct mlx5_cmd_layout *lay;
|
|
int ret;
|
|
int page_queue;
|
|
u8 status;
|
|
u8 token;
|
|
u64 ts1;
|
|
u64 ts2;
|
|
u16 op;
|
|
};
|
|
|
|
struct mlx5_pas {
|
|
u64 pa;
|
|
u8 log_sz;
|
|
};
|
|
|
|
enum port_state_policy {
|
|
MLX5_POLICY_DOWN = 0,
|
|
MLX5_POLICY_UP = 1,
|
|
MLX5_POLICY_FOLLOW = 2,
|
|
MLX5_POLICY_INVALID = 0xffffffff
|
|
};
|
|
|
|
enum phy_port_state {
|
|
MLX5_AAA_111
|
|
};
|
|
|
|
struct mlx5_hca_vport_context {
|
|
u32 field_select;
|
|
bool sm_virt_aware;
|
|
bool has_smi;
|
|
bool has_raw;
|
|
enum port_state_policy policy;
|
|
enum phy_port_state phys_state;
|
|
enum ib_port_state vport_state;
|
|
u8 port_physical_state;
|
|
u64 sys_image_guid;
|
|
u64 port_guid;
|
|
u64 node_guid;
|
|
u32 cap_mask1;
|
|
u32 cap_mask1_perm;
|
|
u32 cap_mask2;
|
|
u32 cap_mask2_perm;
|
|
u16 lid;
|
|
u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
|
|
u8 lmc;
|
|
u8 subnet_timeout;
|
|
u16 sm_lid;
|
|
u8 sm_sl;
|
|
u16 qkey_violation_counter;
|
|
u16 pkey_violation_counter;
|
|
bool grh_required;
|
|
};
|
|
|
|
static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset)
|
|
{
|
|
return buf->direct.buf + offset;
|
|
}
|
|
|
|
extern struct workqueue_struct *mlx5_core_wq;
|
|
|
|
#define STRUCT_FIELD(header, field) \
|
|
.struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
|
|
.struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
|
|
|
|
static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
|
|
{
|
|
return pci_get_drvdata(pdev);
|
|
}
|
|
|
|
extern struct dentry *mlx5_debugfs_root;
|
|
|
|
static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
|
|
{
|
|
return ioread32be(&dev->iseg->fw_rev) & 0xffff;
|
|
}
|
|
|
|
static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
|
|
{
|
|
return ioread32be(&dev->iseg->fw_rev) >> 16;
|
|
}
|
|
|
|
static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
|
|
{
|
|
return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
|
|
}
|
|
|
|
static inline u16 cmdif_rev(struct mlx5_core_dev *dev)
|
|
{
|
|
return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
|
|
}
|
|
|
|
static inline void *mlx5_vzalloc(unsigned long size)
|
|
{
|
|
void *rtn;
|
|
|
|
rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
|
|
if (!rtn)
|
|
rtn = vzalloc(size);
|
|
return rtn;
|
|
}
|
|
|
|
static inline u32 mlx5_base_mkey(const u32 key)
|
|
{
|
|
return key & 0xffffff00u;
|
|
}
|
|
|
|
int mlx5_cmd_init(struct mlx5_core_dev *dev);
|
|
void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
|
|
void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
|
|
void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
|
|
|
|
int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
|
|
int out_size);
|
|
int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
|
|
void *out, int out_size, mlx5_cmd_cbk_t callback,
|
|
void *context);
|
|
void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome);
|
|
|
|
int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
|
|
int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
|
|
int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
|
|
int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
|
|
int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
|
|
int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar,
|
|
bool map_wc);
|
|
void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
|
|
void mlx5_health_cleanup(struct mlx5_core_dev *dev);
|
|
int mlx5_health_init(struct mlx5_core_dev *dev);
|
|
void mlx5_start_health_poll(struct mlx5_core_dev *dev);
|
|
void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
|
|
void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
|
|
void mlx5_drain_health_recovery(struct mlx5_core_dev *dev);
|
|
int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size,
|
|
struct mlx5_buf *buf, int node);
|
|
int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, struct mlx5_buf *buf);
|
|
void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
|
|
struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
|
|
gfp_t flags, int npages);
|
|
void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
|
|
struct mlx5_cmd_mailbox *head);
|
|
int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
|
|
struct mlx5_srq_attr *in);
|
|
int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
|
|
int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
|
|
struct mlx5_srq_attr *out);
|
|
int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
|
|
u16 lwm, int is_srq);
|
|
void mlx5_init_mkey_table(struct mlx5_core_dev *dev);
|
|
void mlx5_cleanup_mkey_table(struct mlx5_core_dev *dev);
|
|
int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev,
|
|
struct mlx5_core_mkey *mkey,
|
|
u32 *in, int inlen,
|
|
u32 *out, int outlen,
|
|
mlx5_cmd_cbk_t callback, void *context);
|
|
int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
|
|
struct mlx5_core_mkey *mkey,
|
|
u32 *in, int inlen);
|
|
int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev,
|
|
struct mlx5_core_mkey *mkey);
|
|
int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey,
|
|
u32 *out, int outlen);
|
|
int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *_mkey,
|
|
u32 *mkey);
|
|
int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
|
|
int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
|
|
int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
|
|
u16 opmod, u8 port);
|
|
void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
|
|
void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
|
|
int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
|
|
void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
|
|
void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
|
|
s32 npages);
|
|
int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
|
|
int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
|
|
void mlx5_register_debugfs(void);
|
|
void mlx5_unregister_debugfs(void);
|
|
int mlx5_eq_init(struct mlx5_core_dev *dev);
|
|
void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
|
|
void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
|
|
void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn);
|
|
void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
|
|
#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
|
|
void mlx5_eq_pagefault(struct mlx5_core_dev *dev, struct mlx5_eqe *eqe);
|
|
#endif
|
|
void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
|
|
struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
|
|
void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced);
|
|
void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
|
|
int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
|
|
int nent, u64 mask, const char *name, struct mlx5_uar *uar);
|
|
int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
|
|
int mlx5_start_eqs(struct mlx5_core_dev *dev);
|
|
int mlx5_stop_eqs(struct mlx5_core_dev *dev);
|
|
int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
|
|
unsigned int *irqn);
|
|
int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
|
|
int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
|
|
|
|
int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
|
|
void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
|
|
int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
|
|
int size_in, void *data_out, int size_out,
|
|
u16 reg_num, int arg, int write);
|
|
|
|
int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
|
|
void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
|
|
int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
|
|
u32 *out, int outlen);
|
|
int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
|
|
void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
|
|
int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
|
|
void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
|
|
int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
|
|
int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
|
|
int node);
|
|
void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
|
|
|
|
const char *mlx5_command_str(int command);
|
|
int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
|
|
void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
|
|
int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
|
|
int npsvs, u32 *sig_index);
|
|
int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
|
|
void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
|
|
int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
|
|
struct mlx5_odp_caps *odp_caps);
|
|
int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
|
|
u8 port_num, void *out, size_t sz);
|
|
|
|
int mlx5_init_rl_table(struct mlx5_core_dev *dev);
|
|
void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
|
|
int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u32 rate, u16 *index);
|
|
void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, u32 rate);
|
|
bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
|
|
|
|
static inline int fw_initializing(struct mlx5_core_dev *dev)
|
|
{
|
|
return ioread32be(&dev->iseg->initializing) >> 31;
|
|
}
|
|
|
|
static inline u32 mlx5_mkey_to_idx(u32 mkey)
|
|
{
|
|
return mkey >> 8;
|
|
}
|
|
|
|
static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
|
|
{
|
|
return mkey_idx << 8;
|
|
}
|
|
|
|
static inline u8 mlx5_mkey_variant(u32 mkey)
|
|
{
|
|
return mkey & 0xff;
|
|
}
|
|
|
|
enum {
|
|
MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
|
|
MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
|
|
};
|
|
|
|
enum {
|
|
MAX_MR_CACHE_ENTRIES = 16,
|
|
};
|
|
|
|
enum {
|
|
MLX5_INTERFACE_PROTOCOL_IB = 0,
|
|
MLX5_INTERFACE_PROTOCOL_ETH = 1,
|
|
};
|
|
|
|
struct mlx5_interface {
|
|
void * (*add)(struct mlx5_core_dev *dev);
|
|
void (*remove)(struct mlx5_core_dev *dev, void *context);
|
|
int (*attach)(struct mlx5_core_dev *dev, void *context);
|
|
void (*detach)(struct mlx5_core_dev *dev, void *context);
|
|
void (*event)(struct mlx5_core_dev *dev, void *context,
|
|
enum mlx5_dev_event event, unsigned long param);
|
|
void * (*get_dev)(void *context);
|
|
int protocol;
|
|
struct list_head list;
|
|
};
|
|
|
|
void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
|
|
int mlx5_register_interface(struct mlx5_interface *intf);
|
|
void mlx5_unregister_interface(struct mlx5_interface *intf);
|
|
int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
|
|
|
|
int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
|
|
int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
|
|
bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
|
|
struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev);
|
|
|
|
struct mlx5_profile {
|
|
u64 mask;
|
|
u8 log_max_qp;
|
|
struct {
|
|
int size;
|
|
int limit;
|
|
} mr_cache[MAX_MR_CACHE_ENTRIES];
|
|
};
|
|
|
|
enum {
|
|
MLX5_PCI_DEV_IS_VF = 1 << 0,
|
|
};
|
|
|
|
static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev)
|
|
{
|
|
return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF);
|
|
}
|
|
|
|
static inline int mlx5_get_gid_table_len(u16 param)
|
|
{
|
|
if (param > 4) {
|
|
pr_warn("gid table length is zero\n");
|
|
return 0;
|
|
}
|
|
|
|
return 8 * (1 << param);
|
|
}
|
|
|
|
static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
|
|
{
|
|
return !!(dev->priv.rl_table.max_size);
|
|
}
|
|
|
|
enum {
|
|
MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
|
|
};
|
|
|
|
struct mlx5_thermal {
|
|
struct mlx5_core_dev *core;
|
|
struct thermal_zone_device *tzdev;
|
|
enum thermal_device_mode mode;
|
|
};
|
|
|
|
#ifdef CONFIG_MLX5_CORE_THERMAL
|
|
int mlx5_thermal_init(struct mlx5_core_dev *core);
|
|
void mlx5_thermal_deinit(struct mlx5_core_dev *core);
|
|
#else
|
|
static inline int mlx5_thermal_init(struct mlx5_core_dev *core)
|
|
{
|
|
core->thermal = NULL;
|
|
return 0;
|
|
}
|
|
|
|
static inline void mlx5_thermal_deinit(struct mlx5_core_dev *core)
|
|
{
|
|
}
|
|
#endif
|
|
|
|
#endif /* MLX5_DRIVER_H */
|