813 lines
27 KiB
C
813 lines
27 KiB
C
/*
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* Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
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*
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* Authors: Shlomi Gridish <gridish@freescale.com>
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* Li Yang <leoli@freescale.com>
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*
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* Description:
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* QUICC Engine (QE) external definitions and structure.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef _ASM_POWERPC_QE_H
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#define _ASM_POWERPC_QE_H
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#ifdef __KERNEL__
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#include <linux/compiler.h>
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#include <linux/genalloc.h>
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#include <linux/spinlock.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <asm/cpm.h>
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#include <soc/fsl/qe/immap_qe.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/types.h>
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#define QE_NUM_OF_SNUM 256 /* There are 256 serial number in QE */
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#define QE_NUM_OF_BRGS 16
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#define QE_NUM_OF_PORTS 1024
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/* Memory partitions
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*/
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#define MEM_PART_SYSTEM 0
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#define MEM_PART_SECONDARY 1
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#define MEM_PART_MURAM 2
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/* Clocks and BRGs */
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enum qe_clock {
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QE_CLK_NONE = 0,
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QE_BRG1, /* Baud Rate Generator 1 */
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QE_BRG2, /* Baud Rate Generator 2 */
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QE_BRG3, /* Baud Rate Generator 3 */
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QE_BRG4, /* Baud Rate Generator 4 */
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QE_BRG5, /* Baud Rate Generator 5 */
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QE_BRG6, /* Baud Rate Generator 6 */
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QE_BRG7, /* Baud Rate Generator 7 */
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QE_BRG8, /* Baud Rate Generator 8 */
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QE_BRG9, /* Baud Rate Generator 9 */
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QE_BRG10, /* Baud Rate Generator 10 */
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QE_BRG11, /* Baud Rate Generator 11 */
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QE_BRG12, /* Baud Rate Generator 12 */
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QE_BRG13, /* Baud Rate Generator 13 */
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QE_BRG14, /* Baud Rate Generator 14 */
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QE_BRG15, /* Baud Rate Generator 15 */
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QE_BRG16, /* Baud Rate Generator 16 */
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QE_CLK1, /* Clock 1 */
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QE_CLK2, /* Clock 2 */
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QE_CLK3, /* Clock 3 */
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QE_CLK4, /* Clock 4 */
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QE_CLK5, /* Clock 5 */
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QE_CLK6, /* Clock 6 */
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QE_CLK7, /* Clock 7 */
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QE_CLK8, /* Clock 8 */
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QE_CLK9, /* Clock 9 */
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QE_CLK10, /* Clock 10 */
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QE_CLK11, /* Clock 11 */
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QE_CLK12, /* Clock 12 */
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QE_CLK13, /* Clock 13 */
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QE_CLK14, /* Clock 14 */
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QE_CLK15, /* Clock 15 */
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QE_CLK16, /* Clock 16 */
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QE_CLK17, /* Clock 17 */
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QE_CLK18, /* Clock 18 */
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QE_CLK19, /* Clock 19 */
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QE_CLK20, /* Clock 20 */
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QE_CLK21, /* Clock 21 */
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QE_CLK22, /* Clock 22 */
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QE_CLK23, /* Clock 23 */
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QE_CLK24, /* Clock 24 */
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QE_RSYNC_PIN, /* RSYNC from pin */
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QE_TSYNC_PIN, /* TSYNC from pin */
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QE_CLK_DUMMY
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};
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static inline bool qe_clock_is_brg(enum qe_clock clk)
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{
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return clk >= QE_BRG1 && clk <= QE_BRG16;
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}
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extern spinlock_t cmxgcr_lock;
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/* Export QE common operations */
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#ifdef CONFIG_QUICC_ENGINE
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extern void qe_reset(void);
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#else
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static inline void qe_reset(void) {}
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#endif
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int cpm_muram_init(void);
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#if defined(CONFIG_CPM) || defined(CONFIG_QUICC_ENGINE)
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unsigned long cpm_muram_alloc(unsigned long size, unsigned long align);
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int cpm_muram_free(unsigned long offset);
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unsigned long cpm_muram_alloc_fixed(unsigned long offset, unsigned long size);
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void __iomem *cpm_muram_addr(unsigned long offset);
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unsigned long cpm_muram_offset(void __iomem *addr);
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dma_addr_t cpm_muram_dma(void __iomem *addr);
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#else
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static inline unsigned long cpm_muram_alloc(unsigned long size,
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unsigned long align)
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{
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return -ENOSYS;
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}
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static inline int cpm_muram_free(unsigned long offset)
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{
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return -ENOSYS;
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}
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static inline unsigned long cpm_muram_alloc_fixed(unsigned long offset,
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unsigned long size)
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{
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return -ENOSYS;
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}
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static inline void __iomem *cpm_muram_addr(unsigned long offset)
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{
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return NULL;
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}
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static inline unsigned long cpm_muram_offset(void __iomem *addr)
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{
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return -ENOSYS;
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}
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static inline dma_addr_t cpm_muram_dma(void __iomem *addr)
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{
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return 0;
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}
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#endif /* defined(CONFIG_CPM) || defined(CONFIG_QUICC_ENGINE) */
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/* QE PIO */
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#define QE_PIO_PINS 32
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struct qe_pio_regs {
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__be32 cpodr; /* Open drain register */
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__be32 cpdata; /* Data register */
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__be32 cpdir1; /* Direction register */
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__be32 cpdir2; /* Direction register */
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__be32 cppar1; /* Pin assignment register */
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__be32 cppar2; /* Pin assignment register */
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#ifdef CONFIG_PPC_85xx
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u8 pad[8];
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#endif
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};
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#define QE_PIO_DIR_IN 2
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#define QE_PIO_DIR_OUT 1
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extern void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin,
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int dir, int open_drain, int assignment,
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int has_irq);
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#ifdef CONFIG_QUICC_ENGINE
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extern int par_io_init(struct device_node *np);
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extern int par_io_of_config(struct device_node *np);
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extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
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int assignment, int has_irq);
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extern int par_io_data_set(u8 port, u8 pin, u8 val);
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#else
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static inline int par_io_init(struct device_node *np) { return -ENOSYS; }
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static inline int par_io_of_config(struct device_node *np) { return -ENOSYS; }
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static inline int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
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int assignment, int has_irq) { return -ENOSYS; }
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static inline int par_io_data_set(u8 port, u8 pin, u8 val) { return -ENOSYS; }
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#endif /* CONFIG_QUICC_ENGINE */
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/*
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* Pin multiplexing functions.
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*/
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struct qe_pin;
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#ifdef CONFIG_QE_GPIO
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extern struct qe_pin *qe_pin_request(struct device_node *np, int index);
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extern void qe_pin_free(struct qe_pin *qe_pin);
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extern void qe_pin_set_gpio(struct qe_pin *qe_pin);
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extern void qe_pin_set_dedicated(struct qe_pin *pin);
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#else
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static inline struct qe_pin *qe_pin_request(struct device_node *np, int index)
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{
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return ERR_PTR(-ENOSYS);
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}
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static inline void qe_pin_free(struct qe_pin *qe_pin) {}
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static inline void qe_pin_set_gpio(struct qe_pin *qe_pin) {}
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static inline void qe_pin_set_dedicated(struct qe_pin *pin) {}
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#endif /* CONFIG_QE_GPIO */
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#ifdef CONFIG_QUICC_ENGINE
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int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input);
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#else
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static inline int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol,
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u32 cmd_input)
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{
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return -ENOSYS;
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}
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#endif /* CONFIG_QUICC_ENGINE */
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/* QE internal API */
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enum qe_clock qe_clock_source(const char *source);
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unsigned int qe_get_brg_clk(void);
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int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier);
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int qe_get_snum(void);
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void qe_put_snum(u8 snum);
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unsigned int qe_get_num_of_risc(void);
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unsigned int qe_get_num_of_snums(void);
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static inline int qe_alive_during_sleep(void)
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{
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/*
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* MPC8568E reference manual says:
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*
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* "...power down sequence waits for all I/O interfaces to become idle.
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* In some applications this may happen eventually without actively
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* shutting down interfaces, but most likely, software will have to
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* take steps to shut down the eTSEC, QUICC Engine Block, and PCI
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* interfaces before issuing the command (either the write to the core
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* MSR[WE] as described above or writing to POWMGTCSR) to put the
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* device into sleep state."
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*
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* MPC8569E reference manual has a similar paragraph.
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*/
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#ifdef CONFIG_PPC_85xx
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return 0;
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#else
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return 1;
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#endif
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}
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/* we actually use cpm_muram implementation, define this for convenience */
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#define qe_muram_init cpm_muram_init
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#define qe_muram_alloc cpm_muram_alloc
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#define qe_muram_alloc_fixed cpm_muram_alloc_fixed
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#define qe_muram_free cpm_muram_free
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#define qe_muram_addr cpm_muram_addr
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#define qe_muram_offset cpm_muram_offset
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#define qe_muram_dma cpm_muram_dma
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#define qe_setbits32(_addr, _v) iowrite32be(ioread32be(_addr) | (_v), (_addr))
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#define qe_clrbits32(_addr, _v) iowrite32be(ioread32be(_addr) & ~(_v), (_addr))
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#define qe_setbits16(_addr, _v) iowrite16be(ioread16be(_addr) | (_v), (_addr))
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#define qe_clrbits16(_addr, _v) iowrite16be(ioread16be(_addr) & ~(_v), (_addr))
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#define qe_setbits8(_addr, _v) iowrite8(ioread8(_addr) | (_v), (_addr))
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#define qe_clrbits8(_addr, _v) iowrite8(ioread8(_addr) & ~(_v), (_addr))
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#define qe_clrsetbits32(addr, clear, set) \
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iowrite32be((ioread32be(addr) & ~(clear)) | (set), (addr))
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#define qe_clrsetbits16(addr, clear, set) \
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iowrite16be((ioread16be(addr) & ~(clear)) | (set), (addr))
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#define qe_clrsetbits8(addr, clear, set) \
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iowrite8((ioread8(addr) & ~(clear)) | (set), (addr))
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/* Structure that defines QE firmware binary files.
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*
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* See Documentation/powerpc/qe_firmware.txt for a description of these
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* fields.
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*/
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struct qe_firmware {
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struct qe_header {
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__be32 length; /* Length of the entire structure, in bytes */
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u8 magic[3]; /* Set to { 'Q', 'E', 'F' } */
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u8 version; /* Version of this layout. First ver is '1' */
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} header;
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u8 id[62]; /* Null-terminated identifier string */
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u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */
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u8 count; /* Number of microcode[] structures */
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struct {
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__be16 model; /* The SOC model */
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u8 major; /* The SOC revision major */
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u8 minor; /* The SOC revision minor */
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} __attribute__ ((packed)) soc;
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u8 padding[4]; /* Reserved, for alignment */
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__be64 extended_modes; /* Extended modes */
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__be32 vtraps[8]; /* Virtual trap addresses */
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u8 reserved[4]; /* Reserved, for future expansion */
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struct qe_microcode {
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u8 id[32]; /* Null-terminated identifier */
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__be32 traps[16]; /* Trap addresses, 0 == ignore */
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__be32 eccr; /* The value for the ECCR register */
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__be32 iram_offset; /* Offset into I-RAM for the code */
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__be32 count; /* Number of 32-bit words of the code */
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__be32 code_offset; /* Offset of the actual microcode */
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u8 major; /* The microcode version major */
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u8 minor; /* The microcode version minor */
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u8 revision; /* The microcode version revision */
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u8 padding; /* Reserved, for alignment */
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u8 reserved[4]; /* Reserved, for future expansion */
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} __attribute__ ((packed)) microcode[1];
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/* All microcode binaries should be located here */
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/* CRC32 should be located here, after the microcode binaries */
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} __attribute__ ((packed));
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struct qe_firmware_info {
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char id[64]; /* Firmware name */
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u32 vtraps[8]; /* Virtual trap addresses */
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u64 extended_modes; /* Extended modes */
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};
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#ifdef CONFIG_QUICC_ENGINE
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/* Upload a firmware to the QE */
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int qe_upload_firmware(const struct qe_firmware *firmware);
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#else
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static inline int qe_upload_firmware(const struct qe_firmware *firmware)
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{
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return -ENOSYS;
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}
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#endif /* CONFIG_QUICC_ENGINE */
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/* Obtain information on the uploaded firmware */
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struct qe_firmware_info *qe_get_firmware_info(void);
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/* QE USB */
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int qe_usb_clock_set(enum qe_clock clk, int rate);
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/* Buffer descriptors */
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struct qe_bd {
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__be16 status;
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__be16 length;
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__be32 buf;
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} __attribute__ ((packed));
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#define BD_STATUS_MASK 0xffff0000
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#define BD_LENGTH_MASK 0x0000ffff
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/* Alignment */
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#define QE_INTR_TABLE_ALIGN 16 /* ??? */
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#define QE_ALIGNMENT_OF_BD 8
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#define QE_ALIGNMENT_OF_PRAM 64
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/* RISC allocation */
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#define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */
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#define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */
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#define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */
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#define QE_RISC_ALLOCATION_RISC4 0x8 /* RISC 4 */
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#define QE_RISC_ALLOCATION_RISC1_AND_RISC2 (QE_RISC_ALLOCATION_RISC1 | \
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QE_RISC_ALLOCATION_RISC2)
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#define QE_RISC_ALLOCATION_FOUR_RISCS (QE_RISC_ALLOCATION_RISC1 | \
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QE_RISC_ALLOCATION_RISC2 | \
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QE_RISC_ALLOCATION_RISC3 | \
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QE_RISC_ALLOCATION_RISC4)
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/* QE extended filtering Table Lookup Key Size */
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enum qe_fltr_tbl_lookup_key_size {
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QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES
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= 0x3f, /* LookupKey parsed by the Generate LookupKey
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CMD is truncated to 8 bytes */
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QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES
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= 0x5f, /* LookupKey parsed by the Generate LookupKey
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CMD is truncated to 16 bytes */
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};
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/* QE FLTR extended filtering Largest External Table Lookup Key Size */
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enum qe_fltr_largest_external_tbl_lookup_key_size {
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QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE
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= 0x0,/* not used */
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QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES
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= QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES, /* 8 bytes */
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QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES
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= QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES, /* 16 bytes */
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};
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/* structure representing QE parameter RAM */
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struct qe_timer_tables {
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u16 tm_base; /* QE timer table base adr */
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u16 tm_ptr; /* QE timer table pointer */
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u16 r_tmr; /* QE timer mode register */
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u16 r_tmv; /* QE timer valid register */
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u32 tm_cmd; /* QE timer cmd register */
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u32 tm_cnt; /* QE timer internal cnt */
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} __attribute__ ((packed));
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#define QE_FLTR_TAD_SIZE 8
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/* QE extended filtering Termination Action Descriptor (TAD) */
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struct qe_fltr_tad {
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u8 serialized[QE_FLTR_TAD_SIZE];
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} __attribute__ ((packed));
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/* Communication Direction */
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enum comm_dir {
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COMM_DIR_NONE = 0,
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COMM_DIR_RX = 1,
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COMM_DIR_TX = 2,
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COMM_DIR_RX_AND_TX = 3
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};
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/* QE CMXUCR Registers.
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* There are two UCCs represented in each of the four CMXUCR registers.
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* These values are for the UCC in the LSBs
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*/
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#define QE_CMXUCR_MII_ENET_MNG 0x00007000
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#define QE_CMXUCR_MII_ENET_MNG_SHIFT 12
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#define QE_CMXUCR_GRANT 0x00008000
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#define QE_CMXUCR_TSA 0x00004000
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#define QE_CMXUCR_BKPT 0x00000100
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#define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F
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/* QE CMXGCR Registers.
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*/
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#define QE_CMXGCR_MII_ENET_MNG 0x00007000
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#define QE_CMXGCR_MII_ENET_MNG_SHIFT 12
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#define QE_CMXGCR_USBCS 0x0000000f
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#define QE_CMXGCR_USBCS_CLK3 0x1
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#define QE_CMXGCR_USBCS_CLK5 0x2
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#define QE_CMXGCR_USBCS_CLK7 0x3
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#define QE_CMXGCR_USBCS_CLK9 0x4
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#define QE_CMXGCR_USBCS_CLK13 0x5
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#define QE_CMXGCR_USBCS_CLK17 0x6
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#define QE_CMXGCR_USBCS_CLK19 0x7
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#define QE_CMXGCR_USBCS_CLK21 0x8
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#define QE_CMXGCR_USBCS_BRG9 0x9
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#define QE_CMXGCR_USBCS_BRG10 0xa
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/* QE CECR Commands.
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*/
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#define QE_CR_FLG 0x00010000
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#define QE_RESET 0x80000000
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#define QE_INIT_TX_RX 0x00000000
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#define QE_INIT_RX 0x00000001
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#define QE_INIT_TX 0x00000002
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#define QE_ENTER_HUNT_MODE 0x00000003
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#define QE_STOP_TX 0x00000004
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#define QE_GRACEFUL_STOP_TX 0x00000005
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#define QE_RESTART_TX 0x00000006
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#define QE_CLOSE_RX_BD 0x00000007
|
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#define QE_SWITCH_COMMAND 0x00000007
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#define QE_SET_GROUP_ADDRESS 0x00000008
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#define QE_START_IDMA 0x00000009
|
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#define QE_MCC_STOP_RX 0x00000009
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#define QE_ATM_TRANSMIT 0x0000000a
|
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#define QE_HPAC_CLEAR_ALL 0x0000000b
|
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#define QE_GRACEFUL_STOP_RX 0x0000001a
|
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#define QE_RESTART_RX 0x0000001b
|
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#define QE_HPAC_SET_PRIORITY 0x0000010b
|
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#define QE_HPAC_STOP_TX 0x0000020b
|
|
#define QE_HPAC_STOP_RX 0x0000030b
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#define QE_HPAC_GRACEFUL_STOP_TX 0x0000040b
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#define QE_HPAC_GRACEFUL_STOP_RX 0x0000050b
|
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#define QE_HPAC_START_TX 0x0000060b
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#define QE_HPAC_START_RX 0x0000070b
|
|
#define QE_USB_STOP_TX 0x0000000a
|
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#define QE_USB_RESTART_TX 0x0000000c
|
|
#define QE_QMC_STOP_TX 0x0000000c
|
|
#define QE_QMC_STOP_RX 0x0000000d
|
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#define QE_SS7_SU_FIL_RESET 0x0000000e
|
|
/* jonathbr added from here down for 83xx */
|
|
#define QE_RESET_BCS 0x0000000a
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#define QE_MCC_INIT_TX_RX_16 0x00000003
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#define QE_MCC_STOP_TX 0x00000004
|
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#define QE_MCC_INIT_TX_1 0x00000005
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#define QE_MCC_INIT_RX_1 0x00000006
|
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#define QE_MCC_RESET 0x00000007
|
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#define QE_SET_TIMER 0x00000008
|
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#define QE_RANDOM_NUMBER 0x0000000c
|
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#define QE_ATM_MULTI_THREAD_INIT 0x00000011
|
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#define QE_ASSIGN_PAGE 0x00000012
|
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#define QE_ADD_REMOVE_HASH_ENTRY 0x00000013
|
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#define QE_START_FLOW_CONTROL 0x00000014
|
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#define QE_STOP_FLOW_CONTROL 0x00000015
|
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#define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016
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|
|
#define QE_ASSIGN_RISC 0x00000010
|
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#define QE_CR_MCN_NORMAL_SHIFT 6
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#define QE_CR_MCN_USB_SHIFT 4
|
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#define QE_CR_MCN_RISC_ASSIGN_SHIFT 8
|
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#define QE_CR_SNUM_SHIFT 17
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|
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/* QE CECR Sub Block - sub block of QE command.
|
|
*/
|
|
#define QE_CR_SUBBLOCK_INVALID 0x00000000
|
|
#define QE_CR_SUBBLOCK_USB 0x03200000
|
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#define QE_CR_SUBBLOCK_UCCFAST1 0x02000000
|
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#define QE_CR_SUBBLOCK_UCCFAST2 0x02200000
|
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#define QE_CR_SUBBLOCK_UCCFAST3 0x02400000
|
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#define QE_CR_SUBBLOCK_UCCFAST4 0x02600000
|
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#define QE_CR_SUBBLOCK_UCCFAST5 0x02800000
|
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#define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000
|
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#define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000
|
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#define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000
|
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#define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000
|
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#define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000
|
|
#define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000
|
|
#define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000
|
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#define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000
|
|
#define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000
|
|
#define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000
|
|
#define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000
|
|
#define QE_CR_SUBBLOCK_MCC1 0x03800000
|
|
#define QE_CR_SUBBLOCK_MCC2 0x03a00000
|
|
#define QE_CR_SUBBLOCK_MCC3 0x03000000
|
|
#define QE_CR_SUBBLOCK_IDMA1 0x02800000
|
|
#define QE_CR_SUBBLOCK_IDMA2 0x02a00000
|
|
#define QE_CR_SUBBLOCK_IDMA3 0x02c00000
|
|
#define QE_CR_SUBBLOCK_IDMA4 0x02e00000
|
|
#define QE_CR_SUBBLOCK_HPAC 0x01e00000
|
|
#define QE_CR_SUBBLOCK_SPI1 0x01400000
|
|
#define QE_CR_SUBBLOCK_SPI2 0x01600000
|
|
#define QE_CR_SUBBLOCK_RAND 0x01c00000
|
|
#define QE_CR_SUBBLOCK_TIMER 0x01e00000
|
|
#define QE_CR_SUBBLOCK_GENERAL 0x03c00000
|
|
|
|
/* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command */
|
|
#define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */
|
|
#define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00
|
|
#define QE_CR_PROTOCOL_QMC 0x02
|
|
#define QE_CR_PROTOCOL_UART 0x04
|
|
#define QE_CR_PROTOCOL_ATM_POS 0x0A
|
|
#define QE_CR_PROTOCOL_ETHERNET 0x0C
|
|
#define QE_CR_PROTOCOL_L2_SWITCH 0x0D
|
|
|
|
/* BRG configuration register */
|
|
#define QE_BRGC_ENABLE 0x00010000
|
|
#define QE_BRGC_DIVISOR_SHIFT 1
|
|
#define QE_BRGC_DIVISOR_MAX 0xFFF
|
|
#define QE_BRGC_DIV16 1
|
|
|
|
/* QE Timers registers */
|
|
#define QE_GTCFR1_PCAS 0x80
|
|
#define QE_GTCFR1_STP2 0x20
|
|
#define QE_GTCFR1_RST2 0x10
|
|
#define QE_GTCFR1_GM2 0x08
|
|
#define QE_GTCFR1_GM1 0x04
|
|
#define QE_GTCFR1_STP1 0x02
|
|
#define QE_GTCFR1_RST1 0x01
|
|
|
|
/* SDMA registers */
|
|
#define QE_SDSR_BER1 0x02000000
|
|
#define QE_SDSR_BER2 0x01000000
|
|
|
|
#define QE_SDMR_GLB_1_MSK 0x80000000
|
|
#define QE_SDMR_ADR_SEL 0x20000000
|
|
#define QE_SDMR_BER1_MSK 0x02000000
|
|
#define QE_SDMR_BER2_MSK 0x01000000
|
|
#define QE_SDMR_EB1_MSK 0x00800000
|
|
#define QE_SDMR_ER1_MSK 0x00080000
|
|
#define QE_SDMR_ER2_MSK 0x00040000
|
|
#define QE_SDMR_CEN_MASK 0x0000E000
|
|
#define QE_SDMR_SBER_1 0x00000200
|
|
#define QE_SDMR_SBER_2 0x00000200
|
|
#define QE_SDMR_EB1_PR_MASK 0x000000C0
|
|
#define QE_SDMR_ER1_PR 0x00000008
|
|
|
|
#define QE_SDMR_CEN_SHIFT 13
|
|
#define QE_SDMR_EB1_PR_SHIFT 6
|
|
|
|
#define QE_SDTM_MSNUM_SHIFT 24
|
|
|
|
#define QE_SDEBCR_BA_MASK 0x01FFFFFF
|
|
|
|
/* Communication Processor */
|
|
#define QE_CP_CERCR_MEE 0x8000 /* Multi-user RAM ECC enable */
|
|
#define QE_CP_CERCR_IEE 0x4000 /* Instruction RAM ECC enable */
|
|
#define QE_CP_CERCR_CIR 0x0800 /* Common instruction RAM */
|
|
|
|
/* I-RAM */
|
|
#define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */
|
|
#define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */
|
|
#define QE_IRAM_READY 0x80000000 /* Ready */
|
|
|
|
/* UPC */
|
|
#define UPGCR_PROTOCOL 0x80000000 /* protocol ul2 or pl2 */
|
|
#define UPGCR_TMS 0x40000000 /* Transmit master/slave mode */
|
|
#define UPGCR_RMS 0x20000000 /* Receive master/slave mode */
|
|
#define UPGCR_ADDR 0x10000000 /* Master MPHY Addr multiplexing */
|
|
#define UPGCR_DIAG 0x01000000 /* Diagnostic mode */
|
|
|
|
/* UCC GUEMR register */
|
|
#define UCC_GUEMR_MODE_MASK_RX 0x02
|
|
#define UCC_GUEMR_MODE_FAST_RX 0x02
|
|
#define UCC_GUEMR_MODE_SLOW_RX 0x00
|
|
#define UCC_GUEMR_MODE_MASK_TX 0x01
|
|
#define UCC_GUEMR_MODE_FAST_TX 0x01
|
|
#define UCC_GUEMR_MODE_SLOW_TX 0x00
|
|
#define UCC_GUEMR_MODE_MASK (UCC_GUEMR_MODE_MASK_RX | UCC_GUEMR_MODE_MASK_TX)
|
|
#define UCC_GUEMR_SET_RESERVED3 0x10 /* Bit 3 in the guemr is reserved but
|
|
must be set 1 */
|
|
|
|
/* structure representing UCC SLOW parameter RAM */
|
|
struct ucc_slow_pram {
|
|
__be16 rbase; /* RX BD base address */
|
|
__be16 tbase; /* TX BD base address */
|
|
u8 rbmr; /* RX bus mode register (same as CPM's RFCR) */
|
|
u8 tbmr; /* TX bus mode register (same as CPM's TFCR) */
|
|
__be16 mrblr; /* Rx buffer length */
|
|
__be32 rstate; /* Rx internal state */
|
|
__be32 rptr; /* Rx internal data pointer */
|
|
__be16 rbptr; /* rb BD Pointer */
|
|
__be16 rcount; /* Rx internal byte count */
|
|
__be32 rtemp; /* Rx temp */
|
|
__be32 tstate; /* Tx internal state */
|
|
__be32 tptr; /* Tx internal data pointer */
|
|
__be16 tbptr; /* Tx BD pointer */
|
|
__be16 tcount; /* Tx byte count */
|
|
__be32 ttemp; /* Tx temp */
|
|
__be32 rcrc; /* temp receive CRC */
|
|
__be32 tcrc; /* temp transmit CRC */
|
|
} __attribute__ ((packed));
|
|
|
|
/* General UCC SLOW Mode Register (GUMRH & GUMRL) */
|
|
#define UCC_SLOW_GUMR_H_SAM_QMC 0x00000000
|
|
#define UCC_SLOW_GUMR_H_SAM_SATM 0x00008000
|
|
#define UCC_SLOW_GUMR_H_REVD 0x00002000
|
|
#define UCC_SLOW_GUMR_H_TRX 0x00001000
|
|
#define UCC_SLOW_GUMR_H_TTX 0x00000800
|
|
#define UCC_SLOW_GUMR_H_CDP 0x00000400
|
|
#define UCC_SLOW_GUMR_H_CTSP 0x00000200
|
|
#define UCC_SLOW_GUMR_H_CDS 0x00000100
|
|
#define UCC_SLOW_GUMR_H_CTSS 0x00000080
|
|
#define UCC_SLOW_GUMR_H_TFL 0x00000040
|
|
#define UCC_SLOW_GUMR_H_RFW 0x00000020
|
|
#define UCC_SLOW_GUMR_H_TXSY 0x00000010
|
|
#define UCC_SLOW_GUMR_H_4SYNC 0x00000004
|
|
#define UCC_SLOW_GUMR_H_8SYNC 0x00000008
|
|
#define UCC_SLOW_GUMR_H_16SYNC 0x0000000c
|
|
#define UCC_SLOW_GUMR_H_RTSM 0x00000002
|
|
#define UCC_SLOW_GUMR_H_RSYN 0x00000001
|
|
|
|
#define UCC_SLOW_GUMR_L_TCI 0x10000000
|
|
#define UCC_SLOW_GUMR_L_RINV 0x02000000
|
|
#define UCC_SLOW_GUMR_L_TINV 0x01000000
|
|
#define UCC_SLOW_GUMR_L_TEND 0x00040000
|
|
#define UCC_SLOW_GUMR_L_TDCR_MASK 0x00030000
|
|
#define UCC_SLOW_GUMR_L_TDCR_32 0x00030000
|
|
#define UCC_SLOW_GUMR_L_TDCR_16 0x00020000
|
|
#define UCC_SLOW_GUMR_L_TDCR_8 0x00010000
|
|
#define UCC_SLOW_GUMR_L_TDCR_1 0x00000000
|
|
#define UCC_SLOW_GUMR_L_RDCR_MASK 0x0000c000
|
|
#define UCC_SLOW_GUMR_L_RDCR_32 0x0000c000
|
|
#define UCC_SLOW_GUMR_L_RDCR_16 0x00008000
|
|
#define UCC_SLOW_GUMR_L_RDCR_8 0x00004000
|
|
#define UCC_SLOW_GUMR_L_RDCR_1 0x00000000
|
|
#define UCC_SLOW_GUMR_L_RENC_NRZI 0x00000800
|
|
#define UCC_SLOW_GUMR_L_RENC_NRZ 0x00000000
|
|
#define UCC_SLOW_GUMR_L_TENC_NRZI 0x00000100
|
|
#define UCC_SLOW_GUMR_L_TENC_NRZ 0x00000000
|
|
#define UCC_SLOW_GUMR_L_DIAG_MASK 0x000000c0
|
|
#define UCC_SLOW_GUMR_L_DIAG_LE 0x000000c0
|
|
#define UCC_SLOW_GUMR_L_DIAG_ECHO 0x00000080
|
|
#define UCC_SLOW_GUMR_L_DIAG_LOOP 0x00000040
|
|
#define UCC_SLOW_GUMR_L_DIAG_NORM 0x00000000
|
|
#define UCC_SLOW_GUMR_L_ENR 0x00000020
|
|
#define UCC_SLOW_GUMR_L_ENT 0x00000010
|
|
#define UCC_SLOW_GUMR_L_MODE_MASK 0x0000000F
|
|
#define UCC_SLOW_GUMR_L_MODE_BISYNC 0x00000008
|
|
#define UCC_SLOW_GUMR_L_MODE_AHDLC 0x00000006
|
|
#define UCC_SLOW_GUMR_L_MODE_UART 0x00000004
|
|
#define UCC_SLOW_GUMR_L_MODE_QMC 0x00000002
|
|
|
|
/* General UCC FAST Mode Register */
|
|
#define UCC_FAST_GUMR_LOOPBACK 0x40000000
|
|
#define UCC_FAST_GUMR_TCI 0x20000000
|
|
#define UCC_FAST_GUMR_TRX 0x10000000
|
|
#define UCC_FAST_GUMR_TTX 0x08000000
|
|
#define UCC_FAST_GUMR_CDP 0x04000000
|
|
#define UCC_FAST_GUMR_CTSP 0x02000000
|
|
#define UCC_FAST_GUMR_CDS 0x01000000
|
|
#define UCC_FAST_GUMR_CTSS 0x00800000
|
|
#define UCC_FAST_GUMR_TXSY 0x00020000
|
|
#define UCC_FAST_GUMR_RSYN 0x00010000
|
|
#define UCC_FAST_GUMR_SYNL_MASK 0x0000C000
|
|
#define UCC_FAST_GUMR_SYNL_16 0x0000C000
|
|
#define UCC_FAST_GUMR_SYNL_8 0x00008000
|
|
#define UCC_FAST_GUMR_SYNL_AUTO 0x00004000
|
|
#define UCC_FAST_GUMR_RTSM 0x00002000
|
|
#define UCC_FAST_GUMR_REVD 0x00000400
|
|
#define UCC_FAST_GUMR_ENR 0x00000020
|
|
#define UCC_FAST_GUMR_ENT 0x00000010
|
|
|
|
/* UART Slow UCC Event Register (UCCE) */
|
|
#define UCC_UART_UCCE_AB 0x0200
|
|
#define UCC_UART_UCCE_IDLE 0x0100
|
|
#define UCC_UART_UCCE_GRA 0x0080
|
|
#define UCC_UART_UCCE_BRKE 0x0040
|
|
#define UCC_UART_UCCE_BRKS 0x0020
|
|
#define UCC_UART_UCCE_CCR 0x0008
|
|
#define UCC_UART_UCCE_BSY 0x0004
|
|
#define UCC_UART_UCCE_TX 0x0002
|
|
#define UCC_UART_UCCE_RX 0x0001
|
|
|
|
/* HDLC Slow UCC Event Register (UCCE) */
|
|
#define UCC_HDLC_UCCE_GLR 0x1000
|
|
#define UCC_HDLC_UCCE_GLT 0x0800
|
|
#define UCC_HDLC_UCCE_IDLE 0x0100
|
|
#define UCC_HDLC_UCCE_BRKE 0x0040
|
|
#define UCC_HDLC_UCCE_BRKS 0x0020
|
|
#define UCC_HDLC_UCCE_TXE 0x0010
|
|
#define UCC_HDLC_UCCE_RXF 0x0008
|
|
#define UCC_HDLC_UCCE_BSY 0x0004
|
|
#define UCC_HDLC_UCCE_TXB 0x0002
|
|
#define UCC_HDLC_UCCE_RXB 0x0001
|
|
|
|
/* BISYNC Slow UCC Event Register (UCCE) */
|
|
#define UCC_BISYNC_UCCE_GRA 0x0080
|
|
#define UCC_BISYNC_UCCE_TXE 0x0010
|
|
#define UCC_BISYNC_UCCE_RCH 0x0008
|
|
#define UCC_BISYNC_UCCE_BSY 0x0004
|
|
#define UCC_BISYNC_UCCE_TXB 0x0002
|
|
#define UCC_BISYNC_UCCE_RXB 0x0001
|
|
|
|
/* Gigabit Ethernet Fast UCC Event Register (UCCE) */
|
|
#define UCC_GETH_UCCE_MPD 0x80000000
|
|
#define UCC_GETH_UCCE_SCAR 0x40000000
|
|
#define UCC_GETH_UCCE_GRA 0x20000000
|
|
#define UCC_GETH_UCCE_CBPR 0x10000000
|
|
#define UCC_GETH_UCCE_BSY 0x08000000
|
|
#define UCC_GETH_UCCE_RXC 0x04000000
|
|
#define UCC_GETH_UCCE_TXC 0x02000000
|
|
#define UCC_GETH_UCCE_TXE 0x01000000
|
|
#define UCC_GETH_UCCE_TXB7 0x00800000
|
|
#define UCC_GETH_UCCE_TXB6 0x00400000
|
|
#define UCC_GETH_UCCE_TXB5 0x00200000
|
|
#define UCC_GETH_UCCE_TXB4 0x00100000
|
|
#define UCC_GETH_UCCE_TXB3 0x00080000
|
|
#define UCC_GETH_UCCE_TXB2 0x00040000
|
|
#define UCC_GETH_UCCE_TXB1 0x00020000
|
|
#define UCC_GETH_UCCE_TXB0 0x00010000
|
|
#define UCC_GETH_UCCE_RXB7 0x00008000
|
|
#define UCC_GETH_UCCE_RXB6 0x00004000
|
|
#define UCC_GETH_UCCE_RXB5 0x00002000
|
|
#define UCC_GETH_UCCE_RXB4 0x00001000
|
|
#define UCC_GETH_UCCE_RXB3 0x00000800
|
|
#define UCC_GETH_UCCE_RXB2 0x00000400
|
|
#define UCC_GETH_UCCE_RXB1 0x00000200
|
|
#define UCC_GETH_UCCE_RXB0 0x00000100
|
|
#define UCC_GETH_UCCE_RXF7 0x00000080
|
|
#define UCC_GETH_UCCE_RXF6 0x00000040
|
|
#define UCC_GETH_UCCE_RXF5 0x00000020
|
|
#define UCC_GETH_UCCE_RXF4 0x00000010
|
|
#define UCC_GETH_UCCE_RXF3 0x00000008
|
|
#define UCC_GETH_UCCE_RXF2 0x00000004
|
|
#define UCC_GETH_UCCE_RXF1 0x00000002
|
|
#define UCC_GETH_UCCE_RXF0 0x00000001
|
|
|
|
/* UCC Protocol Specific Mode Register (UPSMR), when used for UART */
|
|
#define UCC_UART_UPSMR_FLC 0x8000
|
|
#define UCC_UART_UPSMR_SL 0x4000
|
|
#define UCC_UART_UPSMR_CL_MASK 0x3000
|
|
#define UCC_UART_UPSMR_CL_8 0x3000
|
|
#define UCC_UART_UPSMR_CL_7 0x2000
|
|
#define UCC_UART_UPSMR_CL_6 0x1000
|
|
#define UCC_UART_UPSMR_CL_5 0x0000
|
|
#define UCC_UART_UPSMR_UM_MASK 0x0c00
|
|
#define UCC_UART_UPSMR_UM_NORMAL 0x0000
|
|
#define UCC_UART_UPSMR_UM_MAN_MULTI 0x0400
|
|
#define UCC_UART_UPSMR_UM_AUTO_MULTI 0x0c00
|
|
#define UCC_UART_UPSMR_FRZ 0x0200
|
|
#define UCC_UART_UPSMR_RZS 0x0100
|
|
#define UCC_UART_UPSMR_SYN 0x0080
|
|
#define UCC_UART_UPSMR_DRT 0x0040
|
|
#define UCC_UART_UPSMR_PEN 0x0010
|
|
#define UCC_UART_UPSMR_RPM_MASK 0x000c
|
|
#define UCC_UART_UPSMR_RPM_ODD 0x0000
|
|
#define UCC_UART_UPSMR_RPM_LOW 0x0004
|
|
#define UCC_UART_UPSMR_RPM_EVEN 0x0008
|
|
#define UCC_UART_UPSMR_RPM_HIGH 0x000C
|
|
#define UCC_UART_UPSMR_TPM_MASK 0x0003
|
|
#define UCC_UART_UPSMR_TPM_ODD 0x0000
|
|
#define UCC_UART_UPSMR_TPM_LOW 0x0001
|
|
#define UCC_UART_UPSMR_TPM_EVEN 0x0002
|
|
#define UCC_UART_UPSMR_TPM_HIGH 0x0003
|
|
|
|
/* UCC Protocol Specific Mode Register (UPSMR), when used for Ethernet */
|
|
#define UCC_GETH_UPSMR_FTFE 0x80000000
|
|
#define UCC_GETH_UPSMR_PTPE 0x40000000
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#define UCC_GETH_UPSMR_ECM 0x04000000
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#define UCC_GETH_UPSMR_HSE 0x02000000
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#define UCC_GETH_UPSMR_PRO 0x00400000
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#define UCC_GETH_UPSMR_CAP 0x00200000
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#define UCC_GETH_UPSMR_RSH 0x00100000
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#define UCC_GETH_UPSMR_RPM 0x00080000
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#define UCC_GETH_UPSMR_R10M 0x00040000
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#define UCC_GETH_UPSMR_RLPB 0x00020000
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#define UCC_GETH_UPSMR_TBIM 0x00010000
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#define UCC_GETH_UPSMR_RES1 0x00002000
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#define UCC_GETH_UPSMR_RMM 0x00001000
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#define UCC_GETH_UPSMR_CAM 0x00000400
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#define UCC_GETH_UPSMR_BRO 0x00000200
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#define UCC_GETH_UPSMR_SMM 0x00000080
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#define UCC_GETH_UPSMR_SGMM 0x00000020
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/* UCC Transmit On Demand Register (UTODR) */
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#define UCC_SLOW_TOD 0x8000
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#define UCC_FAST_TOD 0x8000
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/* UCC Bus Mode Register masks */
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/* Not to be confused with the Bundle Mode Register */
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#define UCC_BMR_GBL 0x20
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#define UCC_BMR_BO_BE 0x10
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#define UCC_BMR_CETM 0x04
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#define UCC_BMR_DTB 0x02
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#define UCC_BMR_BDB 0x01
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/* Function code masks */
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#define FC_GBL 0x20
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#define FC_DTB_LCL 0x02
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#define UCC_FAST_FUNCTION_CODE_GBL 0x20
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#define UCC_FAST_FUNCTION_CODE_DTB_LCL 0x02
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#define UCC_FAST_FUNCTION_CODE_BDB_LCL 0x01
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_QE_H */
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