428 lines
13 KiB
Diff
428 lines
13 KiB
Diff
From 94561afa3b3b778ef7be4a9b33e436ed382b8e46 Mon Sep 17 00:00:00 2001
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From: Frank Rowand <frank.rowand@am.sony.com>
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Date: Mon, 19 Sep 2011 14:51:14 -0700
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Subject: [PATCH 052/365] arm: Convert arm boot_lock to raw
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The arm boot_lock is used by the secondary processor startup code. The locking
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task is the idle thread, which has idle->sched_class == &idle_sched_class.
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idle_sched_class->enqueue_task == NULL, so if the idle task blocks on the
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lock, the attempt to wake it when the lock becomes available will fail:
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try_to_wake_up()
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...
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activate_task()
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enqueue_task()
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p->sched_class->enqueue_task(rq, p, flags)
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Fix by converting boot_lock to a raw spin lock.
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Signed-off-by: Frank Rowand <frank.rowand@am.sony.com>
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Link: http://lkml.kernel.org/r/4E77B952.3010606@am.sony.com
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Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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---
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arch/arm/mach-exynos/platsmp.c | 12 ++++++------
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arch/arm/mach-hisi/platmcpm.c | 22 +++++++++++-----------
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arch/arm/mach-omap2/omap-smp.c | 10 +++++-----
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arch/arm/mach-prima2/platsmp.c | 10 +++++-----
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arch/arm/mach-qcom/platsmp.c | 10 +++++-----
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arch/arm/mach-spear/platsmp.c | 10 +++++-----
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arch/arm/mach-sti/platsmp.c | 10 +++++-----
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arch/arm/plat-versatile/platsmp.c | 10 +++++-----
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8 files changed, 47 insertions(+), 47 deletions(-)
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diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
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index 98ffe1e62ad5..df9769ddece5 100644
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--- a/arch/arm/mach-exynos/platsmp.c
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+++ b/arch/arm/mach-exynos/platsmp.c
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@@ -229,7 +229,7 @@ static void __iomem *scu_base_addr(void)
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return (void __iomem *)(S5P_VA_SCU);
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}
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-static DEFINE_SPINLOCK(boot_lock);
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+static DEFINE_RAW_SPINLOCK(boot_lock);
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static void exynos_secondary_init(unsigned int cpu)
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{
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@@ -242,8 +242,8 @@ static void exynos_secondary_init(unsigned int cpu)
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/*
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* Synchronise with the boot thread.
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*/
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- spin_lock(&boot_lock);
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- spin_unlock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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}
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int exynos_set_boot_addr(u32 core_id, unsigned long boot_addr)
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@@ -307,7 +307,7 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
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* Set synchronisation state between this boot processor
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* and the secondary one
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*/
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- spin_lock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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/*
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* The secondary processor is waiting to be released from
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@@ -334,7 +334,7 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
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if (timeout == 0) {
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printk(KERN_ERR "cpu1 power enable failed");
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- spin_unlock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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return -ETIMEDOUT;
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}
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}
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@@ -380,7 +380,7 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
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* calibrations, then wait for it to finish
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*/
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fail:
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- spin_unlock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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return pen_release != -1 ? ret : 0;
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}
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diff --git a/arch/arm/mach-hisi/platmcpm.c b/arch/arm/mach-hisi/platmcpm.c
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index 4b653a8cb75c..b03d5a922cb1 100644
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--- a/arch/arm/mach-hisi/platmcpm.c
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+++ b/arch/arm/mach-hisi/platmcpm.c
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@@ -61,7 +61,7 @@
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static void __iomem *sysctrl, *fabric;
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static int hip04_cpu_table[HIP04_MAX_CLUSTERS][HIP04_MAX_CPUS_PER_CLUSTER];
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-static DEFINE_SPINLOCK(boot_lock);
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+static DEFINE_RAW_SPINLOCK(boot_lock);
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static u32 fabric_phys_addr;
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/*
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* [0]: bootwrapper physical address
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@@ -113,7 +113,7 @@ static int hip04_boot_secondary(unsigned int l_cpu, struct task_struct *idle)
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if (cluster >= HIP04_MAX_CLUSTERS || cpu >= HIP04_MAX_CPUS_PER_CLUSTER)
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return -EINVAL;
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- spin_lock_irq(&boot_lock);
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+ raw_spin_lock_irq(&boot_lock);
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if (hip04_cpu_table[cluster][cpu])
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goto out;
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@@ -147,7 +147,7 @@ static int hip04_boot_secondary(unsigned int l_cpu, struct task_struct *idle)
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out:
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hip04_cpu_table[cluster][cpu]++;
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- spin_unlock_irq(&boot_lock);
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+ raw_spin_unlock_irq(&boot_lock);
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return 0;
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}
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@@ -162,11 +162,11 @@ static void hip04_cpu_die(unsigned int l_cpu)
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cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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- spin_lock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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hip04_cpu_table[cluster][cpu]--;
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if (hip04_cpu_table[cluster][cpu] == 1) {
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/* A power_up request went ahead of us. */
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- spin_unlock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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return;
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} else if (hip04_cpu_table[cluster][cpu] > 1) {
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pr_err("Cluster %d CPU%d boots multiple times\n", cluster, cpu);
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@@ -174,7 +174,7 @@ static void hip04_cpu_die(unsigned int l_cpu)
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}
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last_man = hip04_cluster_is_down(cluster);
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- spin_unlock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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if (last_man) {
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/* Since it's Cortex A15, disable L2 prefetching. */
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asm volatile(
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@@ -203,7 +203,7 @@ static int hip04_cpu_kill(unsigned int l_cpu)
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cpu >= HIP04_MAX_CPUS_PER_CLUSTER);
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count = TIMEOUT_MSEC / POLL_MSEC;
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- spin_lock_irq(&boot_lock);
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+ raw_spin_lock_irq(&boot_lock);
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for (tries = 0; tries < count; tries++) {
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if (hip04_cpu_table[cluster][cpu])
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goto err;
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@@ -211,10 +211,10 @@ static int hip04_cpu_kill(unsigned int l_cpu)
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data = readl_relaxed(sysctrl + SC_CPU_RESET_STATUS(cluster));
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if (data & CORE_WFI_STATUS(cpu))
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break;
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- spin_unlock_irq(&boot_lock);
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+ raw_spin_unlock_irq(&boot_lock);
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/* Wait for clean L2 when the whole cluster is down. */
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msleep(POLL_MSEC);
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- spin_lock_irq(&boot_lock);
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+ raw_spin_lock_irq(&boot_lock);
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}
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if (tries >= count)
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goto err;
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@@ -231,10 +231,10 @@ static int hip04_cpu_kill(unsigned int l_cpu)
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goto err;
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if (hip04_cluster_is_down(cluster))
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hip04_set_snoop_filter(cluster, 0);
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- spin_unlock_irq(&boot_lock);
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+ raw_spin_unlock_irq(&boot_lock);
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return 1;
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err:
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- spin_unlock_irq(&boot_lock);
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+ raw_spin_unlock_irq(&boot_lock);
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return 0;
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}
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#endif
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diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
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index f7f36da80f40..7e865f118974 100644
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--- a/arch/arm/mach-omap2/omap-smp.c
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+++ b/arch/arm/mach-omap2/omap-smp.c
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@@ -64,7 +64,7 @@ static const struct omap_smp_config omap5_cfg __initconst = {
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.startup_addr = omap5_secondary_startup,
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};
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-static DEFINE_SPINLOCK(boot_lock);
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+static DEFINE_RAW_SPINLOCK(boot_lock);
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void __iomem *omap4_get_scu_base(void)
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{
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@@ -172,8 +172,8 @@ static void omap4_secondary_init(unsigned int cpu)
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/*
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* Synchronise with the boot thread.
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*/
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- spin_lock(&boot_lock);
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- spin_unlock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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}
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static int omap4_boot_secondary(unsigned int cpu, struct task_struct *idle)
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@@ -187,7 +187,7 @@ static int omap4_boot_secondary(unsigned int cpu, struct task_struct *idle)
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* Set synchronisation state between this boot processor
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* and the secondary one
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*/
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- spin_lock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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/*
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* Update the AuxCoreBoot0 with boot state for secondary core.
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@@ -264,7 +264,7 @@ static int omap4_boot_secondary(unsigned int cpu, struct task_struct *idle)
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* Now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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- spin_unlock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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return 0;
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}
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diff --git a/arch/arm/mach-prima2/platsmp.c b/arch/arm/mach-prima2/platsmp.c
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index 0875b99add18..18b6d98d2581 100644
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--- a/arch/arm/mach-prima2/platsmp.c
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+++ b/arch/arm/mach-prima2/platsmp.c
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@@ -22,7 +22,7 @@
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static void __iomem *clk_base;
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-static DEFINE_SPINLOCK(boot_lock);
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+static DEFINE_RAW_SPINLOCK(boot_lock);
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static void sirfsoc_secondary_init(unsigned int cpu)
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{
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@@ -36,8 +36,8 @@ static void sirfsoc_secondary_init(unsigned int cpu)
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/*
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* Synchronise with the boot thread.
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*/
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- spin_lock(&boot_lock);
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- spin_unlock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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}
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static const struct of_device_id clk_ids[] = {
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@@ -75,7 +75,7 @@ static int sirfsoc_boot_secondary(unsigned int cpu, struct task_struct *idle)
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/* make sure write buffer is drained */
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mb();
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- spin_lock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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/*
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* The secondary processor is waiting to be released from
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@@ -107,7 +107,7 @@ static int sirfsoc_boot_secondary(unsigned int cpu, struct task_struct *idle)
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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- spin_unlock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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return pen_release != -1 ? -ENOSYS : 0;
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}
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diff --git a/arch/arm/mach-qcom/platsmp.c b/arch/arm/mach-qcom/platsmp.c
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index 5494c9e0c909..e8ce157d3548 100644
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--- a/arch/arm/mach-qcom/platsmp.c
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+++ b/arch/arm/mach-qcom/platsmp.c
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@@ -46,7 +46,7 @@
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extern void secondary_startup_arm(void);
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-static DEFINE_SPINLOCK(boot_lock);
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+static DEFINE_RAW_SPINLOCK(boot_lock);
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#ifdef CONFIG_HOTPLUG_CPU
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static void qcom_cpu_die(unsigned int cpu)
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@@ -60,8 +60,8 @@ static void qcom_secondary_init(unsigned int cpu)
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/*
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* Synchronise with the boot thread.
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*/
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- spin_lock(&boot_lock);
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- spin_unlock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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}
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static int scss_release_secondary(unsigned int cpu)
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@@ -284,7 +284,7 @@ static int qcom_boot_secondary(unsigned int cpu, int (*func)(unsigned int))
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* set synchronisation state between this boot processor
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* and the secondary one
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*/
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- spin_lock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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/*
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* Send the secondary CPU a soft interrupt, thereby causing
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@@ -297,7 +297,7 @@ static int qcom_boot_secondary(unsigned int cpu, int (*func)(unsigned int))
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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- spin_unlock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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return ret;
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}
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diff --git a/arch/arm/mach-spear/platsmp.c b/arch/arm/mach-spear/platsmp.c
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index 8d1e2d551786..7fa56cc78118 100644
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--- a/arch/arm/mach-spear/platsmp.c
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+++ b/arch/arm/mach-spear/platsmp.c
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@@ -32,7 +32,7 @@ static void write_pen_release(int val)
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sync_cache_w(&pen_release);
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}
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-static DEFINE_SPINLOCK(boot_lock);
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+static DEFINE_RAW_SPINLOCK(boot_lock);
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static void __iomem *scu_base = IOMEM(VA_SCU_BASE);
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@@ -47,8 +47,8 @@ static void spear13xx_secondary_init(unsigned int cpu)
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/*
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* Synchronise with the boot thread.
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*/
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- spin_lock(&boot_lock);
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- spin_unlock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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}
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static int spear13xx_boot_secondary(unsigned int cpu, struct task_struct *idle)
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@@ -59,7 +59,7 @@ static int spear13xx_boot_secondary(unsigned int cpu, struct task_struct *idle)
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* set synchronisation state between this boot processor
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* and the secondary one
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*/
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- spin_lock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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/*
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* The secondary processor is waiting to be released from
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@@ -84,7 +84,7 @@ static int spear13xx_boot_secondary(unsigned int cpu, struct task_struct *idle)
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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- spin_unlock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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return pen_release != -1 ? -ENOSYS : 0;
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}
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diff --git a/arch/arm/mach-sti/platsmp.c b/arch/arm/mach-sti/platsmp.c
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index ea5a2277ee46..b988e081ac79 100644
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--- a/arch/arm/mach-sti/platsmp.c
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+++ b/arch/arm/mach-sti/platsmp.c
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@@ -35,7 +35,7 @@ static void write_pen_release(int val)
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sync_cache_w(&pen_release);
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}
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-static DEFINE_SPINLOCK(boot_lock);
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+static DEFINE_RAW_SPINLOCK(boot_lock);
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static void sti_secondary_init(unsigned int cpu)
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{
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@@ -48,8 +48,8 @@ static void sti_secondary_init(unsigned int cpu)
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/*
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* Synchronise with the boot thread.
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*/
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- spin_lock(&boot_lock);
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- spin_unlock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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}
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static int sti_boot_secondary(unsigned int cpu, struct task_struct *idle)
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@@ -60,7 +60,7 @@ static int sti_boot_secondary(unsigned int cpu, struct task_struct *idle)
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* set synchronisation state between this boot processor
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* and the secondary one
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*/
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- spin_lock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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/*
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* The secondary processor is waiting to be released from
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@@ -91,7 +91,7 @@ static int sti_boot_secondary(unsigned int cpu, struct task_struct *idle)
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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- spin_unlock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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return pen_release != -1 ? -ENOSYS : 0;
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}
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diff --git a/arch/arm/plat-versatile/platsmp.c b/arch/arm/plat-versatile/platsmp.c
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index c2366510187a..6b60f582b738 100644
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--- a/arch/arm/plat-versatile/platsmp.c
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+++ b/arch/arm/plat-versatile/platsmp.c
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@@ -32,7 +32,7 @@ static void write_pen_release(int val)
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sync_cache_w(&pen_release);
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}
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-static DEFINE_SPINLOCK(boot_lock);
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+static DEFINE_RAW_SPINLOCK(boot_lock);
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void versatile_secondary_init(unsigned int cpu)
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{
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@@ -45,8 +45,8 @@ void versatile_secondary_init(unsigned int cpu)
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/*
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* Synchronise with the boot thread.
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*/
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- spin_lock(&boot_lock);
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- spin_unlock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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}
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int versatile_boot_secondary(unsigned int cpu, struct task_struct *idle)
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@@ -57,7 +57,7 @@ int versatile_boot_secondary(unsigned int cpu, struct task_struct *idle)
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* Set synchronisation state between this boot processor
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* and the secondary one
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*/
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- spin_lock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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/*
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* This is really belt and braces; we hold unintended secondary
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@@ -87,7 +87,7 @@ int versatile_boot_secondary(unsigned int cpu, struct task_struct *idle)
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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- spin_unlock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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return pen_release != -1 ? -ENOSYS : 0;
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}
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--
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2.28.0
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