542 lines
14 KiB
C
542 lines
14 KiB
C
/*
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* sst_acpi.c - SST (LPE) driver init file for ACPI enumeration.
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*
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* Copyright (c) 2013, Intel Corporation.
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*
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* Authors: Ramesh Babu K V <Ramesh.Babu@intel.com>
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* Authors: Omair Mohammed Abdullah <omair.m.abdullah@intel.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*
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*/
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#include <linux/module.h>
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#include <linux/fs.h>
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#include <linux/interrupt.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/miscdevice.h>
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#include <linux/platform_device.h>
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#include <linux/firmware.h>
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#include <linux/pm_runtime.h>
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#include <linux/pm_qos.h>
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#include <linux/dmi.h>
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#include <linux/acpi.h>
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#include <asm/platform_sst_audio.h>
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#include <sound/core.h>
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#include <sound/soc.h>
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#include <sound/compress_driver.h>
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#include <acpi/acbuffer.h>
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#include <acpi/platform/acenv.h>
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#include <acpi/platform/aclinux.h>
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#include <acpi/actypes.h>
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#include <acpi/acpi_bus.h>
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#include <asm/cpu_device_id.h>
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#include <asm/iosf_mbi.h>
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#include "../sst-mfld-platform.h"
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#include "../../common/sst-dsp.h"
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#include "../../common/sst-acpi.h"
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#include "sst.h"
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/* LPE viewpoint addresses */
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#define SST_BYT_IRAM_PHY_START 0xff2c0000
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#define SST_BYT_IRAM_PHY_END 0xff2d4000
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#define SST_BYT_DRAM_PHY_START 0xff300000
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#define SST_BYT_DRAM_PHY_END 0xff320000
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#define SST_BYT_IMR_VIRT_START 0xc0000000 /* virtual addr in LPE */
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#define SST_BYT_IMR_VIRT_END 0xc01fffff
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#define SST_BYT_SHIM_PHY_ADDR 0xff340000
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#define SST_BYT_MBOX_PHY_ADDR 0xff344000
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#define SST_BYT_DMA0_PHY_ADDR 0xff298000
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#define SST_BYT_DMA1_PHY_ADDR 0xff29c000
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#define SST_BYT_SSP0_PHY_ADDR 0xff2a0000
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#define SST_BYT_SSP2_PHY_ADDR 0xff2a2000
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#define BYT_FW_MOD_TABLE_OFFSET 0x80000
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#define BYT_FW_MOD_TABLE_SIZE 0x100
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#define BYT_FW_MOD_OFFSET (BYT_FW_MOD_TABLE_OFFSET + BYT_FW_MOD_TABLE_SIZE)
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static const struct sst_info byt_fwparse_info = {
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.use_elf = false,
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.max_streams = 25,
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.iram_start = SST_BYT_IRAM_PHY_START,
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.iram_end = SST_BYT_IRAM_PHY_END,
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.iram_use = true,
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.dram_start = SST_BYT_DRAM_PHY_START,
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.dram_end = SST_BYT_DRAM_PHY_END,
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.dram_use = true,
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.imr_start = SST_BYT_IMR_VIRT_START,
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.imr_end = SST_BYT_IMR_VIRT_END,
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.imr_use = true,
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.mailbox_start = SST_BYT_MBOX_PHY_ADDR,
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.num_probes = 0,
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.lpe_viewpt_rqd = true,
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};
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static const struct sst_ipc_info byt_ipc_info = {
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.ipc_offset = 0,
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.mbox_recv_off = 0x400,
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};
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static const struct sst_lib_dnld_info byt_lib_dnld_info = {
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.mod_base = SST_BYT_IMR_VIRT_START,
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.mod_end = SST_BYT_IMR_VIRT_END,
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.mod_table_offset = BYT_FW_MOD_TABLE_OFFSET,
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.mod_table_size = BYT_FW_MOD_TABLE_SIZE,
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.mod_ddr_dnld = false,
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};
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static const struct sst_res_info byt_rvp_res_info = {
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.shim_offset = 0x140000,
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.shim_size = 0x000100,
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.shim_phy_addr = SST_BYT_SHIM_PHY_ADDR,
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.ssp0_offset = 0xa0000,
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.ssp0_size = 0x1000,
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.dma0_offset = 0x98000,
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.dma0_size = 0x4000,
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.dma1_offset = 0x9c000,
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.dma1_size = 0x4000,
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.iram_offset = 0x0c0000,
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.iram_size = 0x14000,
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.dram_offset = 0x100000,
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.dram_size = 0x28000,
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.mbox_offset = 0x144000,
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.mbox_size = 0x1000,
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.acpi_lpe_res_index = 0,
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.acpi_ddr_index = 2,
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.acpi_ipc_irq_index = 5,
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};
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/* BYTCR has different BIOS from BYT */
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static const struct sst_res_info bytcr_res_info = {
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.shim_offset = 0x140000,
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.shim_size = 0x000100,
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.shim_phy_addr = SST_BYT_SHIM_PHY_ADDR,
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.ssp0_offset = 0xa0000,
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.ssp0_size = 0x1000,
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.dma0_offset = 0x98000,
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.dma0_size = 0x4000,
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.dma1_offset = 0x9c000,
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.dma1_size = 0x4000,
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.iram_offset = 0x0c0000,
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.iram_size = 0x14000,
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.dram_offset = 0x100000,
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.dram_size = 0x28000,
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.mbox_offset = 0x144000,
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.mbox_size = 0x1000,
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.acpi_lpe_res_index = 0,
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.acpi_ddr_index = 2,
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.acpi_ipc_irq_index = 0
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};
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static struct sst_platform_info byt_rvp_platform_data = {
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.probe_data = &byt_fwparse_info,
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.ipc_info = &byt_ipc_info,
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.lib_info = &byt_lib_dnld_info,
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.res_info = &byt_rvp_res_info,
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.platform = "sst-mfld-platform",
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};
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/* Cherryview (Cherrytrail and Braswell) uses same mrfld dpcm fw as Baytrail,
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* so pdata is same as Baytrail.
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*/
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static struct sst_platform_info chv_platform_data = {
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.probe_data = &byt_fwparse_info,
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.ipc_info = &byt_ipc_info,
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.lib_info = &byt_lib_dnld_info,
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.res_info = &byt_rvp_res_info,
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.platform = "sst-mfld-platform",
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};
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static int sst_platform_get_resources(struct intel_sst_drv *ctx)
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{
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struct resource *rsrc;
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struct platform_device *pdev = to_platform_device(ctx->dev);
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/* All ACPI resource request here */
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/* Get Shim addr */
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rsrc = platform_get_resource(pdev, IORESOURCE_MEM,
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ctx->pdata->res_info->acpi_lpe_res_index);
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if (!rsrc) {
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dev_err(ctx->dev, "Invalid SHIM base from IFWI\n");
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return -EIO;
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}
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dev_info(ctx->dev, "LPE base: %#x size:%#x", (unsigned int) rsrc->start,
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(unsigned int)resource_size(rsrc));
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ctx->iram_base = rsrc->start + ctx->pdata->res_info->iram_offset;
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ctx->iram_end = ctx->iram_base + ctx->pdata->res_info->iram_size - 1;
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dev_info(ctx->dev, "IRAM base: %#x", ctx->iram_base);
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ctx->iram = devm_ioremap_nocache(ctx->dev, ctx->iram_base,
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ctx->pdata->res_info->iram_size);
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if (!ctx->iram) {
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dev_err(ctx->dev, "unable to map IRAM\n");
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return -EIO;
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}
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ctx->dram_base = rsrc->start + ctx->pdata->res_info->dram_offset;
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ctx->dram_end = ctx->dram_base + ctx->pdata->res_info->dram_size - 1;
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dev_info(ctx->dev, "DRAM base: %#x", ctx->dram_base);
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ctx->dram = devm_ioremap_nocache(ctx->dev, ctx->dram_base,
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ctx->pdata->res_info->dram_size);
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if (!ctx->dram) {
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dev_err(ctx->dev, "unable to map DRAM\n");
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return -EIO;
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}
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ctx->shim_phy_add = rsrc->start + ctx->pdata->res_info->shim_offset;
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dev_info(ctx->dev, "SHIM base: %#x", ctx->shim_phy_add);
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ctx->shim = devm_ioremap_nocache(ctx->dev, ctx->shim_phy_add,
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ctx->pdata->res_info->shim_size);
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if (!ctx->shim) {
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dev_err(ctx->dev, "unable to map SHIM\n");
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return -EIO;
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}
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/* reassign physical address to LPE viewpoint address */
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ctx->shim_phy_add = ctx->pdata->res_info->shim_phy_addr;
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/* Get mailbox addr */
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ctx->mailbox_add = rsrc->start + ctx->pdata->res_info->mbox_offset;
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dev_info(ctx->dev, "Mailbox base: %#x", ctx->mailbox_add);
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ctx->mailbox = devm_ioremap_nocache(ctx->dev, ctx->mailbox_add,
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ctx->pdata->res_info->mbox_size);
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if (!ctx->mailbox) {
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dev_err(ctx->dev, "unable to map mailbox\n");
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return -EIO;
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}
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/* reassign physical address to LPE viewpoint address */
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ctx->mailbox_add = ctx->info.mailbox_start;
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rsrc = platform_get_resource(pdev, IORESOURCE_MEM,
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ctx->pdata->res_info->acpi_ddr_index);
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if (!rsrc) {
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dev_err(ctx->dev, "Invalid DDR base from IFWI\n");
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return -EIO;
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}
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ctx->ddr_base = rsrc->start;
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ctx->ddr_end = rsrc->end;
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dev_info(ctx->dev, "DDR base: %#x", ctx->ddr_base);
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ctx->ddr = devm_ioremap_nocache(ctx->dev, ctx->ddr_base,
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resource_size(rsrc));
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if (!ctx->ddr) {
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dev_err(ctx->dev, "unable to map DDR\n");
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return -EIO;
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}
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/* Find the IRQ */
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ctx->irq_num = platform_get_irq(pdev,
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ctx->pdata->res_info->acpi_ipc_irq_index);
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return 0;
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}
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static int is_byt_cr(struct device *dev, bool *bytcr)
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{
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int status = 0;
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if (IS_ENABLED(CONFIG_IOSF_MBI)) {
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static const struct x86_cpu_id cpu_ids[] = {
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{ X86_VENDOR_INTEL, 6, 55 }, /* Valleyview, Bay Trail */
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{}
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};
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u32 bios_status;
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if (!x86_match_cpu(cpu_ids) || !iosf_mbi_available()) {
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/* bail silently */
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return status;
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}
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status = iosf_mbi_read(BT_MBI_UNIT_PMC, /* 0x04 PUNIT */
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MBI_REG_READ, /* 0x10 */
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0x006, /* BIOS_CONFIG */
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&bios_status);
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if (status) {
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dev_err(dev, "could not read PUNIT BIOS_CONFIG\n");
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} else {
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/* bits 26:27 mirror PMIC options */
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bios_status = (bios_status >> 26) & 3;
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if ((bios_status == 1) || (bios_status == 3))
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*bytcr = true;
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else
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dev_info(dev, "BYT-CR not detected\n");
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}
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} else {
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dev_info(dev, "IOSF_MBI not enabled, no BYT-CR detection\n");
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}
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return status;
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}
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static int sst_acpi_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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int ret = 0;
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struct intel_sst_drv *ctx;
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const struct acpi_device_id *id;
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struct sst_acpi_mach *mach;
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struct platform_device *mdev;
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struct platform_device *plat_dev;
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struct sst_platform_info *pdata;
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unsigned int dev_id;
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bool bytcr = false;
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id = acpi_match_device(dev->driver->acpi_match_table, dev);
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if (!id)
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return -ENODEV;
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dev_dbg(dev, "for %s\n", id->id);
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mach = (struct sst_acpi_mach *)id->driver_data;
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mach = sst_acpi_find_machine(mach);
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if (mach == NULL) {
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dev_err(dev, "No matching machine driver found\n");
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return -ENODEV;
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}
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if (mach->machine_quirk)
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mach = mach->machine_quirk(mach);
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pdata = mach->pdata;
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ret = kstrtouint(id->id, 16, &dev_id);
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if (ret < 0) {
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dev_err(dev, "Unique device id conversion error: %d\n", ret);
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return ret;
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}
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dev_dbg(dev, "ACPI device id: %x\n", dev_id);
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ret = sst_alloc_drv_context(&ctx, dev, dev_id);
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if (ret < 0)
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return ret;
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ret = is_byt_cr(dev, &bytcr);
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if (!((ret < 0) || (bytcr == false))) {
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dev_info(dev, "Detected Baytrail-CR platform\n");
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/* override resource info */
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byt_rvp_platform_data.res_info = &bytcr_res_info;
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}
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plat_dev = platform_device_register_data(dev, pdata->platform, -1,
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NULL, 0);
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if (IS_ERR(plat_dev)) {
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dev_err(dev, "Failed to create machine device: %s\n",
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pdata->platform);
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return PTR_ERR(plat_dev);
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}
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/*
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* Create platform device for sst machine driver,
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* pass machine info as pdata
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*/
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mdev = platform_device_register_data(dev, mach->drv_name, -1,
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(const void *)mach, sizeof(*mach));
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if (IS_ERR(mdev)) {
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dev_err(dev, "Failed to create machine device: %s\n",
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mach->drv_name);
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return PTR_ERR(mdev);
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}
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/* Fill sst platform data */
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ctx->pdata = pdata;
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strcpy(ctx->firmware_name, mach->fw_filename);
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ret = sst_platform_get_resources(ctx);
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if (ret)
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return ret;
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ret = sst_context_init(ctx);
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if (ret < 0)
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return ret;
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/* need to save shim registers in BYT */
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ctx->shim_regs64 = devm_kzalloc(ctx->dev, sizeof(*ctx->shim_regs64),
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GFP_KERNEL);
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if (!ctx->shim_regs64) {
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ret = -ENOMEM;
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goto do_sst_cleanup;
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}
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sst_configure_runtime_pm(ctx);
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platform_set_drvdata(pdev, ctx);
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return ret;
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do_sst_cleanup:
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sst_context_cleanup(ctx);
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platform_set_drvdata(pdev, NULL);
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dev_err(ctx->dev, "failed with %d\n", ret);
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return ret;
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}
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/**
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* intel_sst_remove - remove function
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*
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* @pdev: platform device structure
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*
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* This function is called by OS when a device is unloaded
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* This frees the interrupt etc
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*/
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static int sst_acpi_remove(struct platform_device *pdev)
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{
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struct intel_sst_drv *ctx;
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ctx = platform_get_drvdata(pdev);
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sst_context_cleanup(ctx);
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platform_set_drvdata(pdev, NULL);
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return 0;
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}
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static unsigned long cht_machine_id;
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#define CHT_SURFACE_MACH 1
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#define BYT_THINKPAD_10 2
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static int cht_surface_quirk_cb(const struct dmi_system_id *id)
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{
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cht_machine_id = CHT_SURFACE_MACH;
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return 1;
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}
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static int byt_thinkpad10_quirk_cb(const struct dmi_system_id *id)
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{
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cht_machine_id = BYT_THINKPAD_10;
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return 1;
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}
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static const struct dmi_system_id byt_table[] = {
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{
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.callback = byt_thinkpad10_quirk_cb,
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
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DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad 10"),
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},
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},
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{
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.callback = byt_thinkpad10_quirk_cb,
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
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DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad Tablet B"),
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},
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},
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{
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.callback = byt_thinkpad10_quirk_cb,
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
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DMI_MATCH(DMI_PRODUCT_VERSION, "Lenovo Miix 2 10"),
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},
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},
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{ }
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};
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static const struct dmi_system_id cht_table[] = {
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{
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.callback = cht_surface_quirk_cb,
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "Microsoft Corporation"),
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DMI_MATCH(DMI_PRODUCT_NAME, "Surface 3"),
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},
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},
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{ }
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};
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static struct sst_acpi_mach cht_surface_mach = {
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"10EC5640", "cht-bsw-rt5645", "intel/fw_sst_22a8.bin", "cht-bsw", NULL,
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&chv_platform_data };
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static struct sst_acpi_mach byt_thinkpad_10 = {
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"10EC5640", "cht-bsw-rt5672", "intel/fw_sst_0f28.bin", "cht-bsw", NULL,
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&byt_rvp_platform_data };
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static struct sst_acpi_mach *cht_quirk(void *arg)
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{
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struct sst_acpi_mach *mach = arg;
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|
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dmi_check_system(cht_table);
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|
|
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if (cht_machine_id == CHT_SURFACE_MACH)
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return &cht_surface_mach;
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else
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return mach;
|
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}
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|
|
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static struct sst_acpi_mach *byt_quirk(void *arg)
|
|
{
|
|
struct sst_acpi_mach *mach = arg;
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|
|
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dmi_check_system(byt_table);
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|
|
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if (cht_machine_id == BYT_THINKPAD_10)
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return &byt_thinkpad_10;
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else
|
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return mach;
|
|
}
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|
|
|
|
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static struct sst_acpi_mach sst_acpi_bytcr[] = {
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{"10EC5640", "bytcr_rt5640", "intel/fw_sst_0f28.bin", "bytcr_rt5640", byt_quirk,
|
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&byt_rvp_platform_data },
|
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{"10EC5642", "bytcr_rt5640", "intel/fw_sst_0f28.bin", "bytcr_rt5640", NULL,
|
|
&byt_rvp_platform_data },
|
|
{"INTCCFFD", "bytcr_rt5640", "intel/fw_sst_0f28.bin", "bytcr_rt5640", NULL,
|
|
&byt_rvp_platform_data },
|
|
{"10EC5651", "bytcr_rt5651", "intel/fw_sst_0f28.bin", "bytcr_rt5651", NULL,
|
|
&byt_rvp_platform_data },
|
|
{},
|
|
};
|
|
|
|
/* Cherryview-based platforms: CherryTrail and Braswell */
|
|
static struct sst_acpi_mach sst_acpi_chv[] = {
|
|
{"10EC5670", "cht-bsw-rt5672", "intel/fw_sst_22a8.bin", "cht-bsw", NULL,
|
|
&chv_platform_data },
|
|
{"10EC5645", "cht-bsw-rt5645", "intel/fw_sst_22a8.bin", "cht-bsw", NULL,
|
|
&chv_platform_data },
|
|
{"10EC5650", "cht-bsw-rt5645", "intel/fw_sst_22a8.bin", "cht-bsw", NULL,
|
|
&chv_platform_data },
|
|
{"193C9890", "cht-bsw-max98090", "intel/fw_sst_22a8.bin", "cht-bsw", NULL,
|
|
&chv_platform_data },
|
|
/* some CHT-T platforms rely on RT5640, use Baytrail machine driver */
|
|
{"10EC5640", "bytcr_rt5640", "intel/fw_sst_22a8.bin", "bytcr_rt5640", cht_quirk,
|
|
&chv_platform_data },
|
|
|
|
{},
|
|
};
|
|
|
|
static const struct acpi_device_id sst_acpi_ids[] = {
|
|
{ "80860F28", (unsigned long)&sst_acpi_bytcr},
|
|
{ "808622A8", (unsigned long) &sst_acpi_chv},
|
|
{ },
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(acpi, sst_acpi_ids);
|
|
|
|
static struct platform_driver sst_acpi_driver = {
|
|
.driver = {
|
|
.name = "intel_sst_acpi",
|
|
.acpi_match_table = ACPI_PTR(sst_acpi_ids),
|
|
.pm = &intel_sst_pm,
|
|
},
|
|
.probe = sst_acpi_probe,
|
|
.remove = sst_acpi_remove,
|
|
};
|
|
|
|
module_platform_driver(sst_acpi_driver);
|
|
|
|
MODULE_DESCRIPTION("Intel (R) SST(R) Audio Engine ACPI Driver");
|
|
MODULE_AUTHOR("Ramesh Babu K V");
|
|
MODULE_AUTHOR("Omair Mohammed Abdullah");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_ALIAS("sst");
|