169 lines
4.0 KiB
C
169 lines
4.0 KiB
C
/*
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* Intel SKL IPC Support
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*
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* Copyright (C) 2014-15, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*/
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#ifndef __SKL_IPC_H
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#define __SKL_IPC_H
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#include <linux/kthread.h>
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#include <linux/irqreturn.h>
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#include "../common/sst-ipc.h"
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struct sst_dsp;
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struct skl_sst;
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struct sst_generic_ipc;
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enum skl_ipc_pipeline_state {
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PPL_INVALID_STATE = 0,
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PPL_UNINITIALIZED = 1,
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PPL_RESET = 2,
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PPL_PAUSED = 3,
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PPL_RUNNING = 4,
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PPL_ERROR_STOP = 5,
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PPL_SAVED = 6,
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PPL_RESTORED = 7
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};
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struct skl_ipc_dxstate_info {
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u32 core_mask;
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u32 dx_mask;
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};
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struct skl_ipc_header {
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u32 primary;
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u32 extension;
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};
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#define SKL_DSP_CORES_MAX 2
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struct skl_dsp_cores {
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unsigned int count;
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enum skl_dsp_states state[SKL_DSP_CORES_MAX];
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int usage_count[SKL_DSP_CORES_MAX];
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};
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struct skl_sst {
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struct device *dev;
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struct sst_dsp *dsp;
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/* boot */
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wait_queue_head_t boot_wait;
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bool boot_complete;
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/* IPC messaging */
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struct sst_generic_ipc ipc;
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/* callback for miscbdge */
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void (*enable_miscbdcge)(struct device *dev, bool enable);
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/* Is CGCTL.MISCBDCGE disabled */
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bool miscbdcg_disabled;
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/* Populate module information */
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struct list_head uuid_list;
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/* Is firmware loaded */
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bool fw_loaded;
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/* first boot ? */
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bool is_first_boot;
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/* multi-core */
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struct skl_dsp_cores cores;
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/* tplg manifest */
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struct skl_dfw_manifest manifest;
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};
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struct skl_ipc_init_instance_msg {
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u32 module_id;
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u32 instance_id;
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u16 param_data_size;
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u8 ppl_instance_id;
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u8 core_id;
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u8 domain;
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};
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struct skl_ipc_bind_unbind_msg {
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u32 module_id;
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u32 instance_id;
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u32 dst_module_id;
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u32 dst_instance_id;
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u8 src_queue;
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u8 dst_queue;
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bool bind;
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};
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struct skl_ipc_large_config_msg {
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u32 module_id;
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u32 instance_id;
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u32 large_param_id;
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u32 param_data_size;
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};
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#define SKL_IPC_BOOT_MSECS 3000
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#define SKL_IPC_D3_MASK 0
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#define SKL_IPC_D0_MASK 3
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irqreturn_t skl_dsp_irq_thread_handler(int irq, void *context);
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int skl_ipc_create_pipeline(struct sst_generic_ipc *sst_ipc,
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u16 ppl_mem_size, u8 ppl_type, u8 instance_id);
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int skl_ipc_delete_pipeline(struct sst_generic_ipc *sst_ipc, u8 instance_id);
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int skl_ipc_set_pipeline_state(struct sst_generic_ipc *sst_ipc,
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u8 instance_id, enum skl_ipc_pipeline_state state);
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int skl_ipc_save_pipeline(struct sst_generic_ipc *ipc,
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u8 instance_id, int dma_id);
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int skl_ipc_restore_pipeline(struct sst_generic_ipc *ipc, u8 instance_id);
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int skl_ipc_init_instance(struct sst_generic_ipc *sst_ipc,
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struct skl_ipc_init_instance_msg *msg, void *param_data);
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int skl_ipc_bind_unbind(struct sst_generic_ipc *sst_ipc,
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struct skl_ipc_bind_unbind_msg *msg);
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int skl_ipc_load_modules(struct sst_generic_ipc *ipc,
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u8 module_cnt, void *data);
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int skl_ipc_unload_modules(struct sst_generic_ipc *ipc,
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u8 module_cnt, void *data);
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int skl_ipc_set_dx(struct sst_generic_ipc *ipc,
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u8 instance_id, u16 module_id, struct skl_ipc_dxstate_info *dx);
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int skl_ipc_set_large_config(struct sst_generic_ipc *ipc,
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struct skl_ipc_large_config_msg *msg, u32 *param);
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int skl_ipc_get_large_config(struct sst_generic_ipc *ipc,
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struct skl_ipc_large_config_msg *msg, u32 *param);
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int skl_sst_ipc_load_library(struct sst_generic_ipc *ipc,
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u8 dma_id, u8 table_id);
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void skl_ipc_int_enable(struct sst_dsp *dsp);
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void skl_ipc_op_int_enable(struct sst_dsp *ctx);
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void skl_ipc_op_int_disable(struct sst_dsp *ctx);
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void skl_ipc_int_disable(struct sst_dsp *dsp);
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bool skl_ipc_int_status(struct sst_dsp *dsp);
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void skl_ipc_free(struct sst_generic_ipc *ipc);
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int skl_ipc_init(struct device *dev, struct skl_sst *skl);
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void skl_clear_module_cnt(struct sst_dsp *ctx);
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#endif /* __SKL_IPC_H */
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