457 lines
11 KiB
C
457 lines
11 KiB
C
/*
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* VGICv2 MMIO handling functions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/irqchip/arm-gic.h>
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#include <linux/kvm.h>
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#include <linux/kvm_host.h>
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#include <kvm/iodev.h>
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#include <kvm/arm_vgic.h>
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#include "vgic.h"
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#include "vgic-mmio.h"
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static unsigned long vgic_mmio_read_v2_misc(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len)
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{
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u32 value;
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switch (addr & 0x0c) {
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case GIC_DIST_CTRL:
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value = vcpu->kvm->arch.vgic.enabled ? GICD_ENABLE : 0;
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break;
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case GIC_DIST_CTR:
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value = vcpu->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
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value = (value >> 5) - 1;
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value |= (atomic_read(&vcpu->kvm->online_vcpus) - 1) << 5;
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break;
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case GIC_DIST_IIDR:
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value = (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);
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break;
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default:
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return 0;
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}
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return value;
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}
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static void vgic_mmio_write_v2_misc(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len,
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unsigned long val)
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{
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struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
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bool was_enabled = dist->enabled;
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switch (addr & 0x0c) {
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case GIC_DIST_CTRL:
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dist->enabled = val & GICD_ENABLE;
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if (!was_enabled && dist->enabled)
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vgic_kick_vcpus(vcpu->kvm);
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break;
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case GIC_DIST_CTR:
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case GIC_DIST_IIDR:
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/* Nothing to do */
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return;
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}
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}
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static void vgic_mmio_write_sgir(struct kvm_vcpu *source_vcpu,
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gpa_t addr, unsigned int len,
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unsigned long val)
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{
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int nr_vcpus = atomic_read(&source_vcpu->kvm->online_vcpus);
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int intid = val & 0xf;
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int targets = (val >> 16) & 0xff;
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int mode = (val >> 24) & 0x03;
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int c;
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struct kvm_vcpu *vcpu;
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switch (mode) {
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case 0x0: /* as specified by targets */
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break;
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case 0x1:
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targets = (1U << nr_vcpus) - 1; /* all, ... */
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targets &= ~(1U << source_vcpu->vcpu_id); /* but self */
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break;
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case 0x2: /* this very vCPU only */
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targets = (1U << source_vcpu->vcpu_id);
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break;
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case 0x3: /* reserved */
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return;
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}
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kvm_for_each_vcpu(c, vcpu, source_vcpu->kvm) {
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struct vgic_irq *irq;
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if (!(targets & (1U << c)))
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continue;
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irq = vgic_get_irq(source_vcpu->kvm, vcpu, intid);
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spin_lock(&irq->irq_lock);
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irq->pending = true;
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irq->source |= 1U << source_vcpu->vcpu_id;
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vgic_queue_irq_unlock(source_vcpu->kvm, irq);
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vgic_put_irq(source_vcpu->kvm, irq);
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}
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}
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static unsigned long vgic_mmio_read_target(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len)
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{
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u32 intid = VGIC_ADDR_TO_INTID(addr, 8);
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int i;
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u64 val = 0;
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for (i = 0; i < len; i++) {
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struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
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val |= (u64)irq->targets << (i * 8);
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vgic_put_irq(vcpu->kvm, irq);
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}
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return val;
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}
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static void vgic_mmio_write_target(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len,
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unsigned long val)
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{
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u32 intid = VGIC_ADDR_TO_INTID(addr, 8);
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int i;
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/* GICD_ITARGETSR[0-7] are read-only */
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if (intid < VGIC_NR_PRIVATE_IRQS)
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return;
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for (i = 0; i < len; i++) {
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struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, NULL, intid + i);
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int target;
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spin_lock(&irq->irq_lock);
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irq->targets = (val >> (i * 8)) & 0xff;
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target = irq->targets ? __ffs(irq->targets) : 0;
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irq->target_vcpu = kvm_get_vcpu(vcpu->kvm, target);
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spin_unlock(&irq->irq_lock);
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vgic_put_irq(vcpu->kvm, irq);
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}
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}
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static unsigned long vgic_mmio_read_sgipend(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len)
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{
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u32 intid = addr & 0x0f;
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int i;
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u64 val = 0;
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for (i = 0; i < len; i++) {
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struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
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val |= (u64)irq->source << (i * 8);
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vgic_put_irq(vcpu->kvm, irq);
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}
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return val;
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}
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static void vgic_mmio_write_sgipendc(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len,
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unsigned long val)
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{
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u32 intid = addr & 0x0f;
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int i;
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for (i = 0; i < len; i++) {
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struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
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spin_lock(&irq->irq_lock);
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irq->source &= ~((val >> (i * 8)) & 0xff);
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if (!irq->source)
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irq->pending = false;
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spin_unlock(&irq->irq_lock);
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vgic_put_irq(vcpu->kvm, irq);
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}
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}
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static void vgic_mmio_write_sgipends(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len,
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unsigned long val)
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{
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u32 intid = addr & 0x0f;
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int i;
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for (i = 0; i < len; i++) {
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struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
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spin_lock(&irq->irq_lock);
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irq->source |= (val >> (i * 8)) & 0xff;
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if (irq->source) {
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irq->pending = true;
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vgic_queue_irq_unlock(vcpu->kvm, irq);
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} else {
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spin_unlock(&irq->irq_lock);
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}
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vgic_put_irq(vcpu->kvm, irq);
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}
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}
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static void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
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{
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if (kvm_vgic_global_state.type == VGIC_V2)
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vgic_v2_set_vmcr(vcpu, vmcr);
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else
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vgic_v3_set_vmcr(vcpu, vmcr);
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}
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static void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
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{
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if (kvm_vgic_global_state.type == VGIC_V2)
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vgic_v2_get_vmcr(vcpu, vmcr);
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else
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vgic_v3_get_vmcr(vcpu, vmcr);
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}
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#define GICC_ARCH_VERSION_V2 0x2
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/* These are for userland accesses only, there is no guest-facing emulation. */
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static unsigned long vgic_mmio_read_vcpuif(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len)
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{
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struct vgic_vmcr vmcr;
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u32 val;
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vgic_get_vmcr(vcpu, &vmcr);
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switch (addr & 0xff) {
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case GIC_CPU_CTRL:
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val = vmcr.ctlr;
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break;
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case GIC_CPU_PRIMASK:
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val = vmcr.pmr;
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break;
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case GIC_CPU_BINPOINT:
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val = vmcr.bpr;
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break;
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case GIC_CPU_ALIAS_BINPOINT:
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val = vmcr.abpr;
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break;
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case GIC_CPU_IDENT:
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val = ((PRODUCT_ID_KVM << 20) |
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(GICC_ARCH_VERSION_V2 << 16) |
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IMPLEMENTER_ARM);
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break;
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default:
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return 0;
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}
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return val;
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}
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static void vgic_mmio_write_vcpuif(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len,
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unsigned long val)
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{
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struct vgic_vmcr vmcr;
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vgic_get_vmcr(vcpu, &vmcr);
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switch (addr & 0xff) {
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case GIC_CPU_CTRL:
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vmcr.ctlr = val;
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break;
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case GIC_CPU_PRIMASK:
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vmcr.pmr = val;
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break;
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case GIC_CPU_BINPOINT:
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vmcr.bpr = val;
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break;
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case GIC_CPU_ALIAS_BINPOINT:
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vmcr.abpr = val;
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break;
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}
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vgic_set_vmcr(vcpu, &vmcr);
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}
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static const struct vgic_register_region vgic_v2_dist_registers[] = {
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REGISTER_DESC_WITH_LENGTH(GIC_DIST_CTRL,
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vgic_mmio_read_v2_misc, vgic_mmio_write_v2_misc, 12,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_IGROUP,
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vgic_mmio_read_rao, vgic_mmio_write_wi, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ENABLE_SET,
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vgic_mmio_read_enable, vgic_mmio_write_senable, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ENABLE_CLEAR,
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vgic_mmio_read_enable, vgic_mmio_write_cenable, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PENDING_SET,
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vgic_mmio_read_pending, vgic_mmio_write_spending, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PENDING_CLEAR,
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vgic_mmio_read_pending, vgic_mmio_write_cpending, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ACTIVE_SET,
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vgic_mmio_read_active, vgic_mmio_write_sactive, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ACTIVE_CLEAR,
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vgic_mmio_read_active, vgic_mmio_write_cactive, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PRI,
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vgic_mmio_read_priority, vgic_mmio_write_priority, 8,
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VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_TARGET,
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vgic_mmio_read_target, vgic_mmio_write_target, 8,
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VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_CONFIG,
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vgic_mmio_read_config, vgic_mmio_write_config, 2,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GIC_DIST_SOFTINT,
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vgic_mmio_read_raz, vgic_mmio_write_sgir, 4,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GIC_DIST_SGI_PENDING_CLEAR,
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vgic_mmio_read_sgipend, vgic_mmio_write_sgipendc, 16,
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VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
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REGISTER_DESC_WITH_LENGTH(GIC_DIST_SGI_PENDING_SET,
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vgic_mmio_read_sgipend, vgic_mmio_write_sgipends, 16,
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VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
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};
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static const struct vgic_register_region vgic_v2_cpu_registers[] = {
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REGISTER_DESC_WITH_LENGTH(GIC_CPU_CTRL,
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vgic_mmio_read_vcpuif, vgic_mmio_write_vcpuif, 4,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GIC_CPU_PRIMASK,
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vgic_mmio_read_vcpuif, vgic_mmio_write_vcpuif, 4,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GIC_CPU_BINPOINT,
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vgic_mmio_read_vcpuif, vgic_mmio_write_vcpuif, 4,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GIC_CPU_ALIAS_BINPOINT,
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vgic_mmio_read_vcpuif, vgic_mmio_write_vcpuif, 4,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GIC_CPU_ACTIVEPRIO,
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vgic_mmio_read_raz, vgic_mmio_write_wi, 16,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GIC_CPU_IDENT,
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vgic_mmio_read_vcpuif, vgic_mmio_write_vcpuif, 4,
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VGIC_ACCESS_32bit),
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};
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unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev)
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{
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dev->regions = vgic_v2_dist_registers;
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dev->nr_regions = ARRAY_SIZE(vgic_v2_dist_registers);
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kvm_iodevice_init(&dev->dev, &kvm_io_gic_ops);
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return SZ_4K;
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}
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int vgic_v2_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr)
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{
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int nr_irqs = dev->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
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const struct vgic_register_region *regions;
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gpa_t addr;
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int nr_regions, i, len;
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addr = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK;
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switch (attr->group) {
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case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
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regions = vgic_v2_dist_registers;
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nr_regions = ARRAY_SIZE(vgic_v2_dist_registers);
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break;
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case KVM_DEV_ARM_VGIC_GRP_CPU_REGS:
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regions = vgic_v2_cpu_registers;
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nr_regions = ARRAY_SIZE(vgic_v2_cpu_registers);
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break;
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default:
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return -ENXIO;
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}
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/* We only support aligned 32-bit accesses. */
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if (addr & 3)
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return -ENXIO;
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for (i = 0; i < nr_regions; i++) {
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if (regions[i].bits_per_irq)
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len = (regions[i].bits_per_irq * nr_irqs) / 8;
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else
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len = regions[i].len;
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if (regions[i].reg_offset <= addr &&
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regions[i].reg_offset + len > addr)
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return 0;
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}
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return -ENXIO;
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}
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/*
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* When userland tries to access the VGIC register handlers, we need to
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* create a usable struct vgic_io_device to be passed to the handlers and we
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* have to set up a buffer similar to what would have happened if a guest MMIO
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* access occurred, including doing endian conversions on BE systems.
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*/
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static int vgic_uaccess(struct kvm_vcpu *vcpu, struct vgic_io_device *dev,
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bool is_write, int offset, u32 *val)
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{
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unsigned int len = 4;
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u8 buf[4];
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int ret;
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if (is_write) {
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vgic_data_host_to_mmio_bus(buf, len, *val);
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ret = kvm_io_gic_ops.write(vcpu, &dev->dev, offset, len, buf);
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} else {
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ret = kvm_io_gic_ops.read(vcpu, &dev->dev, offset, len, buf);
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if (!ret)
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*val = vgic_data_mmio_bus_to_host(buf, len);
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}
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return ret;
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}
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int vgic_v2_cpuif_uaccess(struct kvm_vcpu *vcpu, bool is_write,
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int offset, u32 *val)
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{
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struct vgic_io_device dev = {
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.regions = vgic_v2_cpu_registers,
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.nr_regions = ARRAY_SIZE(vgic_v2_cpu_registers),
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.iodev_type = IODEV_CPUIF,
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};
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return vgic_uaccess(vcpu, &dev, is_write, offset, val);
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}
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int vgic_v2_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
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int offset, u32 *val)
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{
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struct vgic_io_device dev = {
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.regions = vgic_v2_dist_registers,
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.nr_regions = ARRAY_SIZE(vgic_v2_dist_registers),
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.iodev_type = IODEV_DIST,
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};
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return vgic_uaccess(vcpu, &dev, is_write, offset, val);
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}
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