192 lines
6.5 KiB
Plaintext
192 lines
6.5 KiB
Plaintext
Device tree binding for NVIDIA Tegra186 XUSB PADCTL
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========================================================
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The Tegra186 XUSB PADCTL manages UTMI/HSIC/SuperSpeed USB 2.0/3.0 pads, each of
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which can be configured with one out of HOST_ONLY/DEVICE_ONLY/OTG capabilities.
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This document defines the device-specific binding for the Tegra186 PADCTL driver.
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This driver models pads and lanes as phy instances with the generic phy
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abstraction. Function drivers (XHCI/XUDC drivers) could retrieve its own
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phy instance via devm_phy_get() call.
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Refer to pinctrl-bindings.txt in this directory for generic information about
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pin controller device tree bindings and ../phy/phy-bindings.txt for details on
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how to describe and reference PHYs in device trees.
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Required properties:
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--------------------
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- compatible: should be "nvidia,tegra186-xusb-padctl"
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- reg: Physical base address and length of PADCTL.
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- interrupts: IRQ number of PADCTL.
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- #phy-cells: Should be 1. The specifier is the index of the PHY to reference.
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See <dt-bindings/pinctrl/pinctrl-tegra-padctl.h> for the list of valid values.
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- mboxes: Must contain an entry for the XUSB mailbox channel.
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See ../mailbox/mailbox.txt for details.
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- mbox-names: Must include the following entries:
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- xusb
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Optional properties:
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-------------------
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- vbus-{0,1,2}-supply: VBUS regulator for the corresponding UTMI pad.
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- vddio-hsic-supply: VDDIO regulator for the HSIC pads.
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- pinctrl-{1,}: For over-current support, we have to specify 3 different
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pinctrl states for each VBUS_EN pin in sequence of "sfio tristate state",
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"sfio passthrough state" and "default state", for setting over-current support
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with VBUS_EN as tristate and passthrough states,and to restore to its default
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state. For example, if there are 2 VBUS_EN pins, we should set pinctrl-1 to
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pinctrl-6 as:
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1:pin 0 sfio tristate state,
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2:pin 1 sfio tristate state,
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3:pin 0 sfio passthrough state,
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4:pin 1 sfio passthrough state,
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5:pin 0 default state,
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6:pin 1 default state.
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- pinctrl-names: should be set to vbus_en0_sfio, vbus_en0_default,
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vbus_en1_sfio, vbus_en1_default, ... up to the highest supported pin number.
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The first pinctrl-names item should be "default" since pinctrl-0 is used for
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XUSB ports, not for VBUS_ENx pins.
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Lane muxing:
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------------
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Child nodes contain the pinmux configurations following the conventions from
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the pinctrl-bindings.txt document. Typically a single, static configuration is
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given and applied at boot time.
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Each subnode describes groups of lanes along with parameters and pads that
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they should be assigned to. The name of these subnodes is not important. All
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subnodes should be parsed solely based on their content.
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Each subnode only applies the parameters that are explicitly listed. In other
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words, if a subnode that lists a function but no pin configuration parameters
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implies no information about any pin configuration parameters. Similarly, a
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subnode that describes only a parameter implies no information about what
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function the pins are assigned to.
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Required properties:
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- nvidia,lanes: An array of strings. Each string is the name of a lane.
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Optional properties:
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- nvidia,function: A string that is the name of the function (pad) that the
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pin or group should be assigned to. Valid values for function names are
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listed below.
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- nvidia,usb3-port: USB3 port (0/1/2) to which the lane is mapped.
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- nvidia,port-cap: USB port capability.
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Note that not all of these properties are valid for all lanes. Lanes can be
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divided into four groups:
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- otg-0, otg-1, otg-2:
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Valid functions for this group are: "xusb", "uart", "rsvd".
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nvidia,port-cap property is required when the function is xusb.
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- hsic-0:
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Valid functions for this group are: "xusb", "rsvd".
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- usb3-0, usb3-1, usb3-2:
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Do not set function for this group.
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nvidia,port-cap is required.
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- cdp-0, cdp-1, cdp-2:
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Valid functions for this group is: "xusb". No other property is required.
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This type of lane is an abstraction of Tegra CDP (charging downstream port)
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which can be turned on by host controller driver using generic phy API to
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declare a UTMI host port as CDP.
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- nvidia,oc-pin: the overcurrent VBUS pin (should be >=0) the lane is using.
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When this property is specified, the corresponding OC pin will be monitored
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and if overcurrent event happens, the pad associated with this lane will be
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reported. Overcurrent support is default disabled if this property is absent.
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Example:
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========
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SoC file extract:
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-----------------
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pinctrl@0x03520000 {
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compatible = "nvidia,tegra186-xusb-padctl";
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reg = <0x0 0x03520000 0x0 0x1000>,
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<0x0 0x02500000 0x0 0xa0000>;
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interrupts = <0 167 0x4>;
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mboxes = <&xusb_mbox>;
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mbox-names = "xusb";
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#phy-cells = <1>;
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};
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Board file extract:
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-------------------
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# XUSB host mode takes UTMI pad#2 and SuperSpeed pad#2 for a USB 3.0 host
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# port. Also add CDP support for that UTMI pad#2.
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xhci@0x03530000 {
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...
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phys = <&board-padctl TEGRA_PADCTL_PHY_UTMI_P(2)>,
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<&board-padctl TEGRA_PADCTL_PHY_USB3_P(2)>,
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<&board-padctl TEGRA_PADCTL_PHY_CDP_P(2)>;
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phy-names = "utmi-2", "usb3-2", "cdp-2";
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...
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}
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...
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# XUSB device mode takes UTMI pad#0 and SuperSpeed pad#0 for a USB3.0 device port
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xudc@0x03550000 {
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...
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phys = <&board-padctl TEGRA_PADCTL_PHY_UTMI_P(0)>,
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<&board-padctl TEGRA_PADCTL_PHY_USB3_P(0)>,
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phy-names = "usb2", "usb3";
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...
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}
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board-padctl: pinctrl@0x03520000 {
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pinctrl-0 = <&tegra_xusb_padctl_pinmux_default>;
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pinctrl-1 = <&vbus_en0_sfio_tristate_state>;
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pinctrl-2 = <&vbus_en1_sfio_tristate_state>;
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pinctrl-3 = <&vbus_en0_sfio_passthrough_state>;
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pinctrl-4 = <&vbus_en1_sfio_passthrough_state>;
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pinctrl-5 = <&vbus_en0_default_state>;
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pinctrl-6 = <&vbus_en1_default_state>;
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pinctrl-names = "default",
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"vbus_en0_sfio_tristate", "vbus_en1_sfio_tristate",
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"vbus_en0_sfio_passthrough", "vbus_en1_sfio_passthrough",
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"vbus_en0_default", "vbus_en1_default";
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vbus-2-supply = <&vdd_usb3_vbus>;
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pinctrl_default: pinmux {
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usb2-micro-AB {
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nvidia,lanes = "otg-0";
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nvidia,function = "xusb";
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nvidia,port-cap = <TEGRA_PADCTL_PORT_OTG_CAP>;
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nvidia,oc-pin = <0>;
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};
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usb3-micro-AB {
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nvidia,lanes = "usb3-0";
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nvidia,port-cap = <TEGRA_PADCTL_PORT_OTG_CAP>;
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nvidia,oc-pin = <0>;
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};
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usb2-std-A {
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nvidia,lanes = "otg-2";
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nvidia,function = "xusb";
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nvidia,port-cap = <TEGRA_PADCTL_PORT_HOST_ONLY>;
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nvidia,oc-pin = <1>;
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};
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usb3-std-A {
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nvidia,lanes = "usb3-2";
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nvidia,port-cap = <TEGRA_PADCTL_PORT_HOST_ONLY>;
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nvidia,oc-pin = <1>;
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};
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};
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};
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