805 lines
13 KiB
C
805 lines
13 KiB
C
/*
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* Tegra194 MC StreamID configuration
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*
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* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#define pr_fmt(fmt) "%s(): " fmt, __func__
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#include <linux/err.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/platform/tegra/tegra-mc-sid.h>
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#include <dt-bindings/memory/tegra-swgroup.h>
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#include <dt-bindings/memory/tegra194-swgroup.h>
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enum override_id {
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PTCR,
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HDAR,
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HOST1XDMAR,
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NVENCSRD,
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SATAR,
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MPCORER,
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NVENCSWR,
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HDAW,
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MPCOREW,
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SATAW,
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ISPRA,
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ISPFALR,
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ISPWA,
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ISPWB,
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XUSB_HOSTR,
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XUSB_HOSTW,
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XUSB_DEVR,
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XUSB_DEVW,
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TSECSRD,
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TSECSWR,
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SDMMCRA,
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SDMMCR,
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SDMMCRAB,
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SDMMCWA,
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SDMMCW,
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SDMMCWAB,
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VICSRD,
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VICSWR,
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VIW,
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NVDECSRD,
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NVDECSWR,
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APER,
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APEW,
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NVJPGSRD,
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NVJPGSWR,
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SESRD,
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SESWR,
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AXIAPR,
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AXIAPW,
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ETRR,
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ETRW,
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TSECSRDB,
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TSECSWRB,
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AXISR,
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AXISW,
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EQOSR,
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EQOSW,
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UFSHCR,
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UFSHCW,
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NVDISPLAYR,
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BPMPR,
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BPMPW,
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BPMPDMAR,
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BPMPDMAW,
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AONR,
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AONW,
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AONDMAR,
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AONDMAW,
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SCER,
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SCEW,
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SCEDMAR,
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SCEDMAW,
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APEDMAR,
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APEDMAW,
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NVDISPLAYR1,
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VICSRD1,
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NVDECSRD1,
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MIU0R,
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MIU0W,
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MIU1R,
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MIU1W,
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MIU2R,
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MIU2W,
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MIU3R,
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MIU3W,
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VIFALR,
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VIFALW,
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DLA0RDA,
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DLA0FALRDB,
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DLA0WRA,
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DLA0FALWRB,
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DLA1RDA,
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DLA1FALRDB,
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DLA1WRA,
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DLA1FALWRB,
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PVA0RDA,
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PVA0RDB,
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PVA0RDC,
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PVA0WRA,
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PVA0WRB,
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PVA0WRC,
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PVA1RDA,
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PVA1RDB,
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PVA1RDC,
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PVA1WRA,
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PVA1WRB,
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PVA1WRC,
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RCER,
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RCEW,
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RCEDMAR,
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RCEDMAW,
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NVENC1SRD,
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NVENC1SWR,
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PCIE0R,
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PCIE0W,
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PCIE1R,
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PCIE1W,
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PCIE2AR,
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PCIE2AW,
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PCIE3R,
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PCIE3W,
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PCIE4R,
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PCIE4W,
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PCIE5R,
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PCIE5W,
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ISPFALW,
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DLA0RDA1,
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DLA1RDA1,
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PVA0RDA1,
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PVA0RDB1,
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PVA1RDA1,
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PVA1RDB1,
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PCIE5R1,
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NVENCSRD1,
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NVENC1SRD1,
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ISPRA1,
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PCIE0R1,
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NVDEC1SRD,
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NVDEC1SRD1,
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NVDEC1SWR,
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MAX_OID,
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};
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static struct sid_override_reg sid_override_reg[] = {
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DEFREG(PTCR, 0x000),
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DEFREG(HDAR, 0x0A8),
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DEFREG(HOST1XDMAR, 0x0B0),
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DEFREG(NVENCSRD, 0x0E0),
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DEFREG(SATAR, 0x0F8),
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DEFREG(MPCORER, 0x138),
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DEFREG(NVENCSWR, 0x158),
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DEFREG(HDAW, 0x1A8),
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DEFREG(MPCOREW, 0x1C8),
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DEFREG(SATAW, 0x1E8),
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DEFREG(ISPRA, 0x220),
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DEFREG(ISPFALR, 0x228),
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DEFREG(ISPWA, 0x230),
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DEFREG(ISPWB, 0x238),
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DEFREG(XUSB_HOSTR, 0x250),
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DEFREG(XUSB_HOSTW, 0x258),
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DEFREG(XUSB_DEVR, 0x260),
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DEFREG(XUSB_DEVW, 0x268),
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DEFREG(TSECSRD, 0x2A0),
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DEFREG(TSECSWR, 0x2A8),
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DEFREG(SDMMCRA, 0x300),
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DEFREG(SDMMCR, 0x310),
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DEFREG(SDMMCRAB, 0x318),
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DEFREG(SDMMCWA, 0x320),
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DEFREG(SDMMCW, 0x330),
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DEFREG(SDMMCWAB, 0x338),
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DEFREG(VICSRD, 0x360),
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DEFREG(VICSWR, 0x368),
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DEFREG(VIW, 0x390),
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DEFREG(NVDECSRD, 0x3C0),
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DEFREG(NVDECSWR, 0x3C8),
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DEFREG(APER, 0x3D0),
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DEFREG(APEW, 0x3D8),
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DEFREG(NVJPGSRD, 0x3F0),
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DEFREG(NVJPGSWR, 0x3F8),
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DEFREG(SESRD, 0x400),
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DEFREG(SESWR, 0x408),
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DEFREG(AXIAPR, 0x410),
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DEFREG(AXIAPW, 0x418),
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DEFREG(ETRR, 0x420),
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DEFREG(ETRW, 0x428),
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DEFREG(TSECSRDB, 0x430),
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DEFREG(TSECSWRB, 0x438),
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DEFREG(AXISR, 0x460),
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DEFREG(AXISW, 0x468),
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DEFREG(EQOSR, 0x470),
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DEFREG(EQOSW, 0x478),
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DEFREG(UFSHCR, 0x480),
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DEFREG(UFSHCW, 0x488),
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DEFREG(NVDISPLAYR, 0x490),
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DEFREG(BPMPR, 0x498),
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DEFREG(BPMPW, 0x4A0),
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DEFREG(BPMPDMAR, 0x4A8),
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DEFREG(BPMPDMAW, 0x4B0),
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DEFREG(AONR, 0x4B8),
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DEFREG(AONW, 0x4C0),
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DEFREG(AONDMAR, 0x4C8),
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DEFREG(AONDMAW, 0x4D0),
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DEFREG(SCER, 0x4D8),
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DEFREG(SCEW, 0x4E0),
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DEFREG(SCEDMAR, 0x4E8),
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DEFREG(SCEDMAW, 0x4F0),
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DEFREG(APEDMAR, 0x4F8),
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DEFREG(APEDMAW, 0x500),
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DEFREG(NVDISPLAYR1, 0x508),
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DEFREG(VICSRD1, 0x510),
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DEFREG(NVDECSRD1, 0x518),
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DEFREG(MIU0R, 0x530),
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DEFREG(MIU0W, 0x538),
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DEFREG(MIU1R, 0x540),
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DEFREG(MIU1W, 0x548),
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DEFREG(MIU2R, 0x570),
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DEFREG(MIU2W, 0x578),
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DEFREG(MIU3R, 0x580),
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DEFREG(MIU3W, 0x588),
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DEFREG(VIFALR, 0x5E0),
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DEFREG(VIFALW, 0x5E8),
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DEFREG(DLA0RDA, 0x5F0),
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DEFREG(DLA0FALRDB, 0x5F8),
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DEFREG(DLA0WRA, 0x600),
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DEFREG(DLA0FALWRB, 0x608),
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DEFREG(DLA1RDA, 0x610),
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DEFREG(DLA1FALRDB, 0x618),
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DEFREG(DLA1WRA, 0x620),
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DEFREG(DLA1FALWRB, 0x628),
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DEFREG(PVA0RDA, 0x630),
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DEFREG(PVA0RDB, 0x638),
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DEFREG(PVA0RDC, 0x640),
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DEFREG(PVA0WRA, 0x648),
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DEFREG(PVA0WRB, 0x650),
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DEFREG(PVA0WRC, 0x658),
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DEFREG(PVA1RDA, 0x660),
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DEFREG(PVA1RDB, 0x668),
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DEFREG(PVA1RDC, 0x670),
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DEFREG(PVA1WRA, 0x678),
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DEFREG(PVA1WRB, 0x680),
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DEFREG(PVA1WRC, 0x688),
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DEFREG(RCER, 0x690),
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DEFREG(RCEW, 0x698),
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DEFREG(RCEDMAR, 0x6A0),
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DEFREG(RCEDMAW, 0x6A8),
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DEFREG(NVENC1SRD, 0x6B0),
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DEFREG(NVENC1SWR, 0x6B8),
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DEFREG(PCIE0R, 0x6C0),
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DEFREG(PCIE0W, 0x6C8),
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DEFREG(PCIE1R, 0x6D0),
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DEFREG(PCIE1W, 0x6D8),
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DEFREG(PCIE2AR, 0x6E0),
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DEFREG(PCIE2AW, 0x6E8),
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DEFREG(PCIE3R, 0x6F0),
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DEFREG(PCIE3W, 0x6F8),
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DEFREG(PCIE4R, 0x700),
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DEFREG(PCIE4W, 0x708),
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DEFREG(PCIE5R, 0x710),
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DEFREG(PCIE5W, 0x718),
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DEFREG(ISPFALW, 0x720),
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DEFREG(DLA0RDA1, 0x748),
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DEFREG(DLA1RDA1, 0x750),
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DEFREG(PVA0RDA1, 0x758),
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DEFREG(PVA0RDB1, 0x760),
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DEFREG(PVA1RDA1, 0x768),
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DEFREG(PVA1RDB1, 0x770),
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DEFREG(PCIE5R1, 0x778),
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DEFREG(NVENCSRD1, 0x780),
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DEFREG(NVENC1SRD1, 0x788),
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DEFREG(ISPRA1, 0x790),
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DEFREG(PCIE0R1, 0x798),
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DEFREG(NVDEC1SRD, 0x7C8),
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DEFREG(NVDEC1SRD1, 0x7D0),
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DEFREG(NVDEC1SWR, 0x7D8),
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};
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static struct sid_to_oids sid_to_oids[] = {
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{
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.sid = TEGRA_SID_HDA,
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.noids = 2,
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.oid = {
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HDAR,
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HDAW,
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},
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.ord = OVERRIDE,
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.name = "HDA",
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},
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{
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.sid = TEGRA_SID_SATA2,
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.noids = 2,
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.oid = {
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SATAR,
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SATAW,
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},
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.ord = OVERRIDE,
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.name = "SATA2",
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},
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{
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.sid = TEGRA_SID_XUSB_HOST,
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.noids = 2,
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.oid = {
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XUSB_HOSTR,
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XUSB_HOSTW,
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},
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.ord = OVERRIDE,
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.name = "XUSB_HOST",
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},
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{
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.sid = TEGRA_SID_XUSB_DEV,
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.noids = 2,
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.oid = {
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XUSB_DEVR,
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XUSB_DEVW,
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},
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.ord = OVERRIDE,
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.name = "XUSB_DEV",
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},
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{
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.sid = TEGRA_SID_TSEC,
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.noids = 2,
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.oid = {
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TSECSRD,
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TSECSWR,
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},
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.ord = SIM_OVERRIDE,
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.name = "TSEC",
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},
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{
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.sid = TEGRA_SID_SDMMC1A,
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.noids = 2,
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.oid = {
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SDMMCRA,
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SDMMCWA,
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},
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.ord = OVERRIDE,
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.name = "SDMMC1A",
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},
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{
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.sid = TEGRA_SID_SDMMC3A,
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.noids = 2,
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.oid = {
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SDMMCR,
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SDMMCW,
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},
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.ord = OVERRIDE,
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.name = "SDMMC3A",
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},
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{
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.sid = TEGRA_SID_SDMMC4A,
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.noids = 2,
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.oid = {
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SDMMCRAB,
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SDMMCWAB,
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},
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.ord = OVERRIDE,
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.name = "SDMMC4A",
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},
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{
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.sid = TEGRA_SID_APE,
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.noids = 4,
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.oid = {
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APER,
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APEW,
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APEDMAR,
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APEDMAW,
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},
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.ord = NO_OVERRIDE,
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.name = "APE",
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},
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{
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.sid = TEGRA_SID_SE,
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.noids = 2,
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.oid = {
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SESRD,
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SESWR,
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},
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.ord = NO_OVERRIDE,
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.name = "SE",
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},
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{
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.sid = TEGRA_SID_ETR,
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.noids = 2,
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.oid = {
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ETRR,
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ETRW,
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},
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.ord = OVERRIDE,
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.name = "ETR",
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},
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{
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.sid = TEGRA_SID_TSECB,
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.noids = 2,
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.oid = {
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TSECSRDB,
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TSECSWRB,
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},
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.ord = SIM_OVERRIDE,
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.name = "TSECB",
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},
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{
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.sid = TEGRA_SID_GPCDMA_0, /* AXIS */
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.noids = 2,
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.oid = {
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AXISR,
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AXISW,
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},
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.ord = NO_OVERRIDE,
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.name = "GPCDMA",
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},
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{
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.sid = TEGRA_SID_EQOS,
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.noids = 2,
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.oid = {
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EQOSR,
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EQOSW,
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},
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.ord = OVERRIDE,
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.name = "EQOS",
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},
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{
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.sid = TEGRA_SID_UFSHC,
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.noids = 2,
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.oid = {
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UFSHCR,
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UFSHCW,
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},
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.ord = OVERRIDE,
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.name = "UFSHC",
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},
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{
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.sid = TEGRA_SID_NVDISPLAY,
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.noids = 2,
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.oid = {
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NVDISPLAYR,
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NVDISPLAYR1,
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},
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.ord = OVERRIDE,
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.name = "NVDISPLAY",
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},
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{
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.sid = TEGRA_SID_BPMP,
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.noids = 4,
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.oid = {
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BPMPR,
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BPMPW,
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BPMPDMAR,
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BPMPDMAW,
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},
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.ord = NO_OVERRIDE,
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.name = "BPMP",
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},
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{
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.sid = TEGRA_SID_AON,
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.noids = 4,
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.oid = {
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AONR,
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AONW,
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AONDMAR,
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AONDMAW,
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},
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.ord = NO_OVERRIDE,
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.name = "AON",
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},
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{
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.sid = TEGRA_SID_SCE,
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.noids = 4,
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.oid = {
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SCER,
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SCEW,
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SCEDMAR,
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SCEDMAW,
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},
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.ord = NO_OVERRIDE,
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.name = "SCE",
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},
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{
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.sid = TEGRA_SID_HC,
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.noids = 1,
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.oid = {
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HOST1XDMAR,
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},
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.ord = NO_OVERRIDE,
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.name = "HC",
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},
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{
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.sid = TEGRA_SID_VIC,
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.noids = 3,
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.oid = {
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VICSRD1,
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VICSRD,
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VICSWR,
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},
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.ord = NO_OVERRIDE,
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.name = "VIC",
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},
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{
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.sid = TEGRA_SID_VI,
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.noids = 1,
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.oid = {
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VIW,
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},
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.ord = NO_OVERRIDE,
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.name = "VI",
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},
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{
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.sid = TEGRA_SID_VIFALC,
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.noids = 2,
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.oid = {
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VIFALR,
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VIFALW,
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},
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.ord = NO_OVERRIDE,
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.name = "VIFALC",
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},
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{
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.sid = TEGRA_SID_ISP,
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|
.noids = 6,
|
|
.oid = {
|
|
ISPRA,
|
|
ISPWA,
|
|
ISPWB,
|
|
ISPFALR,
|
|
ISPFALW,
|
|
ISPRA1,
|
|
},
|
|
.ord = NO_OVERRIDE,
|
|
.name = "ISP",
|
|
},
|
|
{
|
|
.sid = TEGRA_SID_NVDEC,
|
|
.noids = 3,
|
|
.oid = {
|
|
NVDECSRD1,
|
|
NVDECSRD,
|
|
NVDECSWR,
|
|
},
|
|
.ord = NO_OVERRIDE,
|
|
.name = "NVDEC",
|
|
},
|
|
{
|
|
.sid = TEGRA_SID_NVENC,
|
|
.noids = 3,
|
|
.oid = {
|
|
NVENCSRD,
|
|
NVENCSWR,
|
|
NVENCSRD1,
|
|
},
|
|
.ord = NO_OVERRIDE,
|
|
.name = "NVENC",
|
|
},
|
|
{
|
|
.sid = TEGRA_SID_NVJPG,
|
|
.noids = 2,
|
|
.oid = {
|
|
NVJPGSRD,
|
|
NVJPGSWR,
|
|
},
|
|
.ord = NO_OVERRIDE,
|
|
.name = "NVJPG",
|
|
},
|
|
{
|
|
.sid = TEGRA_SID_MIU,
|
|
.noids = 8,
|
|
.oid = {
|
|
MIU0R,
|
|
MIU0W,
|
|
MIU1R,
|
|
MIU1W,
|
|
MIU2R,
|
|
MIU2W,
|
|
MIU3R,
|
|
MIU3W,
|
|
},
|
|
.ord = SIM_OVERRIDE,
|
|
.name = "MIU",
|
|
},
|
|
{
|
|
.sid = TEGRA_SID_NVDLA0,
|
|
.noids = 5,
|
|
.oid = {
|
|
DLA0RDA,
|
|
DLA0FALRDB,
|
|
DLA0WRA,
|
|
DLA0FALWRB,
|
|
DLA0RDA1,
|
|
},
|
|
.ord = SIM_OVERRIDE,
|
|
.name = "NVDLA0",
|
|
},
|
|
{
|
|
.sid = TEGRA_SID_NVDLA1,
|
|
.noids = 5,
|
|
.oid = {
|
|
DLA1RDA,
|
|
DLA1FALRDB,
|
|
DLA1WRA,
|
|
DLA1FALWRB,
|
|
DLA1RDA1,
|
|
},
|
|
.ord = SIM_OVERRIDE,
|
|
.name = "NVDLA1",
|
|
},
|
|
{
|
|
.sid = TEGRA_SID_PVA0,
|
|
.noids = 8,
|
|
.oid = {
|
|
PVA0RDA,
|
|
PVA0RDB,
|
|
PVA0RDC,
|
|
PVA0WRA,
|
|
PVA0WRB,
|
|
PVA0WRC,
|
|
PVA0RDA1,
|
|
PVA0RDB1,
|
|
},
|
|
.ord = SIM_OVERRIDE,
|
|
.name = "PVA0",
|
|
},
|
|
{
|
|
.sid = TEGRA_SID_PVA1,
|
|
.noids = 8,
|
|
.oid = {
|
|
PVA1RDA,
|
|
PVA1RDB,
|
|
PVA1RDC,
|
|
PVA1WRA,
|
|
PVA1WRB,
|
|
PVA1WRC,
|
|
PVA1RDA1,
|
|
PVA1RDB1,
|
|
},
|
|
.ord = SIM_OVERRIDE,
|
|
.name = "PVA1",
|
|
},
|
|
{
|
|
.sid = TEGRA_SID_RCE,
|
|
.noids = 4,
|
|
.oid = {
|
|
RCER,
|
|
RCEW,
|
|
RCEDMAR,
|
|
RCEDMAW,
|
|
},
|
|
.ord = NO_OVERRIDE,
|
|
.name = "RCE",
|
|
},
|
|
{
|
|
.sid = TEGRA_SID_NVENC1,
|
|
.noids = 3,
|
|
.oid = {
|
|
NVENC1SRD,
|
|
NVENC1SWR,
|
|
NVENC1SRD1,
|
|
},
|
|
.ord = SIM_OVERRIDE,
|
|
.name = "NVENC1",
|
|
},
|
|
{
|
|
.sid = TEGRA_SID_PCIE0,
|
|
.noids = 3,
|
|
.oid = {
|
|
PCIE0R,
|
|
PCIE0W,
|
|
PCIE0R1,
|
|
},
|
|
.ord = SIM_OVERRIDE,
|
|
.name = "PCIE0",
|
|
},
|
|
{
|
|
.sid = TEGRA_SID_PCIE1,
|
|
.noids = 2,
|
|
.oid = {
|
|
PCIE1R,
|
|
PCIE1W,
|
|
},
|
|
.ord = SIM_OVERRIDE,
|
|
.name = "PCIE1",
|
|
},
|
|
{
|
|
.sid = TEGRA_SID_PCIE2,
|
|
.noids = 2,
|
|
.oid = {
|
|
PCIE2AR,
|
|
PCIE2AW,
|
|
},
|
|
.ord = SIM_OVERRIDE,
|
|
.name = "PCIE2",
|
|
},
|
|
{
|
|
.sid = TEGRA_SID_PCIE3,
|
|
.noids = 2,
|
|
.oid = {
|
|
PCIE3R,
|
|
PCIE3W,
|
|
},
|
|
.ord = SIM_OVERRIDE,
|
|
.name = "PCIE3",
|
|
},
|
|
{
|
|
.sid = TEGRA_SID_PCIE4,
|
|
.noids = 2,
|
|
.oid = {
|
|
PCIE4R,
|
|
PCIE4W,
|
|
},
|
|
.ord = SIM_OVERRIDE,
|
|
.name = "PCIE4",
|
|
},
|
|
{
|
|
.sid = TEGRA_SID_PCIE5,
|
|
.noids = 3,
|
|
.oid = {
|
|
PCIE5R,
|
|
PCIE5W,
|
|
PCIE5R1,
|
|
},
|
|
.ord = SIM_OVERRIDE,
|
|
.name = "PCIE5",
|
|
},
|
|
{
|
|
.sid = TEGRA_SID_NVDEC1,
|
|
.noids = 3,
|
|
.oid = {
|
|
NVDEC1SRD,
|
|
NVDEC1SRD1,
|
|
NVDEC1SWR,
|
|
},
|
|
.ord = SIM_OVERRIDE,
|
|
.name = "NVDEC1",
|
|
},
|
|
};
|
|
|
|
static const struct tegra_mc_sid_soc_data tegra194_mc_soc_data = {
|
|
.sid_override_reg = sid_override_reg,
|
|
.nsid_override_reg = ARRAY_SIZE(sid_override_reg),
|
|
.sid_to_oids = sid_to_oids,
|
|
.nsid_to_oids = ARRAY_SIZE(sid_to_oids),
|
|
.max_oids = MAX_OID,
|
|
};
|
|
|
|
static int tegra194_mc_sid_probe(struct platform_device *pdev)
|
|
{
|
|
return tegra_mc_sid_probe(pdev, &tegra194_mc_soc_data);
|
|
}
|
|
|
|
static const struct of_device_id tegra194_mc_sid_of_match[] = {
|
|
{ .compatible = "nvidia,tegra194-mc-sid", },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, tegra194_mc_sid_of_match);
|
|
|
|
static struct platform_driver tegra194_mc_sid_driver = {
|
|
.probe = tegra194_mc_sid_probe,
|
|
.remove = tegra_mc_sid_remove,
|
|
.driver = {
|
|
.owner = THIS_MODULE,
|
|
.name = "tegra194-mc-sid",
|
|
.of_match_table = of_match_ptr(tegra194_mc_sid_of_match),
|
|
},
|
|
};
|
|
|
|
static int __init tegra194_mc_sid_init(void)
|
|
{
|
|
struct device_node *np;
|
|
struct platform_device *pdev = NULL;
|
|
|
|
np = of_find_compatible_node(NULL, NULL, "nvidia,tegra194-mc-sid");
|
|
if (np) {
|
|
pdev = of_platform_device_create(np, NULL,
|
|
platform_bus_type.dev_root);
|
|
of_node_put(np);
|
|
}
|
|
|
|
if (IS_ERR_OR_NULL(pdev))
|
|
return -ENODEV;
|
|
|
|
return platform_driver_register(&tegra194_mc_sid_driver);
|
|
}
|
|
arch_initcall(tegra194_mc_sid_init);
|
|
|
|
MODULE_DESCRIPTION("MC StreamID configuration");
|
|
MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>, Pritesh Raithatha <praithatha@nvidia.com>");
|
|
MODULE_LICENSE("GPL v2");
|