498 lines
11 KiB
C
498 lines
11 KiB
C
/*
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* dev.c
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*
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* A device driver for ADSP and APE
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*
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* Copyright (C) 2014-2018, NVIDIA Corporation. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/platform_device.h>
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#include <linux/fs.h>
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#include <linux/platform_device.h>
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#include <linux/miscdevice.h>
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#include <linux/pm.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/io.h>
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#include <linux/tegra_nvadsp.h>
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#include <soc/tegra/chip-id.h>
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#include <linux/pm_runtime.h>
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#include <linux/tegra_pm_domains.h>
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#include <linux/clk/tegra.h>
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#include <linux/delay.h>
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#include <asm/arch_timer.h>
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#include <linux/irqchip/tegra-agic.h>
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#include "dev.h"
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#include "os.h"
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#include "amc.h"
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#include "ape_actmon.h"
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#include "aram_manager.h"
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#include "dev-t21x.h"
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#include "dev-t18x.h"
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static struct nvadsp_drv_data *nvadsp_drv_data;
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#ifdef CONFIG_DEBUG_FS
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static int __init adsp_debug_init(struct nvadsp_drv_data *drv_data)
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{
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drv_data->adsp_debugfs_root = debugfs_create_dir("tegra_ape", NULL);
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if (!drv_data->adsp_debugfs_root)
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return -ENOMEM;
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return 0;
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}
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#endif /* CONFIG_DEBUG_FS */
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#ifdef CONFIG_PM
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static int nvadsp_runtime_resume(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct nvadsp_drv_data *drv_data = platform_get_drvdata(pdev);
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int ret = -EINVAL;
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if (drv_data->runtime_resume)
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ret = drv_data->runtime_resume(dev);
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return ret;
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}
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static int nvadsp_runtime_suspend(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct nvadsp_drv_data *drv_data = platform_get_drvdata(pdev);
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int ret = -EINVAL;
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if (drv_data->runtime_suspend)
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ret = drv_data->runtime_suspend(dev);
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return ret;
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}
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static int nvadsp_runtime_idle(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct nvadsp_drv_data *drv_data = platform_get_drvdata(pdev);
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int ret = 0;
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if (drv_data->runtime_idle)
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ret = drv_data->runtime_idle(dev);
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return ret;
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}
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#endif /* CONFIG_PM */
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#ifdef CONFIG_PM_SLEEP
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static int nvadsp_suspend(struct device *dev)
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{
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if (pm_runtime_status_suspended(dev))
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return 0;
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return nvadsp_runtime_suspend(dev);
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}
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static int nvadsp_resume(struct device *dev)
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{
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if (pm_runtime_status_suspended(dev))
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return 0;
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return nvadsp_runtime_resume(dev);
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}
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#endif /* CONFIG_PM_SLEEP */
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static const struct dev_pm_ops nvadsp_pm_ops = {
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SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(nvadsp_suspend, nvadsp_resume)
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SET_RUNTIME_PM_OPS(nvadsp_runtime_suspend, nvadsp_runtime_resume,
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nvadsp_runtime_idle)
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};
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uint64_t nvadsp_get_timestamp_counter(void)
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{
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return arch_counter_get_cntvct();
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}
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EXPORT_SYMBOL(nvadsp_get_timestamp_counter);
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static void __init nvadsp_parse_clk_entries(struct platform_device *pdev)
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{
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struct nvadsp_drv_data *drv_data = platform_get_drvdata(pdev);
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struct device *dev = &pdev->dev;
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u32 val32 = 0;
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/* Optional properties, should come from platform dt files */
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if (of_property_read_u32(dev->of_node, "nvidia,adsp_freq", &val32))
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dev_dbg(dev, "adsp_freq dt not found\n");
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else {
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drv_data->adsp_freq = val32;
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drv_data->adsp_freq_hz = val32 * 1000;
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}
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if (of_property_read_u32(dev->of_node, "nvidia,ape_freq", &val32))
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dev_dbg(dev, "ape_freq dt not found\n");
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else
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drv_data->ape_freq = val32;
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if (of_property_read_u32(dev->of_node, "nvidia,ape_emc_freq", &val32))
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dev_dbg(dev, "ape_emc_freq dt not found\n");
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else
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drv_data->ape_emc_freq = val32;
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}
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static int __init nvadsp_parse_dt(struct platform_device *pdev)
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{
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struct nvadsp_drv_data *drv_data = platform_get_drvdata(pdev);
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struct device *dev = &pdev->dev;
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u32 *adsp_reset;
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u32 *adsp_mem;
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int iter;
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adsp_reset = drv_data->unit_fpga_reset;
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adsp_mem = drv_data->adsp_mem;
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for (iter = 0; iter < ADSP_MEM_END; iter++) {
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if (of_property_read_u32_index(dev->of_node, "nvidia,adsp_mem",
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iter, &adsp_mem[iter])) {
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dev_err(dev, "adsp memory dt %d not found\n", iter);
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return -EINVAL;
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}
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}
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for (iter = 0; iter < ADSP_EVP_END; iter++) {
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if (of_property_read_u32_index(dev->of_node,
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"nvidia,adsp-evp-base",
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iter, &drv_data->evp_base[iter])) {
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dev_err(dev, "adsp memory dt %d not found\n", iter);
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return -EINVAL;
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}
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}
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drv_data->adsp_unit_fpga = of_property_read_bool(dev->of_node,
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"nvidia,adsp_unit_fpga");
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drv_data->adsp_os_secload = of_property_read_bool(dev->of_node,
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"nvidia,adsp_os_secload");
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if (drv_data->adsp_unit_fpga) {
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for (iter = 0; iter < ADSP_UNIT_FPGA_RESET_END; iter++) {
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if (of_property_read_u32_index(dev->of_node,
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"nvidia,adsp_unit_fpga_reset", iter,
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&adsp_reset[iter])) {
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dev_err(dev, "adsp reset dt %d not found\n",
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iter);
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return -EINVAL;
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}
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}
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}
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nvadsp_parse_clk_entries(pdev);
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drv_data->state.evp = devm_kzalloc(dev,
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drv_data->evp_base[ADSP_EVP_SIZE], GFP_KERNEL);
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if (!drv_data->state.evp)
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return -ENOMEM;
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return 0;
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}
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static int __init nvadsp_probe(struct platform_device *pdev)
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{
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struct nvadsp_drv_data *drv_data;
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struct device *dev = &pdev->dev;
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struct resource *res = NULL;
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void __iomem *base = NULL;
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uint32_t aram_addr;
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uint32_t aram_size;
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int dram_iter;
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int irq_iter;
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int ret = 0;
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int iter;
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dev_info(dev, "in probe()...\n");
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drv_data = devm_kzalloc(dev, sizeof(*drv_data),
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GFP_KERNEL);
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if (!drv_data) {
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dev_err(&pdev->dev, "Failed to allocate driver data");
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ret = -ENOMEM;
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goto out;
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}
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platform_set_drvdata(pdev, drv_data);
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drv_data->pdev = pdev;
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drv_data->chip_data = of_device_get_match_data(dev);
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ret = nvadsp_parse_dt(pdev);
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if (ret)
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goto out;
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#ifdef CONFIG_PM
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ret = nvadsp_pm_init(pdev);
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if (ret) {
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dev_err(dev, "Failed in pm init");
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goto out;
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}
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#endif
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#ifdef CONFIG_DEBUG_FS
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if (adsp_debug_init(drv_data))
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dev_err(dev,
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"unable to create tegra_ape debug fs directory\n");
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#endif
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drv_data->base_regs =
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devm_kzalloc(dev, sizeof(void *) * APE_MAX_REG,
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GFP_KERNEL);
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if (!drv_data->base_regs) {
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dev_err(dev, "Failed to allocate regs");
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ret = -ENOMEM;
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goto out;
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}
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for (iter = 0; iter < APE_MAX_REG; iter++) {
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res = platform_get_resource(pdev, IORESOURCE_MEM, iter);
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if (!res) {
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dev_err(dev,
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"Failed to get resource with ID %d\n",
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iter);
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ret = -EINVAL;
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goto out;
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}
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if (!drv_data->adsp_unit_fpga && iter == UNIT_FPGA_RST)
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continue;
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/*
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* skip if the particular module is not present in a
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* generation, for which the register start address
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* is made 0 from dt.
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*/
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if (res->start == 0)
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continue;
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base = devm_ioremap_resource(dev, res);
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if (IS_ERR(base)) {
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dev_err(dev, "Failed to iomap resource reg[%d]\n",
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iter);
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ret = PTR_ERR(base);
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goto out;
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}
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drv_data->base_regs[iter] = base;
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nvadsp_add_load_mappings(res->start, base,
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resource_size(res));
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}
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drv_data->base_regs_saved = drv_data->base_regs;
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for (dram_iter = 0; dram_iter < ADSP_MAX_DRAM_MAP; dram_iter++) {
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res = platform_get_resource(pdev, IORESOURCE_MEM, iter++);
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if (!res) {
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dev_err(dev,
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"Failed to get DRAM map with ID %d\n", iter);
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ret = -EINVAL;
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goto out;
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}
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drv_data->dram_region[dram_iter] = res;
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}
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for (irq_iter = 0; irq_iter < NVADSP_VIRQ_MAX; irq_iter++) {
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res = platform_get_resource(pdev, IORESOURCE_IRQ, irq_iter);
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if (!res) {
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dev_err(dev, "Failed to get irq number for index %d\n",
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irq_iter);
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ret = -EINVAL;
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goto out;
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}
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drv_data->agic_irqs[irq_iter] = res->start;
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}
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nvadsp_drv_data = drv_data;
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#ifdef CONFIG_PM
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tegra_pd_add_device(dev);
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pm_runtime_enable(dev);
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ret = pm_runtime_get_sync(dev);
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if (ret < 0)
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goto out;
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#endif
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ret = nvadsp_hwmbox_init(pdev);
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if (ret)
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goto err;
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ret = nvadsp_mbox_init(pdev);
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if (ret)
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goto err;
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#ifdef CONFIG_TEGRA_ADSP_ACTMON
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ret = ape_actmon_probe(pdev);
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if (ret)
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goto err;
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#endif
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ret = nvadsp_os_probe(pdev);
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if (ret)
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goto err;
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ret = nvadsp_reset_init(pdev);
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if (ret) {
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dev_err(dev, "Failed initialize resets\n");
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goto err;
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}
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ret = nvadsp_app_module_probe(pdev);
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if (ret)
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goto err;
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aram_addr = drv_data->adsp_mem[ARAM_ALIAS_0_ADDR];
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aram_size = drv_data->adsp_mem[ARAM_ALIAS_0_SIZE];
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ret = nvadsp_aram_init(aram_addr, aram_size);
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if (ret)
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dev_err(dev, "Failed to init aram\n");
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drv_data->bwmgr = tegra_bwmgr_register(TEGRA_BWMGR_CLIENT_APE_ADSP);
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ret = IS_ERR_OR_NULL(drv_data->bwmgr);
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if (ret)
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dev_err(&pdev->dev, "unable to register bwmgr\n");
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err:
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#ifdef CONFIG_PM
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ret = pm_runtime_put_sync(dev);
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if (ret < 0)
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dev_err(dev, "pm_runtime_put_sync failed\n");
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#endif
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out:
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return ret;
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}
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static int nvadsp_remove(struct platform_device *pdev)
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{
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struct nvadsp_drv_data *drv_data = platform_get_drvdata(pdev);
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int err;
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if (drv_data->bwmgr) {
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err = tegra_bwmgr_set_emc(drv_data->bwmgr, 0,
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TEGRA_BWMGR_SET_EMC_FLOOR);
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if (err) {
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dev_err(&pdev->dev, "failed to set emc freq rate:%d\n",
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err);
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}
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tegra_bwmgr_unregister(drv_data->bwmgr);
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}
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nvadsp_aram_exit();
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pm_runtime_disable(&pdev->dev);
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#ifdef CONFIG_PM
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if (!pm_runtime_status_suspended(&pdev->dev))
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nvadsp_runtime_suspend(&pdev->dev);
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#endif
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tegra_pd_remove_device(&pdev->dev);
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return 0;
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}
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#ifdef CONFIG_OF
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static struct nvadsp_chipdata tegra210_adsp_chipdata = {
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.hwmb = {
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.reg_idx = AMISC,
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.hwmbox0_reg = 0x58,
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.hwmbox1_reg = 0X5C,
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.hwmbox2_reg = 0x60,
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.hwmbox3_reg = 0x64,
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},
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.adsp_state_hwmbox = -1,
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.adsp_thread_hwmbox = -1,
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.adsp_irq_hwmbox = -1,
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.reset_init = nvadsp_reset_t21x_init,
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.os_init = nvadsp_os_t21x_init,
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#ifdef CONFIG_PM
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.pm_init = nvadsp_pm_t21x_init,
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#endif
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.wdt_irq = INT_T210_ADSP_WDT,
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.start_irq = INT_T210_AGIC_START,
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.end_irq = INT_T210_AGIC_END,
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};
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static struct nvadsp_chipdata tegrat18x_adsp_chipdata = {
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.hwmb = {
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.reg_idx = AHSP,
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.hwmbox0_reg = 0x00000,
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.hwmbox1_reg = 0X08000,
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.hwmbox2_reg = 0X10000,
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.hwmbox3_reg = 0X18000,
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.hwmbox4_reg = 0X20000,
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.hwmbox5_reg = 0X28000,
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.hwmbox6_reg = 0X30000,
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.hwmbox7_reg = 0X38000,
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},
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.adsp_state_hwmbox = 0x30000,
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.adsp_thread_hwmbox = 0x20000,
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.adsp_irq_hwmbox = 0x38000,
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.reset_init = nvadsp_reset_t18x_init,
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.os_init = nvadsp_os_t18x_init,
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#ifdef CONFIG_PM
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.pm_init = nvadsp_pm_t18x_init,
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#endif
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.wdt_irq = INT_T18x_ATKE_WDT_IRQ,
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.start_irq = INT_T18x_AGIC_START,
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.end_irq = INT_T18x_AGIC_END,
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};
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static const struct of_device_id nvadsp_of_match[] = {
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{
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.compatible = "nvidia,tegra210-adsp",
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.data = &tegra210_adsp_chipdata,
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}, {
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.compatible = "nvidia,tegra18x-adsp",
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.data = &tegrat18x_adsp_chipdata,
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}, {
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.compatible = "nvidia,tegra18x-adsp-hv",
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.data = &tegrat18x_adsp_chipdata,
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}, {
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},
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};
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#endif
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static struct platform_driver nvadsp_driver __refdata = {
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.driver = {
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.name = "nvadsp",
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.owner = THIS_MODULE,
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.pm = &nvadsp_pm_ops,
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.of_match_table = of_match_ptr(nvadsp_of_match),
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},
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.probe = nvadsp_probe,
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.remove = nvadsp_remove,
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};
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static int __init nvadsp_init(void)
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{
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return platform_driver_register(&nvadsp_driver);
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}
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static void __exit nvadsp_exit(void)
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{
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platform_driver_unregister(&nvadsp_driver);
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}
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module_init(nvadsp_init);
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module_exit(nvadsp_exit);
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MODULE_AUTHOR("NVIDIA");
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MODULE_DESCRIPTION("Tegra Host ADSP Driver");
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MODULE_VERSION("1.0");
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MODULE_LICENSE("Dual BSD/GPL");
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