176 lines
5.2 KiB
C
176 lines
5.2 KiB
C
/*
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* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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*
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* NVIDIA CORPORATION and its licensors retain all intellectual property
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* and proprietary rights in and to this software, related documentation
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* and any modifications thereto. Any use, reproduction, disclosure or
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* distribution of this software and related documentation without an express
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* license agreement from NVIDIA CORPORATION is strictly prohibited.
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*/
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#ifndef _AON_SPI_MESSAGES_H_
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#define _AON_SPI_MESSAGES_H_
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#include <linux/types.h>
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#define TEGRA_IVC_ALIGN 64
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/* 24640 is emperically derived by observing the max len transactions
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* touch.
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*/
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#define AON_SPI_MAX_DATA_SIZE 24640
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/* All the enums and the fields inside the structs described in this header
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* file supports only uX type, where X can be 8,16,32. For inter CPU commun-
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* ication, it is more stable to use this type.
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*/
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/* This enum represents the types of spi requests assocaited
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* with AON.
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*/
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enum aon_spi_request_type {
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AON_SPI_REQUEST_TYPE_INIT = 1,
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AON_SPI_REQUEST_TYPE_SETUP = 2,
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AON_SPI_REQUEST_TYPE_XFER = 3,
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AON_SPI_REQUEST_TYPE_SUSPEND = 4,
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AON_SPI_REQUEST_TYPE_RESUME = 5,
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};
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/*
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* This enum indicates the status of the request from CCPLEX.
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*/
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enum aon_spi_status {
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AON_SPI_STATUS_OK = 0,
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AON_SPI_STATUS_ERROR = 1,
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};
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/* This enum represents whether the current SPI transaction
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* is a read or write. Also indicates whether the current
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* message is the first or last in the context of a big xfer
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* split into multiple xfers.
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*/
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enum aon_spi_xfer_flag {
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AON_SPI_XFER_FLAG_WRITE = BIT(1),
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AON_SPI_XFER_FLAG_READ = BIT(2),
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AON_SPI_XFER_FIRST_MSG = BIT(3),
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AON_SPI_XFER_LAST_MSG = BIT(4),
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AON_SPI_XFER_HANDLE_CACHE = BIT(5),
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};
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/* This struct is used to setup the SPI client setup for AON
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* SPI controller.
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* Fields:
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* cs_setup_clk_count: CS pin setup clock count
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* cs_hold_clk_count: CS pin hold clock count
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* cs_inactive_cycles: CS pin inactive clock count
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* set_rx_tap_delay: Specify if the SPI device need to set
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RX tap delay
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* spi_max_clk_rate: Specify the default clock rate of SPI client
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* spi_no_dma: Flag to indicate pio or dma mode
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*/
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struct aon_spi_setup_request {
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u32 cs_setup_clk_count;
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u32 cs_hold_clk_count;
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u32 cs_inactive_cycles;
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u32 spi_max_clk_rate;
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u8 chip_select;
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u8 set_rx_tap_delay;
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bool spi_no_dma;
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};
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/* This struct indicates the parameters for SPI xfer from CCPLEX to SPE.
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* Fields:
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* spi_clk_rate: Specify clock rate for current transfer
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* flags: Indicate first/last message
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* length: Current transfer length
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* tx_buf_offset: Offset in the data field of the aon_spi_xfer_request
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* struct for tx_buf contents. The buffer memory need to
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* be aligned for DMA transfer
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* rx_buf_offset: Offset in the data field of the aon_spi_xfer_request
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* struct for rx_buf. The buffer memory need to be
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* aligned for DMA transfer
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* chip_select: Chip select of the slave device
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* bits_per_word: Select bits_per_word
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* tx_nbits: Number of bits used for writing
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* rx_nbits: Number of bits used for reading
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*
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* When SPI can transfer in 1x,2x or 4x. It can get this tranfer information
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* from device through tx_nbits and rx_nbits. In Bi-direction, these
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* two should both be set. User can set transfer mode with SPI_NBITS_SINGLE(1x)
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* SPI_NBITS_DUAL(2x) and SPI_NBITS_QUAD(4x) to support these three transfer.
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*/
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struct aon_spi_xfer_params {
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u32 spi_clk_rate;
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/* enum aon_spi_xfer_flag */
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u16 flags;
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u16 length;
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u16 tx_buf_offset;
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u16 rx_buf_offset;
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u16 mode;
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u8 chip_select;
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u8 bits_per_word;
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u8 tx_nbits;
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u8 rx_nbits;
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};
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/* This struct indicates the contents of the xfer request from CCPLEX to SPE
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* for the AON SPI controller.
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*
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* Fields:
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* xfers; Paramters for the current transfers.
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* data: Buffer that holds the data for the current SPI ransaction.
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* The size is aligned to the size of the cache line.
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*/
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struct aon_spi_xfer_request {
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union {
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struct aon_spi_xfer_params xfers;
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u8 align_t[TEGRA_IVC_ALIGN - sizeof(u32)];
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};
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u8 data[AON_SPI_MAX_DATA_SIZE];
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};
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/* This structure indicates the contents of the response from the remote CPU
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* i.e SPE for the previously requested transaction via CCPLEX proxy driver.
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*
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* Fields:
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* data: This just matches the data field in the xfer request struct.
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* All the response is stored in this buf and can be accessed by
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* the offset fields known in the xfer params.
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*/
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struct aon_spi_xfer_response {
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union {
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u8 align_t[TEGRA_IVC_ALIGN - sizeof(u32)];
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};
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u8 data[AON_SPI_MAX_DATA_SIZE];
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};
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/* This structure indicates the current SPI request from CCPLEX to SPE for the
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* AON SPI controller.
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*
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* Fields:
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* req_type: Indicates the type of request. Supports init, setup and xfer.
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* data: Union of structs of all the request types.
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*/
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struct aon_spi_request {
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/* enum aon_spi_request_type */
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u32 req_type;
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union {
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struct aon_spi_setup_request setup;
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struct aon_spi_xfer_request xfer;
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} data;
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};
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/* This structure indicates the response for the SPI request from SPE to CCPLEX
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* for the AON SPI controller.
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*
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* Fields:
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* status: Response in regard to the request i.e success/failure.
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* data: Union of structs of all the response types.
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*/
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struct aon_spi_response {
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u32 status;
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union {
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struct aon_spi_xfer_response xfer;
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} data;
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};
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#endif
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