141 lines
3.3 KiB
C
141 lines
3.3 KiB
C
/*
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* Copyright (C) 2015 Google, Inc.
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* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/types.h>
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#include <linux/printk.h>
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#include <linux/trusty/trusty.h>
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#include <linux/trusty/smcall.h>
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static int get_mem_attr(struct page *page, pgprot_t pgprot)
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{
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#if defined(CONFIG_ARM64)
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uint64_t mair;
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uint attr_index = (pgprot_val(pgprot) & PTE_ATTRINDX_MASK) >> 2;
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asm ("mrs %0, mair_el1\n" : "=&r" (mair));
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return (mair >> (attr_index * 8)) & 0xff;
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#elif defined(CONFIG_ARM_LPAE)
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uint32_t mair;
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uint attr_index = ((pgprot_val(pgprot) & L_PTE_MT_MASK) >> 2);
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if (attr_index >= 4) {
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attr_index -= 4;
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asm volatile("mrc p15, 0, %0, c10, c2, 1\n" : "=&r" (mair));
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} else {
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asm volatile("mrc p15, 0, %0, c10, c2, 0\n" : "=&r" (mair));
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}
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return (mair >> (attr_index * 8)) & 0xff;
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#elif defined(CONFIG_ARM)
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/* check memory type */
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switch (pgprot_val(pgprot) & L_PTE_MT_MASK) {
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case L_PTE_MT_WRITEALLOC:
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/* Normal: write back write allocate */
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return 0xFF;
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case L_PTE_MT_BUFFERABLE:
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/* Normal: non-cacheble */
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return 0x44;
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case L_PTE_MT_WRITEBACK:
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/* Normal: writeback, read allocate */
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return 0xEE;
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case L_PTE_MT_WRITETHROUGH:
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/* Normal: write through */
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return 0xAA;
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case L_PTE_MT_UNCACHED:
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/* strongly ordered */
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return 0x00;
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case L_PTE_MT_DEV_SHARED:
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case L_PTE_MT_DEV_NONSHARED:
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/* device */
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return 0x04;
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default:
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return -EINVAL;
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}
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#else
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return 0;
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#endif
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}
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int trusty_encode_page_info(struct ns_mem_page_info *inf,
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struct page *page, pgprot_t pgprot)
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{
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int mem_attr;
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uint64_t pte;
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int ret = 0;
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if (!inf || !page)
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return -EINVAL;
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/* get physical address */
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pte = (uint64_t) page_to_phys(page);
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ret = hyp_ipa_translate(&pte);
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if (ret)
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return ret;
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/* get memory attributes */
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mem_attr = get_mem_attr(page, pgprot);
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if (mem_attr < 0)
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return mem_attr;
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/* add other attributes */
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#if defined(CONFIG_ARM64) || defined(CONFIG_ARM_LPAE)
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pte |= pgprot_val(pgprot);
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#elif defined(CONFIG_ARM)
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if (pgprot_val(pgprot) & L_PTE_USER)
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pte |= (1 << 6);
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if (pgprot_val(pgprot) & L_PTE_RDONLY)
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pte |= (1 << 7);
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if (pgprot_val(pgprot) & L_PTE_SHARED)
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pte |= (3 << 8); /* inner sharable */
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#endif
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inf->attr = (pte & 0x0000FFFFFFFFFFFFull) | ((uint64_t)mem_attr << 48);
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return 0;
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}
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int trusty_call32_mem_buf(struct device *dev, u32 smcnr,
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struct page *page, u32 size,
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pgprot_t pgprot)
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{
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int ret = 0;
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struct ns_mem_page_info pg_inf;
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if (!dev || !page)
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return -EINVAL;
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ret = trusty_encode_page_info(&pg_inf, page, pgprot);
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if (ret)
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return ret;
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if (SMC_IS_FASTCALL(smcnr)) {
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return trusty_fast_call32(dev, smcnr,
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(u32)pg_inf.attr,
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(u32)(pg_inf.attr >> 32), size);
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} else {
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return trusty_std_call32(dev, smcnr,
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(u32)pg_inf.attr,
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(u32)(pg_inf.attr >> 32), size);
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}
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}
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EXPORT_SYMBOL(trusty_call32_mem_buf);
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