97 lines
2.6 KiB
C
97 lines
2.6 KiB
C
/*
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* max929x_hdmi2gmsl.h: hdmi max929x controller interface.
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*
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* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Author:
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* Tow Wang <toww@nvidia.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __DRIVERS_VIDEO_TEGRA_DC_MAX929x_HDMI2GMSL_H
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#define __DRIVERS_VIDEO_TEGRA_DC_MAX929x_HDMI2GMSL_H
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struct tegra_dc_hdmi2gmsl_data {
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struct tegra_hdmi *hdmi;
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struct i2c_client *client_i2c;
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struct regmap *regmap;
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struct tegra_dc_mode *mode;
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bool hdmi2gmsl_enabled;
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struct mutex lock;
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int en_gpio; /* GPIO */
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int en_gpio_flags;
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};
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/*
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* The data sheet does not give names to the registers.
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* These are just visual cues to avoid mismatched I2C addresses and registers.
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*/
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enum MAX929x_GMSLRegister_e {
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MAX929x_GMSL_REG_00 = 0x00,
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MAX929x_GMSL_REG_01 = 0x01,
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MAX929x_GMSL_REG_02 = 0x02,
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MAX929x_GMSL_REG_03 = 0x03,
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MAX929x_GMSL_REG_04 = 0x04,
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MAX929x_GMSL_REG_05 = 0x05,
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MAX929x_GMSL_REG_06 = 0x06,
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MAX929x_GMSL_REG_07 = 0x07,
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MAX929x_GMSL_REG_08 = 0x08,
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MAX929x_GMSL_REG_09 = 0x09,
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MAX929x_GMSL_REG_0A = 0x0A,
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MAX929x_GMSL_REG_0B = 0x0B,
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MAX929x_GMSL_REG_0C = 0x0C,
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MAX929x_GMSL_REG_0D = 0x0D,
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MAX929x_GMSL_REG_0E = 0x0E,
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MAX929x_GMSL_REG_0F = 0x0F,
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MAX929x_GMSL_REG_10 = 0x10,
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MAX929x_GMSL_REG_11 = 0x11,
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MAX929x_GMSL_REG_12 = 0x12,
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MAX929x_GMSL_REG_13 = 0x13,
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MAX929x_GMSL_REG_14 = 0x14,
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MAX929x_GMSL_REG_15 = 0x15,
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MAX929x_GMSL_REG_16 = 0x16,
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MAX929x_GMSL_REG_17 = 0x17,
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MAX929x_GMSL_REG_18 = 0x18,
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MAX929x_GMSL_REG_19 = 0x19,
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MAX929x_GMSL_REG_1A = 0x1A,
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MAX929x_GMSL_REG_1B = 0x1B,
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MAX929x_GMSL_REG_1C = 0x1C,
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MAX929x_GMSL_REG_1D = 0x1D,
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MAX929x_GMSL_REG_1E = 0x1E,
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MAX929x_GMSL_REG_1F = 0x1F
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};
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/* MAX929x_GMSL_REG_04 */
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#define MAX929x_GMSL_REG_04_MASK_SEREN 0x80
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#define MAX929x_GMSL_REG_04_MASK_CLINKEN 0x40
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#define MAX929x_GMSL_REG_04_MASK_PRBSEN 0x20
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#define MAX929x_GMSL_REG_04_MASK_SLEEP 0x10
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#define MAX929x_GMSL_REG_04_MASK_INTTYPE 0x0C
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#define MAX929x_GMSL_REG_04_MASK_REVCCEN 0x02
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#define MAX929x_GMSL_REG_04_MASK_FWDCCEN 0x01
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/*
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enum MAX9293_HDCPRegister_e {
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MAX9293_HDCP_REG_
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};
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enum MAX929x_HDMIAudioRegister_e {
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MAX929x_HDMI_AUDIO_REG_
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};
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*/
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/* Global variables */
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extern struct tegra_hdmi_out_ops tegra_hdmi2gmsl_ops;
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#endif /* __DRIVERS_VIDEO_TEGRA_DC_MAX929x_HDMI2GMSL_H */
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