125 lines
3.6 KiB
C
125 lines
3.6 KiB
C
/*
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* drivers/video/tegra/host/host1x/host1x_syncpt.c
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*
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* Tegra Graphics Host Syncpoints for HOST1X
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*
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* Copyright (c) 2010-2019, NVIDIA Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <uapi/linux/nvhost_ioctl.h>
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#include <linux/io.h>
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#include <trace/events/nvhost.h>
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#include "nvhost_syncpt.h"
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#include "nvhost_acm.h"
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#include "host1x.h"
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#include "chip_support.h"
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/**
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* Write the current syncpoint value back to hw.
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*/
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static void t20_syncpt_reset(struct nvhost_syncpt *sp, u32 id)
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{
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struct nvhost_master *dev = syncpt_to_dev(sp);
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int min = nvhost_syncpt_read_min(sp, id);
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host1x_sync_writel(dev, (host1x_sync_syncpt_0_r() + id * 4), min);
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}
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/**
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* Updates the last value read from hardware.
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* (was nvhost_syncpt_update_min)
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*/
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static u32 t20_syncpt_update_min(struct nvhost_syncpt *sp, u32 id)
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{
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struct nvhost_master *dev = syncpt_to_dev(sp);
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u32 old, live;
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do {
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old = nvhost_syncpt_read_min(sp, id);
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live = host1x_sync_readl(dev,
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(host1x_sync_syncpt_0_r() + id * 4));
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} while ((u32)atomic_cmpxchg(&sp->min_val[id], old, live) != old);
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return live;
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}
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/**
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* Write a cpu syncpoint increment to the hardware, without touching
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* the cache. Caller is responsible for host being powered.
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*/
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static void t20_syncpt_cpu_incr(struct nvhost_syncpt *sp, u32 id)
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{
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struct nvhost_master *dev = syncpt_to_dev(sp);
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u32 reg_offset = id / 32;
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if (!nvhost_syncpt_client_managed(sp, id)
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&& nvhost_syncpt_min_eq_max(sp, id)) {
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dev_err(&syncpt_to_dev(sp)->dev->dev,
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"Trying to increment syncpoint id %d beyond max\n",
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id);
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nvhost_debug_dump(syncpt_to_dev(sp));
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return;
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}
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host1x_sync_writel(dev,
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host1x_sync_syncpt_cpu_incr_r() + reg_offset * 4, bit_mask(id));
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}
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static const char *t20_syncpt_name(struct nvhost_syncpt *sp, u32 id)
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{
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const char *name = sp->syncpt_names[id];
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return name ? name : "";
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}
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static int syncpt_mutex_try_lock(struct nvhost_syncpt *sp,
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unsigned int idx)
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{
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struct nvhost_master *dev = syncpt_to_dev(sp);
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/* mlock registers returns 0 when the lock is aquired.
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* writing 0 clears the lock. */
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return !!host1x_sync_readl(dev,
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(host1x_sync_mlock_0_r() + idx * 4));
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}
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static void syncpt_mutex_unlock(struct nvhost_syncpt *sp,
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unsigned int idx)
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{
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struct nvhost_master *dev = syncpt_to_dev(sp);
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host1x_sync_writel(dev, (host1x_sync_mlock_0_r() + idx * 4), 0);
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}
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static void syncpt_mutex_owner(struct nvhost_syncpt *sp,
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unsigned int idx,
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bool *cpu, bool *ch,
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unsigned int *chid)
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{
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struct nvhost_master *dev = syncpt_to_dev(sp);
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u32 owner = host1x_sync_readl(dev,
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host1x_sync_mlock_owner_0_r() + idx * 4);
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*chid = host1x_sync_mlock_owner_0_mlock_owner_chid_0_v(owner);
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*cpu = host1x_sync_mlock_owner_0_mlock_cpu_owns_0_v(owner);
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*ch = host1x_sync_mlock_owner_0_mlock_ch_owns_0_v(owner);
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}
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static const struct nvhost_syncpt_ops host1x_syncpt_ops = {
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.reset = t20_syncpt_reset,
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.update_min = t20_syncpt_update_min,
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.cpu_incr = t20_syncpt_cpu_incr,
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.name = t20_syncpt_name,
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.mutex_try_lock = syncpt_mutex_try_lock,
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.mutex_unlock_nvh = syncpt_mutex_unlock,
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.mutex_owner = syncpt_mutex_owner,
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};
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