432 lines
12 KiB
C
432 lines
12 KiB
C
/*
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* drivers/video/tegra/host/nvdla/nvdla.h
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*
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* Tegra Graphics Host NVDLA
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*
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* Copyright (c) 2016-2019 NVIDIA Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __NVHOST_NVDLA_H__
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#define __NVHOST_NVDLA_H__
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#include <linux/completion.h>
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#include <linux/mutex.h>
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#include <uapi/linux/nvdev_fence.h>
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#include <uapi/linux/nvhost_nvdla_ioctl.h>
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#include "nvdla_buffer.h"
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#include "dla_os_interface.h"
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#include "dla_t19x_fw_version.h"
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/*
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* macro to encode firmware version
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*/
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#define FIRMWARE_ENCODE_VERSION(chip) \
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(((FIRMWARE_##chip##_VERSION_MAJOR & 0xffU) << 16) | \
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((FIRMWARE_##chip##_VERSION_MINOR & 0xffU) << 8) | \
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((FIRMWARE_##chip##_VERSION_SUBMINOR & 0xffU)))
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#define ALIGNED_DMA(x) ((x >> 8) & 0xffffffff)
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/*
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* Max grid size
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*/
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#define MAX_GRID_SIZE SZ_256
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/**
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* DLA MCIF (Matrix Convolution Image Filter) outstanding AXI transactions
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* count register offset
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*/
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#define NVDLA_MCIF_CFG_OUTSTANDING_CNT_0_OFFSET 0x00005014 /* RW-4R */
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/**
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* Method ID and Method data THI registers
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*/
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#define NV_DLA_THI_METHOD_ID 0x00000040 /* RW-4R */
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#define NV_DLA_THI_METHOD_DATA 0x00000044 /* RW-4R */
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#define NV_DLA_OS_VERSION 0x00001080 /* RW-4R */
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#define MAX_NUM_ACTION_LIST 1
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/**
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* Maximum number of queue's per engine
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*/
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#define MAX_NVDLA_QUEUE_COUNT 16
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/**
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* Maximum number of tasks per queue
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*/
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#define MAX_NVDLA_TASK_COUNT 32
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/**
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* Maximum number of buffers per pin request
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*/
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#define MAX_NVDLA_PIN_BUFFERS 32
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/**
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* Maximum number of buffers per task
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*/
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#define MAX_NUM_NVDLA_BUFFERS_PER_TASK 6144
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/**
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* Trace Buffer Size
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*/
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#define TRACE_BUFFER_SIZE SZ_1M
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/**
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* Maximum buffer size for debug dump
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*/
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#define DEBUG_BUFFER_SIZE SZ_256
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/**
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* Firmware GCOV Buffer Size
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*/
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#define GCOV_BUFFER_SIZE SZ_64K
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/*
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* CMD submission timeout in msec
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*/
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#define CMD_TIMEOUT_MSEC (1000)
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/**
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* Max number of fences supported
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*/
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#define MAX_NUM_NVDLA_PREFENCES 32
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#define MAX_NUM_NVDLA_POSTFENCES 32
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#define MAX_NUM_NVDLA_EMU_PREFENCES 16
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#define MAX_NUM_NVDLA_EMU_POSTFENCES 16
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#define MAX_NUM_NVDLA_IN_TASK_STATUS MAX_NUM_NVDLA_PREFENCES
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#define MAX_NUM_NVDLA_OUT_TASK_STATUS MAX_NUM_NVDLA_POSTFENCES
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#define MAX_NUM_NVDLA_OUT_TIMESTAMP 32
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#define NUM_PROFILING_POSTACTION 1
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#define MAX_COMMANDS_PER_DEVICE 1
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/*
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* keep max cmd size multiple of 256 bytes.
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*/
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#define MAX_CMD_SIZE SZ_256
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#define NVDLA_CMD_OFFSET(index) (MAX_CMD_SIZE * index)
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/*
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* Tegra/DLA Hardware version specific Quirks
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*/
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#define NVDLA_QUIRK_T194_A01_WAR BIT(0)
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/**
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* data structure to keep command memory
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*
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* @pa IOVA pointing to cmd memory with offset
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* @va VA of cmd memory
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* @index index pointing command in pool
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*
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*/
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struct nvdla_cmd_mem_info {
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dma_addr_t pa;
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void *va;
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int index;
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};
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/**
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* data structure to keep command memory pool
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*
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* @pa IOVA pointing to cmd memory
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* @va VA of cmd memory
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* @lock mutex lock
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* @alloc_table memory usage bitmap table
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*/
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struct nvdla_cmd_mem {
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dma_addr_t pa;
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void *va;
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struct mutex lock;
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unsigned long alloc_table;
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};
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/**
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* data structure to keep command data
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*
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* @method_id method id with command and other info
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* @method_data method data for command
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* @wait If set to true then wait for command completion
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*/
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struct nvdla_cmd_data {
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uint32_t method_id;
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uint32_t method_data;
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bool wait;
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};
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enum nvdla_submit_mode {
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NVDLA_SUBMIT_MODE_MMIO = 0,
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NVDLA_SUBMIT_MODE_CHANNEL = 1
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};
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/**
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* data structure to keep per DLA engine device data
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*
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* @pdev pointer to platform device
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* @pool pointer to queue table
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* @dbg_mask debug mask for print level
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* @en_trace flag to enable kernel tracing
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* @submit_mode flag to enable task submit mode, default is
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* NVDLA_SUBMIT_MODE_MMIO
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* @fw_version saves current firmware version
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* @cmd_mem structure to hold command memory pool
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* @trace_enable to enable/disable the DLA firmware trace
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* @events_mask mask to set/reset the different DLA firmware trace event
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* @is_gos_enabled flag to check if GoS enabled
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* @debug_dump_pa physical address of print buffer
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* @debug_dump_va virtual address of print buffer
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* @trace_dump_pa physical address of trace buffer
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* @trace_dump_va virtual address of trace buffer
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* @en_fw_gcov flag to enable firmware gcov
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* @gcov_dump_pa physical address of fw gcov buffer
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* @gcov_dump_va virtual address of fw gcovbuffer
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* @quirks Tegra/DLA Hardware version specific settings
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*/
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struct nvdla_device {
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struct platform_device *pdev;
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struct nvdla_queue_pool *pool;
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struct completion cmd_completion;
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struct mutex cmd_lock;
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int cmd_status;
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int waiting;
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u32 dbg_mask;
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u32 en_trace;
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u32 submit_mode;
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u32 fw_version;
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struct nvdla_cmd_mem cmd_mem;
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u32 trace_enable;
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u32 events_mask;
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bool is_gos_enabled;
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bool is_gos_fetched;
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dma_addr_t debug_dump_pa;
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u32 *debug_dump_va;
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dma_addr_t trace_dump_pa;
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u32 *trace_dump_va;
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u32 en_fw_gcov;
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dma_addr_t gcov_dump_pa;
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u32 *gcov_dump_va;
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u32 quirks;
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struct work_struct reset_work;
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};
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/**
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* struct nvdla_emu_task: structure for emulator task info
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*
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* @queue Queue in which task submitted
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* @sp pointer to syncpt
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* @prefences pointer to pre fences
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* @postfences pointer to post fences
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* @num_prefences Number of prefences in task
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* @num_postfences Number of postfences in task
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* @fence Fence tracking for current task
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* @fence_counter Counter used to track fence value
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*
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*/
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struct nvdla_emu_task {
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struct nvdla_queue *queue;
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struct nvhost_syncpt *sp;
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struct nvdev_fence prefences[MAX_NUM_NVDLA_EMU_PREFENCES];
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struct nvdev_fence postfences[MAX_NUM_NVDLA_EMU_POSTFENCES];
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u32 num_prefences;
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u32 num_postfences;
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u32 fence;
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u32 fence_counter;
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};
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/**
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* struct nvdla_task: structure for task info
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*
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* @queue Queue in which task submitted
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* @buffers nvhost buffers for priv/task
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* @sp pointer to syncpt
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* @prefences pointer to prefences
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* @postfences pointer to post fences
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* @fence fence tracking for current task
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* @ref Reference count for task
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* @list List entry
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* @task_desc DLA task desc VA
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* @task_desc_pa DLA task desc PA
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* @buf_size Total size of task dma alloc
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* @timeout max timeout to wait for task completion
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* @op_handle pointer to handle list of operation descriptor
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*
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*/
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struct nvdla_task {
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struct nvdla_queue *queue;
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struct nvdla_buffers *buffers;
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struct nvhost_syncpt *sp;
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struct nvdev_fence prefences[MAX_NUM_NVDLA_PREFENCES];
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struct nvdev_fence postfences[MAX_NUM_NVDLA_POSTFENCES];
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struct nvdla_status_notify in_task_status[MAX_NUM_NVDLA_IN_TASK_STATUS];
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struct nvdla_status_notify sof_task_status[MAX_NUM_NVDLA_OUT_TASK_STATUS];
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struct nvdla_status_notify eof_task_status[MAX_NUM_NVDLA_OUT_TASK_STATUS];
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struct nvdla_mem_handle sof_timestamps[MAX_NUM_NVDLA_OUT_TIMESTAMP];
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struct nvdla_mem_handle eof_timestamps[MAX_NUM_NVDLA_OUT_TIMESTAMP];
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struct nvdla_mem_handle memory_handles[NVDLA_MAX_BUFFERS_PER_TASK];
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u8 num_prefences;
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u8 num_postfences;
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u8 num_in_task_status;
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u8 num_sof_task_status;
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u8 num_eof_task_status;
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u8 num_sof_timestamps;
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u8 num_eof_timestamps;
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u32 num_addresses;
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u32 fence;
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u32 fence_counter;
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struct kref ref;
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struct list_head list;
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struct dla_task_descriptor *task_desc;
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dma_addr_t task_desc_pa;
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size_t buf_size;
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int timeout;
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int pool_index;
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struct dma_buf *memory_dmabuf[NVDLA_MAX_BUFFERS_PER_TASK];
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struct dma_buf *prefences_sem_dmabuf[MAX_NUM_NVDLA_PREFENCES];
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struct dma_buf *in_task_status_dmabuf[MAX_NUM_NVDLA_IN_TASK_STATUS];
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struct dma_buf *postfences_sem_dmabuf[MAX_NUM_NVDLA_POSTFENCES];
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struct dma_buf *sof_task_status_dmabuf[MAX_NUM_NVDLA_OUT_TASK_STATUS];
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struct dma_buf *eof_task_status_dmabuf[MAX_NUM_NVDLA_OUT_TASK_STATUS];
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struct dma_buf *sof_timestamps_dmabuf[MAX_NUM_NVDLA_OUT_TIMESTAMP];
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struct dma_buf *eof_timestamps_dmabuf[MAX_NUM_NVDLA_OUT_TIMESTAMP];
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};
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struct dla_mem_addr {
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uint64_t val;
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};
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extern const struct file_operations tegra_nvdla_ctrl_ops;
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extern struct nvdla_queue_ops nvdla_queue_ops;
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/**
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* nvhost_nvdla_finalize_poweron() finalize power on for DLA
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*
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* @pdev Pointer for platform device
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*
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* Return 0 on success otherwise negative
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*
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* This function called from nvhost ACM subsystem,
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* to boot falcon and wait until falcon goes idle after initial setup
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*/
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int nvhost_nvdla_finalize_poweron(struct platform_device *pdev);
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/**
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* nvhost_nvdla_prepare_poweron() prepare to poweroff DLA
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*
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* @pdev Pointer for platform device
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*
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* Return 0 on success otherwise negative
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*
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* This function called from nvhost ACM subsystem,
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* disables falcon interrupts and pass PM core to powergate and clockgate
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*/
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int nvhost_nvdla_prepare_poweroff(struct platform_device *pdev);
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/**
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* nvhost_nvdla_flcn_isr() falcon interrupt handler
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*
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* @pdev Pointer for platform device
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*
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* Return 0 on success otherwise negative
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*
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* This function called from nvhost falcon subsystem on recieving falcon
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* interrupt, like INT_ON_COMPLETE, INT_ON_ERR, DLA_DEBUG etc.
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*/
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int nvhost_nvdla_flcn_isr(struct platform_device *pdev);
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/**
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* nvdla_send_cmd() send command to DLA
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*
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* @pdev Pointer for platform device
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* @cmd_data Pointer command data
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*
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* Return 0 on success otherwise negative
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*
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* This function used to send method to falcon embedding different supporting
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* command. This uses THI registers to send method id and method data
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*/
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int nvdla_send_cmd(struct platform_device *pdev,
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struct nvdla_cmd_data *cmd_data);
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/**
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* nvdla_task_put() decrease task reference count
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*
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* @task Pointer to task in operation
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*
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* Return void
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*
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* This function puts task reference count and zero reference count
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* invokes function to free task.
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*/
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void nvdla_task_put(struct nvdla_task *task);
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/**
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* nvdla_task_get() increase task reference count
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*
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* @task Pointer to task in operation
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*
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* Return void
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*
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* This function gets task reference count
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*/
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void nvdla_task_get(struct nvdla_task *task);
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/**
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* nvdla_task_alloc() allocate task for a give queue
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*
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* @task Pointer to nvdla_task
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*
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* Return allocated task in success, otherwise pointer to err
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*
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* This function allocates task desc and fills up initial task descriptor as
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* task parameter detais
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*/
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int nvdla_fill_task_desc(struct nvdla_task *task);
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/**
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* nvdla_send_postfences() send back fences to UMD
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*
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* @task Pointer to nvhost queue
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* @usr_task Pointer to user task to be updated
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*
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* Return 0 on success otherwise negative
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*
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* This function send post fences back to UMD after task submit
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*/
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int nvdla_send_postfences(struct nvdla_task *task,
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struct nvdla_ioctl_submit_task *usr_task);
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int nvdla_get_cmd_memory(struct platform_device *pdev,
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struct nvdla_cmd_mem_info *cmd_mem_info);
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int nvdla_put_cmd_memory(struct platform_device *pdev, int index);
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int nvdla_set_queue_state(struct nvdla_queue *queue, int cmd);
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int nvdla_get_task_mem(struct nvdla_queue *queue,
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struct nvdla_task **task);
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void nvdla_put_task_mem(struct nvdla_task *task);
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size_t nvdla_get_max_task_size(void);
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int nvdla_alloc_gcov_region(struct platform_device *pdev);
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int nvdla_free_gcov_region(struct platform_device *pdev, bool update_region);
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int nvdla_emulator_submit(struct nvdla_queue *queue,
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struct nvdla_emu_task *task);
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void task_free(struct kref *ref);
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int nvdla_get_signal_fences(struct nvdla_queue *queue, void *in_task);
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int nvdla_send_gos_region(struct platform_device *pdev);
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#endif /* End of __NVHOST_NVDLA_H__ */
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