248 lines
5.8 KiB
C
248 lines
5.8 KiB
C
/*
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* Copyright (c) 2016-2019 NVIDIA Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _PVA_TASK_H_
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#define _PVA_TASK_H_
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#define TASK_VERSION_ID 0x01
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#define PVA_TASK_VERSION_ID 0x01
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#define PVA_ENGINE_ID 'P'
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#define PVA_MAX_PREACTION_LISTS 1U
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#define PVA_MAX_POSTACTION_LISTS 1U
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/*
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* These are not the in DRAM representations of the action list elements,
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* they are repackaged to allow for them to be managed more efficiently.
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*/
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struct pva_task_action_ptr {
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u64 p;
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u32 v;
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} __packed;
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struct pva_task_action_gos {
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u8 gos;
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u16 ofs;
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u32 v;
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} __packed;
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struct pva_task_action_status {
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u64 p;
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u16 status;
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} __packed;
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/*
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* Generic task meta-data for the CV pipeline.
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*/
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struct pva_gen_task {
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u64 next; /* ptr to next task in the list */
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u8 versionid;
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u8 engineid;
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u16 length;
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u16 sequence;
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u8 n_preaction_lists;
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u8 n_postaction_lists;
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u16 preaction_lists_p;
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u16 postaction_lists_p;
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} __packed;
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/*
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* Structure pointed to by {pre/post}action_lists_p. This points
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* to the actual action list.
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*/
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struct pva_action_list {
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u16 offset;
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u16 length;
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} __packed;
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enum pva_task_action_ids_e {
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TASK_ACT_TERMINATE = 0x00U,
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TASK_ACT_NEXT = 0x01U,
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TASK_ACT_RESTART = 0x02U,
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TASK_ACT_ERROR = 0x03U,
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TASK_ACT_STOP = 0x10U,
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TASK_ACT_DEV_SPEC_1ST = 0x40U,
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TASK_ACT_PVA_STATISTICS = 0x40U,
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TASK_ACT_PVA_VPU_PERF_COUNTERS = 0x50U,
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TASK_ACT_DEV_SPEC_LAST = 0x7FU,
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TASK_ACT_PTR_WRITE_VAL = 0x80U,
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TASK_ACT_PTR_WRITE_VAL_SFRAME = 0x81U,
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TASK_ACT_PTR_INCR = 0x82U,
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TASK_ACT_PTR_WRITE_VAL_TS = 0x83U,
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TASK_ACT_PTR_WRITE_VAL_SFRAME_TS = 0x84U,
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TASK_ACT_PTR_INCR_TS = 0x85U,
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TASK_ACT_PTR_BLK_EQUAL = 0x90U,
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TASK_ACT_PTR_BLK_EQUAL_SFRAME = 0x91U,
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TASK_ACT_PTR_BLK_GTREQL = 0x92U,
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TASK_ACT_PTR_BLK_GTREQL_SFRAME = 0x93U,
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TASK_ACT_GOS_WRITE_VAL = 0xA0U,
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TASK_ACT_GOS_WRITE_VAL_SFRAME = 0xA1U,
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TASK_ACT_GOS_INCR = 0xA2U,
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TASK_ACT_GOS_BLK_EQUAL = 0xB0U,
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TASK_ACT_GOS_BLK_EQUAL_SFRAME = 0xB1U,
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TASK_ACT_GOS_BLK_GTREQL = 0xB2U,
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TASK_ACT_GOS_BLK_GTREQL_SFRAME = 0xB3U,
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TASK_ACT_READ_STATUS = 0xC0U,
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TASK_ACT_WRITE_STATUS = 0xC1U,
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TASK_ACT_PTR_WRITE_SOT_V_TS = 0xC2U,
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TASK_ACT_PTR_WRITE_SOT_R_TS = 0xC3U,
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TASK_ACT_PTR_WRITE_EOT_V_TS = 0xC4U,
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TASK_ACT_PTR_WRITE_EOT_R_TS = 0xC5U,
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TASK_ACT_PTR_WRITE_TS = 0xC6U,
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TASK_ACT_PTR_WRITE_VAL_SOT_V = 0xC7U,
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TASK_ACT_PTR_WRITE_VAL_SOT_R = 0xC8U,
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TASK_ACT_PTR_WRITE_VAL_EOT_V = 0xC9U,
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TASK_ACT_PTR_WRITE_VAL_EOT_R = 0xCAU
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};
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struct pva_gen_task_status {
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u64 timestamp;
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u32 engine_status;
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u16 subframe;
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u16 status_task;
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};
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struct pva_task_statistics {
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u64 queued_time; /* when task was accepted by PVA */
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u64 head_time; /* when task reached head of queue */
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u64 input_actions_complete; /* when input actions done */
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u64 vpu_assigned_time; /* when task assigned a VPU */
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u64 vpu_start_time; /* when VPU started running task */
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u64 vpu_complete_time; /* when execution completed */
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u64 complete_time; /* when task considered complete */
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u8 vpu_assigned; /* which VPU task was assigned */
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u8 reserved[7];
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};
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/*
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* PVA specific task structure.
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*/
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#define PVA_TASK_FL_ATOMIC (1 << 0)
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#define PVA_TASK_FL_CV_RD_SCALARS (1 << 1)
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#define PVA_TASK_FL_CV_WR_SCALARS (1 << 2)
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#define PVA_TASK_FL_CV_WR_ROI (1 << 3)
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#define PVA_TASK_FL_VPU_DEBUG (1 << 4)
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struct pva_task {
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struct pva_gen_task gen_task;
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u8 runlist_version;
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u8 queue_id;
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u8 num_input_parameters;
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u8 num_output_parameters;
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u8 operation_version;
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u8 reserved;
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u16 input_parameters;
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u16 output_parameters;
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u16 flags;
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u32 operation;
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u64 timeout;
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u8 r5_reserved[32];
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}__packed;
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enum pva_task_parameter_type_e {
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PVA_PARAM_FIRST = 0U, /* must match first type */
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PVA_PARAM_SCALAR_LIST = 0U,
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PVA_PARAM_SURFACE_LIST = 1U,
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PVA_PARAM_ROI_LIST = 2U,
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PVA_PARAM_2DPOINTS_LIST = 3U,
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PVA_PARAM_OPAQUE_DATA = 4U,
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PVA_PARAM_LAST = 5U, /* must be last! */
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};
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#define PVA_TASK_POINTER_AUX_SIZE_MASK 0x00ffffffffffffffULL
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#define PVA_TASK_POINTER_AUX_SIZE_SHIFT 0
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#define PVA_TASK_POINTER_AUX_FLAGS_MASK 0xff00000000000000ULL
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#define PVA_TASK_POINTER_AUX_FLAGS_SHIFT 56
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#define PVA_TASK_POINTER_AUX_FLAGS_CVNAS (1 << 0)
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struct pva_task_pointer {
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u64 address;
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u64 aux;
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} __packed;
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struct pva_task_opaque_data_desc {
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u16 primary_payload_size;
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} __packed;
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struct pva_task_parameter_array {
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u64 address;
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u32 size;
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u32 type;
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};
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/*
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* Parameter descriptor (all parameters have the same header)
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* the specific data for the parameters immediately follows
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* the descriptor.
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*/
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struct pva_task_parameter_desc {
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u32 num_parameters;
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u32 reserved;
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};
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/*
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* Individual Region of Interest (ROI) descriptor
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*/
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struct pva_task_roi_desc {
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u32 left;
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u32 top;
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u32 right;
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u32 bottom;
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};
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/*
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* Surface descriptor
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*/
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struct pva_task_surface {
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u64 address;
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u64 roi_addr;
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u32 roi_size;
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u32 surface_size;
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u32 width;
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u32 height;
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u32 line_stride;
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u32 plane_stride;
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u32 num_planes;
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u8 layout;
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u8 block_height_log2;
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u8 memory;
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u8 reserved;
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u64 format;
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};
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/*
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* 2-dimentional point descriptor
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*/
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struct pva_task_point2d {
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u32 x;
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u32 y;
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};
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/*
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* Surface Layout.
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*/
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#define PVA_TASK_SURFACE_LAYOUT_PITCH_LINEAR 0U
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#define PVA_TASK_SURFACE_LAYOUT_BLOCK_LINEAR 1U
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/*
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* Where the surface is located.
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*/
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#define PVA_TASK_SURFACE_MEM_FL_CV_SURFACE (1 << 0)
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#define PVA_TASK_SURFACE_MEM_FL_CV_ROI (1 << 1)
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#endif
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