163 lines
4.9 KiB
C
163 lines
4.9 KiB
C
/*
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* PVA mailbox header
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*
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* Copyright (c) 2016-2018, NVIDIA Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __PVA_MAILBOX_H__
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#define __PVA_MAILBOX_H__
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#include <linux/platform_device.h>
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#include "pva-interface.h"
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/* Total CCQ status registers */
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#define PVA_CCQ_STATUS_REGS 9
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/* Symbolic definitions of the CCQ status registers */
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#define PVA_CCQ_STATUS0_INDEX 0
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#define PVA_CCQ_STATUS1_INDEX 1
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#define PVA_CCQ_STATUS2_INDEX 2
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#define PVA_CCQ_STATUS3_INDEX 3
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#define PVA_CCQ_STATUS4_INDEX 4
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#define PVA_CCQ_STATUS5_INDEX 5
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#define PVA_CCQ_STATUS6_INDEX 6
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#define PVA_CCQ_STATUS7_INDEX 7
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#define PVA_CCQ_STATUS8_INDEX 8
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/* Number of valid MBOX registers used for sending commands */
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#define VALID_MB_INPUT_REGS 4
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/* Number of valid MBOX registers */
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#define VALID_MB_INPUT_REGS_EX 8
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struct pva;
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/**
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* enum pva_mailbox_status - PVA mailbox status indication
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*
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* These enumerations reflect the state of PVA interrupt handler
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*/
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enum pva_mailbox_status {
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PVA_MBOX_STATUS_INVALID = 0,
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PVA_MBOX_STATUS_WFI = 1,
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PVA_MBOX_STATUS_DONE = 2,
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PVA_MBOX_STATUS_ABORTED = 3,
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};
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/**
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* struct pva_mailbox_status_regs - Handle the MBOX status based on ISR
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*
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* @cmd: Holds the current MBOX command
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* @error: Holds the any error shown through ISR
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* @status: Holds the status of all CCQ registers
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*
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*/
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struct pva_mailbox_status_regs {
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uint32_t status[PVA_CCQ_STATUS_REGS];
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uint32_t error;
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uint32_t cmd;
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};
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/**
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* pva_mailbox_send_cmd_sync() - Send a command and wait for response
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*
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* @pva: Pointer to PVA structure
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* @pva_cmd: Pointer to the pva command struct
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* @nregs: Number of valid mailbox registers for the command
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* @mb_status_regs: Pointer to pva_mailbox_status_regs struct
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*
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* Return: 0 on Success or negative error code
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*
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* This function called by OS to pass the mailbox commands to
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* the PVA uCode. The function returns the output status from PVA
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* firmware once the task is completed.
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*
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* The caller is responsible to ensure that PVA has been powered
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* up through nvhost_module_busy() API prior calling this function.
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*/
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int pva_mailbox_send_cmd_sync(struct pva *pva,
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struct pva_cmd *cmd, u32 nregs,
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struct pva_mailbox_status_regs *mb_status_regs);
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/**
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* pva_mailbox_send_cmd_sync_locked() - Send a command and wait for response
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*
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* @pva: Pointer to PVA structure
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* @pva_cmd: Pointer to the pva command struct
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* @nregs: Number of valid mailbox registers for the command
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* @mb_status_regs: Pointer to pva_mailbox_status_regs struct
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*
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* Return: 0 on Success or negative error code
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*
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* This function called by OS to pass the mailbox commands to
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* the PVA uCode. The function returns the output status from PVA
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* firmware once the task is completed. This function must not be
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* used during runtime without holding the mailbox mutex (i.e.
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* the function can be called during PVA boot-up).
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*/
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int pva_mailbox_send_cmd_sync_locked(struct pva *pva,
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struct pva_cmd *cmd, u32 nregs,
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struct pva_mailbox_status_regs *mailbox_status_regs);
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/**
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* pva_mailbox_isr() - Handle interrupt for PVA ISR
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*
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* @pva: Pointer to PVA structure
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*
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* This function is used to read the CCQ status registers based on
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* the status set in mailbox7 by the PVA uCode.
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*/
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void pva_mailbox_isr(struct pva *pva);
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/**
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* pva_mailbox_wait_event() - mailbox wait event
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*
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* @pva:» Pointer to PVA structure
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* @wait_time» WaitTime Interval for the event
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*
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* This function do the wait until the mailbox isr get invoked based on
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* the mailbox register set by the ucode.
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*/
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int pva_mailbox_wait_event(struct pva *pva, int wait_time);
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/**
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* pva_read_mailbox() - read a mailbox register
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*
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* @pva: Pointer to PVA structure
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* @mbox: mailbox register to be written
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*
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* This function will read the indicated mailbox register and return its
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* contents. it uses side channel B as host would.
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*
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* Return Value:
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* contents of the indicated mailbox register
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*/
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u32 pva_read_mailbox(struct platform_device *pdev, u32 mbox_id);
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/**
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* pva_write_mailbox() - write to a mailbox register
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*
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* @pva: Pointer to PVA structure
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* @mbox: mailbox register to be written
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* @value: value to be written into the mailbox register
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*
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* This function will write a value into the indicated mailbox register.
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*
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* Return Value:
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* none
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*/
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void pva_write_mailbox(struct platform_device *pdev, u32 mbox_id, u32 value);
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#endif /*__PVA_MAINBOX_H__*/
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