2072 lines
142 KiB
C
2072 lines
142 KiB
C
/*
|
|
* Copyright (c) 2017, NVIDIA Corporation. All rights reserved.
|
|
*
|
|
* This software is licensed under the terms of the GNU General Public
|
|
* License version 2, as published by the Free Software Foundation, and
|
|
* may be copied, distributed, and modified under those terms.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*/
|
|
|
|
#ifndef __MACH_TEGRA_MC_REGS_T19X_H__
|
|
#define __MACH_TEGRA_MC_REGS_T19X_H__
|
|
|
|
/* Auto generated. Do not edit. */
|
|
#define MC_MCF_ORSPX_RDRSP 0x8004
|
|
#define MC_MCF_ORSPX_WRRSP 0x8008
|
|
#define MC_MCF_IRSPX_RDRSP_OPT 0x800c
|
|
#define MC_MCF_ORSPX_CLKEN_OVERRIDE 0x8010
|
|
#define MC_MCF_IRSPX_CLKEN_OVERRIDE 0x8014
|
|
#define MC_MCF_ORSPX_PM_FIFO_SRC_MATCH 0x8018
|
|
#define MC_MCF_ORSPX_PM_FIFO_CONFIG 0x801c
|
|
#define MC_MCF_IRSPX_PM_FIFO_SRC_MATCH 0x8020
|
|
#define MC_MCF_IREQX_VCARB_CONFIG 0x8100
|
|
#define MC_MCF_OREQX_VCARB_CONFIG 0x8104
|
|
#define MC_MCF_OREQX_LLARB_CONFIG 0x8108
|
|
#define MC_MCF_IREQX_SRC_WEIGHT_0 0x810c
|
|
#define MC_MCF_IREQX_SRC_WEIGHT_1 0x8110
|
|
#define MC_MCF_IREQX_CLKEN_OVERRIDE 0x8114
|
|
#define MC_MCF_OREQX_CLKEN_OVERRIDE 0x8118
|
|
#define MC_MCF_IREQX_PM_FIFO_SRC_MATCH0 0x8130
|
|
#define MC_MCF_IREQX_PM_FIFO_SRC_MATCH1 0x8134
|
|
#define MC_MCF_IREQX_PM_FIFO_SUM_MSK 0x8138
|
|
#define MC_MCF_IREQX_PM_FIFO_SRC_MISC 0x813c
|
|
#define MC_MCF_OREQX_PM_FIFO_SRC_MATCH0 0x8140
|
|
#define MC_MCF_OREQX_PM_FIFO_SRC_MATCH1 0x8144
|
|
#define MC_MCF_OREQX_PM_FIFO_SUM_MSK 0x8148
|
|
#define MC_MCF_OREQX_PM_FIFO_SRC_MISC 0x814c
|
|
#define MC_MCF_IREQX_HUB_FIFO_NISO 0x8200
|
|
#define MC_MCF_IREQX_HUB_FIFO_SISO 0x8204
|
|
#define MC_MCF_IREQX_HUB_FIFO_ISO 0x8208
|
|
#define MC_MCF_IREQX_HUB_FIFO_TRANS_DONE 0x820c
|
|
#define MC_MCF_IREQX_HUB_FIFO_ORD_1 0x8214
|
|
#define MC_MCF_IREQX_HUB_FIFO_ORD_2 0x8218
|
|
#define MC_MCF_IREQX_HUB_FIFO_ORD_3 0x821c
|
|
#define MC_MCF_IREQX_HUB_FIFO_SHARED 0x8220
|
|
#define MC_MCF_IREQX_NVL_FIFO_NISO 0x8224
|
|
#define MC_MCF_IREQX_NVL_FIFO_SISO 0x8228
|
|
#define MC_MCF_IREQX_NVL_FIFO_ISO 0x822c
|
|
#define MC_MCF_IREQX_NVL_FIFO_TRANS_DONE 0x8230
|
|
#define MC_MCF_IREQX_NVL_FIFO_ORD_1 0x8238
|
|
#define MC_MCF_IREQX_NVL_FIFO_ORD_2 0x823c
|
|
#define MC_MCF_IREQX_NVL_FIFO_ORD_3 0x8240
|
|
#define MC_MCF_IREQX_NVL_FIFO_SHARED 0x8244
|
|
#define MC_MCF_OREQX_MCF_FIFO_NISO 0x8248
|
|
#define MC_MCF_OREQX_MCF_FIFO_SISO 0x824c
|
|
#define MC_MCF_OREQX_MCF_FIFO_ISO 0x8250
|
|
#define MC_MCF_OREQX_MCF_FIFO_CPU_LL 0x8254
|
|
#define MC_MCF_OREQX_MCF_FIFO_NISO_REMOTE 0x8258
|
|
#define MC_MCF_OREQX_MCF_FIFO_SHARED 0x825c
|
|
#define MC_MCF_OREQX_SCF_FIFO_NISO 0x8260
|
|
#define MC_MCF_OREQX_SCF_FIFO_SISO 0x8264
|
|
#define MC_MCF_OREQX_SCF_FIFO_ISO 0x8268
|
|
#define MC_MCF_OREQX_SCF_FIFO_CPU_LL 0x826c
|
|
#define MC_MCF_OREQX_SCF_FIFO_NISO_REMOTE 0x8270
|
|
#define MC_MCF_OREQX_SCF_FIFO_SHARED 0x8274
|
|
#define MC_MCF_OREQX_SCF_LLFIFO_CPU_LL 0x8278
|
|
#define MC_MCF_SLICE_CFG 0x8300
|
|
#define MC_MCF_SLICE_FL_NISO_LIMIT 0x8304
|
|
#define MC_MCF_SLICE_FL_SISO_LIMIT 0x8308
|
|
#define MC_MCF_SLICE_FL_ISO_LIMIT 0x830c
|
|
#define MC_MCF_SLICE_FL_TRANSDONE_LIMIT 0x8310
|
|
#define MC_MCF_SLICE_FL_NISO_REMOTE_LIMIT 0x8314
|
|
#define MC_MCF_SLICE_FL_ORD1_LIMIT 0x8318
|
|
#define MC_MCF_SLICE_FL_ORD2_LIMIT 0x831c
|
|
#define MC_MCF_SLICE_FL_ORD3_LIMIT 0x8320
|
|
#define MC_MCF_SLICE_CLKEN_OVERRIDE 0x8324
|
|
#define MC_MSS_SYSRAM_INIT 0x8c00
|
|
#define MC_MSS_SYSRAM_CLKEN_OVERRIDE 0x8c04
|
|
#define MC_MSS_SBS_ASYNC 0x8f00
|
|
#define MC_MSS_SBS_ARB 0x8f04
|
|
#define MC_MSS_SBS_INTSTATUS 0x8f08
|
|
#define MC_MSS_SBS_INTMASK 0x8f0c
|
|
#define MC_MSS_SBS_CLKEN_OVERRIDE 0x8f10
|
|
#define MC_MSS_SBS_VC_LIMIT 0x8f14
|
|
#define MC_REGIF_CONFIG 0xf80
|
|
#define MC_REGIF_CONFIG_1 0xf8c
|
|
#define MC_REGIF_CONFIG_2 0x3700
|
|
#define MC_REGIF_BROADCAST 0xf84
|
|
#define MC_REGIF_BROADCAST_1 0xf88
|
|
#define MC_REGIF_BROADCAST_2 0x3704
|
|
#define MC_REGIF_UNICAST0 0xf90
|
|
#define MC_REGIF_UNICAST0_1 0x1134
|
|
#define MC_REGIF_UNICAST0_2 0x370c
|
|
#define MC_REGIF_UNICAST1 0xf94
|
|
#define MC_REGIF_UNICAST1_1 0x1140
|
|
#define MC_REGIF_UNICAST1_2 0x3710
|
|
#define MC_REGIF_UNICAST2 0xf98
|
|
#define MC_REGIF_UNICAST2_1 0x1144
|
|
#define MC_REGIF_UNICAST2_2 0x3714
|
|
#define MC_REGIF_UNICAST3 0xf9c
|
|
#define MC_REGIF_UNICAST3_1 0x1148
|
|
#define MC_REGIF_UNICAST3_2 0x3718
|
|
#define MC_REGIF_UNICAST4 0x1164
|
|
#define MC_REGIF_UNICAST4_1 0x114c
|
|
#define MC_REGIF_UNICAST4_2 0x371c
|
|
#define MC_REGIF_UNICAST5 0x1168
|
|
#define MC_REGIF_UNICAST5_1 0x1150
|
|
#define MC_REGIF_UNICAST5_2 0x3720
|
|
#define MC_REGIF_UNICAST6 0x116c
|
|
#define MC_REGIF_UNICAST6_1 0x1154
|
|
#define MC_REGIF_UNICAST6_2 0x3724
|
|
#define MC_REGIF_UNICAST7 0x1170
|
|
#define MC_REGIF_UNICAST7_1 0x1160
|
|
#define MC_REGIF_UNICAST7_2 0x3728
|
|
#define MC_REGIF_UNICAST8 0x372c
|
|
#define MC_REGIF_UNICAST8_1 0x374c
|
|
#define MC_REGIF_UNICAST8_2 0x376c
|
|
#define MC_REGIF_UNICAST9 0x3730
|
|
#define MC_REGIF_UNICAST9_1 0x3750
|
|
#define MC_REGIF_UNICAST9_2 0x3770
|
|
#define MC_REGIF_UNICAST10 0x3734
|
|
#define MC_REGIF_UNICAST10_1 0x3754
|
|
#define MC_REGIF_UNICAST10_2 0x3774
|
|
#define MC_REGIF_UNICAST11 0x3738
|
|
#define MC_REGIF_UNICAST11_1 0x3758
|
|
#define MC_REGIF_UNICAST11_2 0x3778
|
|
#define MC_REGIF_UNICAST12 0x373c
|
|
#define MC_REGIF_UNICAST12_1 0x375c
|
|
#define MC_REGIF_UNICAST12_2 0x377c
|
|
#define MC_REGIF_UNICAST13 0x3740
|
|
#define MC_REGIF_UNICAST13_1 0x3760
|
|
#define MC_REGIF_UNICAST13_2 0x3780
|
|
#define MC_REGIF_UNICAST14 0x3744
|
|
#define MC_REGIF_UNICAST14_1 0x3764
|
|
#define MC_REGIF_UNICAST14_2 0x3784
|
|
#define MC_REGIF_UNICAST15 0x3748
|
|
#define MC_REGIF_UNICAST15_1 0x3768
|
|
#define MC_REGIF_UNICAST15_2 0x3788
|
|
#define MC_INTSTATUS 0x0
|
|
#define MC_INTMASK 0x4
|
|
#define MC_INTPRIORITY 0xec4
|
|
#define MC_HUBC_INTSTATUS 0xf2c
|
|
#define MC_HUB_INTMASK 0xf50
|
|
#define MC_HUB_INTPRIORITY 0xf54
|
|
#define MC_HUB_INTSTATUS 0xf58
|
|
#define MC_GLOBAL_INTSTATUS 0xf24
|
|
#define MC_GLOBAL_CRITICAL_INTSTATUS 0xf28
|
|
#define MC_GLOBAL_INTSTATUS_1 0x37e0
|
|
#define MC_GLOBAL_CRITICAL_INTSTATUS_1 0x37e4
|
|
#define MC_ERR_STATUS 0x8
|
|
#define MC_ERR_ADR 0xc
|
|
#define MC_ERR_ADR_HI 0x11fc
|
|
#define MC_PCFIFO_CLIENT_CONFIG0 0xdd0
|
|
#define MC_PCFIFO_CLIENT_CONFIG1 0xdd4
|
|
#define MC_PCFIFO_CLIENT_CONFIG2 0xdd8
|
|
#define MC_PCFIFO_CLIENT_CONFIG3 0xddc
|
|
#define MC_PCFIFO_CLIENT_CONFIG4 0xde0
|
|
#define MC_PCFIFO_CLIENT_CONFIG5 0xbf4
|
|
#define MC_PCFIFO_CLIENT_CONFIG6 0xb90
|
|
#define MC_PCFIFO_CLIENT_CONFIG7 0xacc
|
|
#define MC_EMEM_CFG 0x50
|
|
#define MC_EMEM_ADR_CFG 0x54
|
|
#define MC_EMEM_ADR_CFG_DEV0 0x58
|
|
#define MC_EMEM_ADR_CFG_DEV1 0x5c
|
|
#define MC_EMEM_ADR_CFG_CHANNEL_ENABLE 0xdf8
|
|
#define MC_EMEM_ADR_CFG_CHANNEL_MASK 0x60
|
|
#define MC_EMEM_ADR_CFG_CHANNEL_MASK_1 0xdfc
|
|
#define MC_EMEM_ADR_CFG_CHANNEL_MASK_2 0xdf4
|
|
#define MC_EMEM_ADR_CFG_CHANNEL_MASK_3 0xdf0
|
|
#define MC_EMEM_ADR_CFG_BANK_MASK_0 0x64
|
|
#define MC_EMEM_ADR_CFG_BANK_MASK_1 0x68
|
|
#define MC_EMEM_ADR_CFG_BANK_MASK_2 0x6c
|
|
#define MC_SECURITY_CFG0 0x70
|
|
#define MC_SECURITY_CFG1 0x74
|
|
#define MC_SECURITY_CFG_REG_CTRL 0x154
|
|
#define MC_SECURITY_CFG3 0x9bc
|
|
#define MC_SECURITY_RSV 0x7c
|
|
#define MC_EMEM_ARB_CFG 0x90
|
|
#define MC_EMEM_ARB_OUTSTANDING_REQ 0x94
|
|
#define MC_EMEM_ARB_TIMING_RCD 0x98
|
|
#define MC_EMEM_ARB_TIMING_RP 0x9c
|
|
#define MC_EMEM_ARB_TIMING_RC 0xa0
|
|
#define MC_EMEM_ARB_TIMING_RAS 0xa4
|
|
#define MC_EMEM_ARB_TIMING_FAW 0xa8
|
|
#define MC_EMEM_ARB_TIMING_RRD 0xac
|
|
#define MC_EMEM_ARB_TIMING_RAP2PRE 0xb0
|
|
#define MC_EMEM_ARB_TIMING_WAP2PRE 0xb4
|
|
#define MC_EMEM_ARB_TIMING_R2R 0xb8
|
|
#define MC_EMEM_ARB_TIMING_W2W 0xbc
|
|
#define MC_EMEM_ARB_TIMING_R2W 0xc0
|
|
#define MC_EMEM_ARB_TIMING_W2R 0xc4
|
|
#define MC_EMEM_ARB_TIMING_RFCPB 0x6c0
|
|
#define MC_EMEM_ARB_TIMING_CCDMW 0x6c4
|
|
#define MC_EMEM_ARB_TIMING_PBR2PBR 0x6c8
|
|
#define MC_EMEM_ARB_TIMING_PDEX 0x6cc
|
|
#define MC_EMEM_ARB_TIMING_SREX 0x6d0
|
|
#define MC_EMEM_ARB_REFPB_HP_CTRL 0x6f0
|
|
#define MC_EMEM_ARB_REFPB_BANK_CTRL 0x6f4
|
|
#define MC_EMEM_ARB_DA_TURNS 0xd0
|
|
#define MC_EMEM_ARB_DA_COVERS 0xd4
|
|
#define MC_EMEM_ARB_DA_HYSTERESIS 0x9fc
|
|
#define MC_EMEM_ARB_MISC0 0xd8
|
|
#define MC_EMEM_ARB_MISC1 0xdc
|
|
#define MC_EMEM_ARB_MISC2 0xc8
|
|
#define MC_EMEM_ARB_MISC3 0x23c
|
|
#define MC_EMEM_ARB_MISC4 0x240
|
|
#define MC_EMEM_ARB_RING1_THROTTLE 0xe0
|
|
#define MC_EMEM_ARB_RING3_THROTTLE 0xe4
|
|
#define MC_EMEM_ARB_NISO_THROTTLE 0x6b0
|
|
#define MC_EMEM_ARB_OVERRIDE 0xe8
|
|
#define MC_EMEM_ARB_RSV 0xec
|
|
#define MC_CLKEN_OVERRIDE 0xf4
|
|
#define MC_HUB_CLKEN_OVERRIDE 0xfa0
|
|
#define MC_HUB_VCTHROTTLE_OVERRIDE 0xfa4
|
|
#define MC_CLKEN_A1_OVERRIDE 0xcc
|
|
#define MC_TIMING_CONTROL_DBG 0xf8
|
|
#define MC_TIMING_CONTROL 0xfc
|
|
#define MC_STAT_CONTROL 0x100
|
|
#define MC_STAT_STATUS 0x104
|
|
#define MC_STAT_EMC_CLOCK_LIMIT 0x108
|
|
#define MC_STAT_EMC_CLOCK_LIMIT_MSBS 0x10c
|
|
#define MC_STAT_EMC_CLOCKS 0x110
|
|
#define MC_STAT_EMC_CLOCKS_MSBS 0x114
|
|
#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_LO 0x118
|
|
#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_LO 0x158
|
|
#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_HI 0x11c
|
|
#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_HI 0x15c
|
|
#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_UPPER 0xa20
|
|
#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_UPPER 0xa24
|
|
#define MC_STAT_EMC_FILTER_SET0_VIRTUAL_ADR_LIMIT_LO 0x198
|
|
#define MC_STAT_EMC_FILTER_SET1_VIRTUAL_ADR_LIMIT_LO 0x1a8
|
|
#define MC_STAT_EMC_FILTER_SET0_VIRTUAL_ADR_LIMIT_HI 0x19c
|
|
#define MC_STAT_EMC_FILTER_SET1_VIRTUAL_ADR_LIMIT_HI 0x1ac
|
|
#define MC_STAT_EMC_FILTER_SET0_VIRTUAL_ADR_LIMIT_UPPER 0xa28
|
|
#define MC_STAT_EMC_FILTER_SET1_VIRTUAL_ADR_LIMIT_UPPER 0xa2c
|
|
#define MC_STAT_EMC_FILTER_SET0_ASID 0x1a0
|
|
#define MC_STAT_EMC_FILTER_SET1_ASID 0x1b0
|
|
#define MC_STAT_EMC_FILTER_SET0_SLACK_LIMIT 0x120
|
|
#define MC_STAT_EMC_FILTER_SET1_SLACK_LIMIT 0x160
|
|
#define MC_STAT_EMC_FILTER_SET0_CLIENT_0 0x128
|
|
#define MC_STAT_EMC_FILTER_SET1_CLIENT_0 0x168
|
|
#define MC_STAT_EMC_FILTER_SET0_CLIENT_1 0x12c
|
|
#define MC_STAT_EMC_FILTER_SET1_CLIENT_1 0x16c
|
|
#define MC_STAT_EMC_FILTER_SET0_CLIENT_2 0x130
|
|
#define MC_STAT_EMC_FILTER_SET1_CLIENT_2 0x170
|
|
#define MC_STAT_EMC_FILTER_SET0_CLIENT_3 0x134
|
|
#define MC_STAT_EMC_FILTER_SET0_CLIENT_4 0xb88
|
|
#define MC_STAT_EMC_FILTER_SET0_CLIENT_5 0xbc4
|
|
#define MC_STAT_EMC_FILTER_SET0_CLIENT_6 0xac4
|
|
#define MC_STAT_EMC_FILTER_SET0_CLIENT_7 0xac8
|
|
#define MC_STAT_EMC_FILTER_SET1_CLIENT_3 0x174
|
|
#define MC_STAT_EMC_FILTER_SET1_CLIENT_4 0xb8c
|
|
#define MC_STAT_EMC_FILTER_SET1_CLIENT_5 0xbc8
|
|
#define MC_STAT_EMC_FILTER_SET1_CLIENT_6 0xec8
|
|
#define MC_STAT_EMC_FILTER_SET1_CLIENT_7 0xecc
|
|
#define MC_STAT_EMC_SET0_COUNT 0x138
|
|
#define MC_STAT_EMC_SET0_COUNT_MSBS 0x13c
|
|
#define MC_STAT_EMC_SET1_COUNT 0x178
|
|
#define MC_STAT_EMC_SET1_COUNT_MSBS 0x17c
|
|
#define MC_STAT_EMC_SET0_SLACK_ACCUM 0x140
|
|
#define MC_STAT_EMC_SET0_SLACK_ACCUM_MSBS 0x144
|
|
#define MC_STAT_EMC_SET1_SLACK_ACCUM 0x180
|
|
#define MC_STAT_EMC_SET1_SLACK_ACCUM_MSBS 0x184
|
|
#define MC_STAT_EMC_SET0_HISTO_COUNT 0x148
|
|
#define MC_STAT_EMC_SET0_HISTO_COUNT_MSBS 0x14c
|
|
#define MC_STAT_EMC_SET1_HISTO_COUNT 0x188
|
|
#define MC_STAT_EMC_SET1_HISTO_COUNT_MSBS 0x18c
|
|
#define MC_STAT_EMC_SET0_MINIMUM_SLACK_OBSERVED 0x150
|
|
#define MC_STAT_EMC_SET1_MINIMUM_SLACK_OBSERVED 0x190
|
|
#define MC_STAT_EMC_SET0_IDLE_CYCLE_COUNT 0x1b8
|
|
#define MC_STAT_EMC_SET0_IDLE_CYCL_COUNT_MSBS 0x1bc
|
|
#define MC_STAT_EMC_SET1_IDLE_CYCLE_COUNT 0x1c8
|
|
#define MC_STAT_EMC_SET1_IDLE_CYCL_COUNT_MSBS 0x1cc
|
|
#define MC_STAT_EMC_SET0_IDLE_CYCLE_PARTITION_SELECT 0x1c0
|
|
#define MC_STAT_EMC_SET1_IDLE_CYCLE_PARTITION_SELECT 0x1d0
|
|
#define MC_CIFLL_MISC0 0xf60
|
|
#define MC_CIFLL_REDEADLINE0 0xf64
|
|
#define MC_CIFLL_REDEADLINE1 0xf68
|
|
#define MC_CIFLL_REQ_MT_FIFO_CREDITS 0xf6c
|
|
#define MC_CIFLL_WRDAT_MT_FIFO_CREDITS 0xf70
|
|
#define MC_CLIENT_HOTRESET_CTRL 0x200
|
|
#define MC_CLIENT_HOTRESET_CTRL_1 0x970
|
|
#define MC_CLIENT_HOTRESET_CTRL_2 0x97c
|
|
#define MC_CLIENT_HOTRESET_STATUS 0x204
|
|
#define MC_CLIENT_HOTRESET_STATUS_1 0x974
|
|
#define MC_EMEM_ARB_ISOCHRONOUS_0 0x208
|
|
#define MC_EMEM_ARB_ISOCHRONOUS_1 0x20c
|
|
#define MC_EMEM_ARB_ISOCHRONOUS_2 0x210
|
|
#define MC_EMEM_ARB_ISOCHRONOUS_3 0x214
|
|
#define MC_EMEM_ARB_ISOCHRONOUS_4 0xb94
|
|
#define MC_EMEM_ARB_ISOCHRONOUS_5 0xba8
|
|
#define MC_EMEM_ARB_ISOCHRONOUS_6 0xaac
|
|
#define MC_EMEM_ARB_ISOCHRONOUS_7 0xab0
|
|
#define MC_EMEM_ARB_HYSTERESIS_0 0x218
|
|
#define MC_EMEM_ARB_HYSTERESIS_1 0x21c
|
|
#define MC_EMEM_ARB_HYSTERESIS_2 0x220
|
|
#define MC_EMEM_ARB_HYSTERESIS_3 0x224
|
|
#define MC_EMEM_ARB_HYSTERESIS_4 0xb84
|
|
#define MC_EMEM_ARB_HYSTERESIS_5 0xba4
|
|
#define MC_EMEM_ARB_HYSTERESIS_6 0xef4
|
|
#define MC_EMEM_ARB_HYSTERESIS_7 0xef8
|
|
#define MC_EMEM_ARB_DHYSTERESIS_0 0xbb0
|
|
#define MC_EMEM_ARB_DHYSTERESIS_1 0xbb4
|
|
#define MC_EMEM_ARB_DHYSTERESIS_2 0xbb8
|
|
#define MC_EMEM_ARB_DHYSTERESIS_3 0xbbc
|
|
#define MC_EMEM_ARB_DHYSTERESIS_4 0xbc0
|
|
#define MC_EMEM_ARB_DHYSTERESIS_5 0xbf0
|
|
#define MC_EMEM_ARB_DHYSTERESIS_6 0x1d00
|
|
#define MC_EMEM_ARB_DHYSTERESIS_7 0x1d04
|
|
#define MC_EMEM_ARB_DHYST_CTRL 0xbcc
|
|
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0 0xbd0
|
|
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1 0xbd4
|
|
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2 0xbd8
|
|
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3 0xbdc
|
|
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4 0xbe0
|
|
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5 0xbe4
|
|
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6 0xbe8
|
|
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7 0xbec
|
|
#define MC_RESERVED_RSV 0x3fc
|
|
#define MC_UFSHCPC2_EXTRA_SNAP_LEVELS 0x4844
|
|
#define MC_BPMPPC_EXTRA_SNAP_LEVELS 0xa60
|
|
#define MC_PVA1XA3_EXTRA_SNAP_LEVELS 0x4818
|
|
#define MC_FTOP_EXTRA_SNAP_LEVELS 0x2bc
|
|
#define MC_MIU4_EXTRA_SNAP_LEVELS 0x4924
|
|
#define MC_MIU6_EXTRA_SNAP_LEVELS 0x492c
|
|
#define MC_VICPC3_EXTRA_SNAP_LEVELS 0xa80
|
|
#define MC_ISP2PC_EXTRA_SNAP_LEVELS 0x4910
|
|
#define MC_USBD2_EXTRA_SNAP_LEVELS 0x484c
|
|
#define MC_PVA1XB_EXTRA_SNAP_LEVELS 0x481c
|
|
#define MC_PVA0XB3_EXTRA_SNAP_LEVELS 0x4810
|
|
#define MC_VICPC_EXTRA_SNAP_LEVELS 0xa1c
|
|
#define MC_UFSHCPC_EXTRA_SNAP_LEVELS 0xa58
|
|
#define MC_MSEA_EXTRA_SNAP_LEVELS 0x4900
|
|
#define MC_USBX_EXTRA_SNAP_LEVELS 0x404
|
|
#define MC_PCIE4XA_EXTRA_SNAP_LEVELS 0x4800
|
|
#define MC_MSE2_EXTRA_SNAP_LEVELS 0xe08
|
|
#define MC_PVA0XA3_EXTRA_SNAP_LEVELS 0x4808
|
|
#define MC_PCIE4X_EXTRA_SNAP_LEVELS 0x4104
|
|
#define MC_DLA1XA2_EXTRA_SNAP_LEVELS 0x482c
|
|
#define MC_MIU3_EXTRA_SNAP_LEVELS 0x3260
|
|
#define MC_NVD2_EXTRA_SNAP_LEVELS 0xe00
|
|
#define MC_USBD_EXTRA_SNAP_LEVELS 0xa18
|
|
#define MC_PVA0XB2_EXTRA_SNAP_LEVELS 0x4834
|
|
#define MC_RCEPC_EXTRA_SNAP_LEVELS 0xe20
|
|
#define MC_MSE_EXTRA_SNAP_LEVELS 0x40c
|
|
#define MC_AUD_EXTRA_SNAP_LEVELS 0xa10
|
|
#define MC_DLA0XA_EXTRA_SNAP_LEVELS 0xe10
|
|
#define MC_PCIE0X2_EXTRA_SNAP_LEVELS 0x4914
|
|
#define MC_DLA0XA2_EXTRA_SNAP_LEVELS 0x4828
|
|
#define MC_PCIE0XA_EXTRA_SNAP_LEVELS 0x4118
|
|
#define MC_PCIE1X_EXTRA_SNAP_LEVELS 0x3270
|
|
#define MC_EQOSPC_EXTRA_SNAP_LEVELS 0xa5c
|
|
#define MC_MIU7_EXTRA_SNAP_LEVELS 0x4930
|
|
#define MC_MIU1_EXTRA_SNAP_LEVELS 0x3258
|
|
#define MC_HDAPC_EXTRA_SNAP_LEVELS 0xa48
|
|
#define MC_DLA0FALPC_EXTRA_SNAP_LEVELS 0x3264
|
|
#define MC_PVA1XB2_EXTRA_SNAP_LEVELS 0x483c
|
|
#define MC_PVA1XA_EXTRA_SNAP_LEVELS 0xe1c
|
|
#define MC_AONPC_EXTRA_SNAP_LEVELS 0xa68
|
|
#define MC_SD_EXTRA_SNAP_LEVELS 0xa04
|
|
#define MC_VE_EXTRA_SNAP_LEVELS 0x2d8
|
|
#define MC_SCEPC_EXTRA_SNAP_LEVELS 0xa70
|
|
#define MC_HOST_EXTRA_SNAP_LEVELS 0xa14
|
|
#define MC_JPG_EXTRA_SNAP_LEVELS 0xa3c
|
|
#define MC_DLA0XA3_EXTRA_SNAP_LEVELS 0x4110
|
|
#define MC_DIS_EXTRA_SNAP_LEVELS 0x2ac
|
|
#define MC_DLA1XA_EXTRA_SNAP_LEVELS 0xe14
|
|
#define MC_PCIE0X_EXTRA_SNAP_LEVELS 0x326c
|
|
#define MC_PCIE5X_EXTRA_SNAP_LEVELS 0x4108
|
|
#define MC_PVA0XC_EXTRA_SNAP_LEVELS 0x4814
|
|
#define MC_MSE3_EXTRA_SNAP_LEVELS 0x3250
|
|
#define MC_USBX2_EXTRA_SNAP_LEVELS 0x4848
|
|
#define MC_PVA0XA_EXTRA_SNAP_LEVELS 0xe18
|
|
#define MC_DLA1FALPC_EXTRA_SNAP_LEVELS 0x3268
|
|
#define MC_DLA1XA3_EXTRA_SNAP_LEVELS 0x4114
|
|
#define MC_PCIE5XA_EXTRA_SNAP_LEVELS 0x4804
|
|
#define MC_MIU5_EXTRA_SNAP_LEVELS 0x4928
|
|
#define MC_VICPC2_EXTRA_SNAP_LEVELS 0xa7c
|
|
#define MC_ISPPC_EXTRA_SNAP_LEVELS 0x490c
|
|
#define MC_PCIE1XA_EXTRA_SNAP_LEVELS 0x411c
|
|
#define MC_NVD6_EXTRA_SNAP_LEVELS 0x4920
|
|
#define MC_SDM_EXTRA_SNAP_LEVELS 0xa44
|
|
#define MC_APB_EXTRA_SNAP_LEVELS 0x2a4
|
|
#define MC_ISP_EXTRA_SNAP_LEVELS 0xa08
|
|
#define MC_MIU0_EXTRA_SNAP_LEVELS 0x3254
|
|
#define MC_PCIE5X2_EXTRA_SNAP_LEVELS 0x4840
|
|
#define MC_NIC_EXTRA_SNAP_LEVELS 0xa54
|
|
#define MC_MIU2_EXTRA_SNAP_LEVELS 0x325c
|
|
#define MC_PVA0XB_EXTRA_SNAP_LEVELS 0x480c
|
|
#define MC_PVA1XB3_EXTRA_SNAP_LEVELS 0x4820
|
|
#define MC_NVD3_EXTRA_SNAP_LEVELS 0xe04
|
|
#define MC_SAX_EXTRA_SNAP_LEVELS 0x2c0
|
|
#define MC_MSEB1_EXTRA_SNAP_LEVELS 0x4908
|
|
#define MC_MSEB_EXTRA_SNAP_LEVELS 0x4904
|
|
#define MC_NVD4_EXTRA_SNAP_LEVELS 0x4918
|
|
#define MC_PVA1XC_EXTRA_SNAP_LEVELS 0x4824
|
|
#define MC_NVD_EXTRA_SNAP_LEVELS 0xa38
|
|
#define MC_PVA1XA2_EXTRA_SNAP_LEVELS 0x4838
|
|
#define MC_PVA0XA2_EXTRA_SNAP_LEVELS 0x4830
|
|
#define MC_NVD5_EXTRA_SNAP_LEVELS 0x491c
|
|
#define MC_DIS2_EXTRA_SNAP_LEVELS 0xa84
|
|
#define MC_VIDEO_PROTECT_BOM 0x648
|
|
#define MC_VIDEO_PROTECT_SIZE_MB 0x64c
|
|
#define MC_VIDEO_PROTECT_BOM_ADR_HI 0x978
|
|
#define MC_VIDEO_PROTECT_REG_CTRL 0x650
|
|
#define MC_ERR_VPR_STATUS 0x654
|
|
#define MC_ERR_VPR_ADR 0x658
|
|
#define MC_VIDEO_PROTECT_VPR_OVERRIDE 0x418
|
|
#define MC_VIDEO_PROTECT_VPR_OVERRIDE1 0x590
|
|
#define MC_VIDEO_PROTECT_VPR_OVERRIDE2 0x594
|
|
#define MC_EMEM_CFG_ACCESS_CTRL 0x664
|
|
#define MC_TZ_SECURITY_CTRL 0x668
|
|
#define MC_TZ_CARVEOUT_CLIENT_ACCESS2 0x1988
|
|
#define MC_TZ_CARVEOUT_CLIENT_ACCESS6 0x1998
|
|
#define MC_TZ_CARVEOUT_CLIENT_ACCESS3 0x198c
|
|
#define MC_TZ_CARVEOUT_CLIENT_ACCESS5 0x1994
|
|
#define MC_TZ_CARVEOUT_CLIENT_ACCESS0 0x1980
|
|
#define MC_TZ_CARVEOUT_CLIENT_ACCESS4 0x1990
|
|
#define MC_TZ_CARVEOUT_CLIENT_ACCESS1 0x1984
|
|
#define MC_TZ_CARVEOUT_CLIENT_ACCESS7 0x199c
|
|
#define MC_EMEM_ARB_OUTSTANDING_REQ_RING3 0x66c
|
|
#define MC_EMEM_ARB_OUTSTANDING_REQ_NISO 0x6b4
|
|
#define MC_EMEM_ARB_RING0_THROTTLE_MASK 0x6bc
|
|
#define MC_EMEM_ARB_NISO_THROTTLE_MASK_3 0x3b00
|
|
#define MC_EMEM_ARB_NISO_THROTTLE_MASK 0x6b8
|
|
#define MC_EMEM_ARB_NISO_THROTTLE_MASK_1 0xb80
|
|
#define MC_EMEM_ARB_NISO_THROTTLE_MASK_2 0x3200
|
|
#define MC_SEC_CARVEOUT_BOM 0x670
|
|
#define MC_SEC_CARVEOUT_SIZE_MB 0x674
|
|
#define MC_SEC_CARVEOUT_ADR_HI 0x9d4
|
|
#define MC_SEC_CARVEOUT_REG_CTRL 0x678
|
|
#define MC_ERR_SEC_STATUS 0x67c
|
|
#define MC_ERR_SEC_ADR 0x680
|
|
#define MC_PC_IDLE_CLOCK_GATE_CONFIG 0x684
|
|
#define MC_STUTTER_CONTROL 0x688
|
|
#define MC_RESERVED_RSV_1 0x958
|
|
#define MC_DVFS_PIPE_SELECT 0x95c
|
|
#define MC_SCEPC_PTSA_MIN 0x790
|
|
#define MC_AUD_PTSA_MIN 0x54c
|
|
#define MC_MLL_MPCORER_PTSA_RATE 0x44c
|
|
#define MC_RING2_PTSA_RATE 0x440
|
|
#define MC_USBD_PTSA_RATE 0x530
|
|
#define MC_PCIE5X_PTSA_MAX 0x3350
|
|
#define MC_ISPPC_PTSA_MIN 0x3a70
|
|
#define MC_JPG_PTSA_RATE 0x584
|
|
#define MC_APB_PTSA_MAX 0x4f0
|
|
#define MC_PVA1XC_PTSA_RATE 0x3924
|
|
#define MC_MIU7_PTSA_MAX 0x4b68
|
|
#define MC_PVA0XB_PTSA_MIN 0x3558
|
|
#define MC_DIS_PTSA_MIN 0x420
|
|
#define MC_NVD2_PTSA_MIN 0x3a1c
|
|
#define MC_SD_PTSA_MAX 0x4d8
|
|
#define MC_MSE_PTSA_RATE 0x4c4
|
|
#define MC_MSE3_PTSA_MIN 0x3134
|
|
#define MC_DLA0XA_PTSA_MIN 0x7e4
|
|
#define MC_ISP_PTSA_RATE 0x4a0
|
|
#define MC_MIU6_PTSA_MAX 0x4b5c
|
|
#define MC_UFSHCPC2_PTSA_RATE 0x3a24
|
|
#define MC_PCIE5X2_PTSA_RATE 0x3a00
|
|
#define MC_PVA0XB2_PTSA_MIN 0x3958
|
|
#define MC_HOST_PTSA_MIN 0x51c
|
|
#define MC_DLA1XA3_PTSA_MIN 0x3370
|
|
#define MC_MLL_MPCORER_PTSA_MAX 0x454
|
|
#define MC_SD_PTSA_MIN 0x4d4
|
|
#define MC_PVA1XB2_PTSA_MAX 0x3974
|
|
#define MC_DLA0XA_PTSA_MAX 0x7e8
|
|
#define MC_RING1_PTSA_RATE 0x47c
|
|
#define MC_NVD2_PTSA_RATE 0x3a18
|
|
#define MC_PVA1XC_PTSA_MAX 0x392c
|
|
#define MC_DLA1FALPC_PTSA_MIN 0x3304
|
|
#define MC_PCIE1XA_PTSA_MIN 0x3510
|
|
#define MC_MIU1_PTSA_MAX 0x3150
|
|
#define MC_MIU0_PTSA_RATE 0x313c
|
|
#define MC_JPG_PTSA_MAX 0x58c
|
|
#define MC_UFSHCPC_PTSA_MAX 0x74c
|
|
#define MC_NVD5_PTSA_MAX 0x4b2c
|
|
#define MC_VICPC2_PTSA_MIN 0x3a10
|
|
#define MC_VICPC_PTSA_MAX 0x55c
|
|
#define MC_DLA1FALPC_PTSA_MAX 0x3308
|
|
#define MC_NVD2_PTSA_MAX 0x3a20
|
|
#define MC_NVD_PTSA_RATE 0x578
|
|
#define MC_MIU1_PTSA_RATE 0x3148
|
|
#define MC_SCEPC_PTSA_RATE 0x78c
|
|
#define MC_MIU3_PTSA_MIN 0x3164
|
|
#define MC_EQOSPC_PTSA_MIN 0x754
|
|
#define MC_PVA1XB3_PTSA_MAX 0x3920
|
|
#define MC_PVA0XA2_PTSA_RATE 0x3948
|
|
#define MC_EQOSPC_PTSA_RATE 0x750
|
|
#define MC_USBX2_PTSA_MAX 0x3a38
|
|
#define MC_VICPC3_PTSA_MIN 0x7b4
|
|
#define MC_MLL_MPCORER_PTSA_MIN 0x450
|
|
#define MC_ISP_PTSA_MAX 0x4a8
|
|
#define MC_PCIE4XA_PTSA_MAX 0x3538
|
|
#define MC_UFSHCPC_PTSA_MIN 0x748
|
|
#define MC_PVA0XC_PTSA_MIN 0x3570
|
|
#define MC_FTOP_PTSA_RATE 0x50c
|
|
#define MC_VICPC2_PTSA_MAX 0x3a14
|
|
#define MC_PCIE4XA_PTSA_RATE 0x3530
|
|
#define MC_DLA0XA2_PTSA_RATE 0x3930
|
|
#define MC_NVD3_PTSA_MIN 0x7c0
|
|
#define MC_PCIE5X2_PTSA_MIN 0x3a04
|
|
#define MC_DLA0FALPC_PTSA_MAX 0x3174
|
|
#define MC_MIU0_PTSA_MIN 0x3140
|
|
#define MC_MIU2_PTSA_MAX 0x315c
|
|
#define MC_ISP2PC_PTSA_MIN 0x4b04
|
|
#define MC_USBX_PTSA_MAX 0x52c
|
|
#define MC_USBD_PTSA_MAX 0x538
|
|
#define MC_MIU5_PTSA_MIN 0x4b4c
|
|
#define MC_USBX_PTSA_RATE 0x524
|
|
#define MC_PCIE0X_PTSA_MAX 0x3314
|
|
#define MC_MSEA_PTSA_MIN 0x3a4c
|
|
#define MC_FTOP_PTSA_MAX 0x514
|
|
#define MC_PVA0XA3_PTSA_MAX 0x3550
|
|
#define MC_ISP2PC_PTSA_MAX 0x4b08
|
|
#define MC_HDAPC_PTSA_MAX 0x630
|
|
#define MC_SD_PTSA_RATE 0x4d0
|
|
#define MC_MSEA_PTSA_MAX 0x3a50
|
|
#define MC_PCIE1X_PTSA_MAX 0x3320
|
|
#define MC_PCIE0X2_PTSA_MAX 0x4b14
|
|
#define MC_PCIE5XA_PTSA_RATE 0x353c
|
|
#define MC_PVA0XA_PTSA_MIN 0x3104
|
|
#define MC_FTOP_PTSA_MIN 0x510
|
|
#define MC_DLA1XA3_PTSA_RATE 0x336c
|
|
#define MC_BPMPPC_PTSA_MAX 0x764
|
|
#define MC_MSE_PTSA_MIN 0x4c8
|
|
#define MC_PCIE0X2_PTSA_MIN 0x4b10
|
|
#define MC_PVA0XB3_PTSA_RATE 0x3560
|
|
#define MC_PVA0XA_PTSA_RATE 0x3100
|
|
#define MC_NVD5_PTSA_MIN 0x4b28
|
|
#define MC_VE_PTSA_RATE 0x434
|
|
#define MC_DLA1XA2_PTSA_RATE 0x393c
|
|
#define MC_AONPC_PTSA_RATE 0x774
|
|
#define MC_DLA0FALPC_PTSA_MIN 0x3170
|
|
#define MC_MIU4_PTSA_RATE 0x4b3c
|
|
#define MC_MIU4_PTSA_MAX 0x4b44
|
|
#define MC_SAX_PTSA_MIN 0x4bc
|
|
#define MC_PVA0XB2_PTSA_MAX 0x395c
|
|
#define MC_PVA0XA3_PTSA_MIN 0x354c
|
|
#define MC_ISP_PTSA_MIN 0x4a4
|
|
#define MC_HOST_PTSA_MAX 0x520
|
|
#define MC_BPMPPC_PTSA_MIN 0x760
|
|
#define MC_PCIE1X_PTSA_RATE 0x3318
|
|
#define MC_NVD6_PTSA_RATE 0x4b30
|
|
#define MC_DLA0XA2_PTSA_MIN 0x3934
|
|
#define MC_ISP2PC_PTSA_RATE 0x4b00
|
|
#define MC_PVA0XB3_PTSA_MIN 0x3564
|
|
#define MC_MSE3_PTSA_MAX 0x3138
|
|
#define MC_NVD5_PTSA_RATE 0x4b24
|
|
#define MC_MSEB1_PTSA_MIN 0x3a64
|
|
#define MC_PVA0XB2_PTSA_RATE 0x3954
|
|
#define MC_EQOSPC_PTSA_MAX 0x758
|
|
#define MC_MSEB_PTSA_RATE 0x3a54
|
|
#define MC_USBX_PTSA_MIN 0x528
|
|
#define MC_PCIE4X_PTSA_RATE 0x333c
|
|
#define MC_USBD_PTSA_MIN 0x534
|
|
#define MC_PCIE5X_PTSA_MIN 0x334c
|
|
#define MC_MIU3_PTSA_MAX 0x3168
|
|
#define MC_DLA1FALPC_PTSA_RATE 0x3300
|
|
#define MC_PVA1XB3_PTSA_RATE 0x3918
|
|
#define MC_DLA1XA3_PTSA_MAX 0x3374
|
|
#define MC_MIU1_PTSA_MIN 0x314c
|
|
#define MC_PCIE5XA_PTSA_MAX 0x3544
|
|
#define MC_DLA0XA3_PTSA_MIN 0x3364
|
|
#define MC_DIS_PTSA_MAX 0x424
|
|
#define MC_RING1_PTSA_MIN 0x480
|
|
#define MC_UFSHCPC2_PTSA_MAX 0x3a2c
|
|
#define MC_VICPC_PTSA_MIN 0x558
|
|
#define MC_MSEB_PTSA_MAX 0x3a5c
|
|
#define MC_PVA0XB_PTSA_MAX 0x355c
|
|
#define MC_USBX2_PTSA_MIN 0x3a34
|
|
#define MC_RING2_PTSA_MAX 0x448
|
|
#define MC_AUD_PTSA_RATE 0x548
|
|
#define MC_PCIE0XA_PTSA_MIN 0x3504
|
|
#define MC_PCIE0XA_PTSA_RATE 0x3500
|
|
#define MC_DLA1XA2_PTSA_MIN 0x3940
|
|
#define MC_PVA1XB2_PTSA_RATE 0x396c
|
|
#define MC_RCEPC_PTSA_MIN 0x311c
|
|
#define MC_PVA1XA_PTSA_MIN 0x3110
|
|
#define MC_DLA0XA3_PTSA_RATE 0x3360
|
|
#define MC_NIC_PTSA_MAX 0x740
|
|
#define MC_NVD_PTSA_MAX 0x580
|
|
#define MC_MIU6_PTSA_MIN 0x4b58
|
|
#define MC_PCIE0X_PTSA_RATE 0x330c
|
|
#define MC_AONPC_PTSA_MAX 0x77c
|
|
#define MC_JPG_PTSA_MIN 0x588
|
|
#define MC_UFSHCPC2_PTSA_MIN 0x3a28
|
|
#define MC_HDAPC_PTSA_MIN 0x62c
|
|
#define MC_DLA1XA_PTSA_MAX 0x7f4
|
|
#define MC_MSE2_PTSA_MAX 0x7d0
|
|
#define MC_NVD4_PTSA_MAX 0x4b20
|
|
#define MC_PVA1XA_PTSA_MAX 0x3114
|
|
#define MC_VE_PTSA_MAX 0x43c
|
|
#define MC_DLA0XA2_PTSA_MAX 0x3938
|
|
#define MC_PVA0XB_PTSA_RATE 0x3554
|
|
#define MC_MSEB1_PTSA_RATE 0x3a60
|
|
#define MC_PVA0XC_PTSA_MAX 0x3574
|
|
#define MC_VICPC_PTSA_RATE 0x554
|
|
#define MC_BPMPPC_PTSA_RATE 0x75c
|
|
#define MC_ISPPC_PTSA_MAX 0x3a74
|
|
#define MC_SCEPC_PTSA_MAX 0x794
|
|
#define MC_DLA0XA_PTSA_RATE 0x7e0
|
|
#define MC_DLA0XA3_PTSA_MAX 0x3368
|
|
#define MC_MIU7_PTSA_RATE 0x4b60
|
|
#define MC_PCIE4X_PTSA_MIN 0x3340
|
|
#define MC_PCIE5X_PTSA_RATE 0x3348
|
|
#define MC_SDM_PTSA_MAX 0x624
|
|
#define MC_VICPC2_PTSA_RATE 0x3a0c
|
|
#define MC_PCIE5XA_PTSA_MIN 0x3540
|
|
#define MC_NVD4_PTSA_RATE 0x4b18
|
|
#define MC_PVA0XA_PTSA_MAX 0x3108
|
|
#define MC_MSE2_PTSA_MIN 0x7cc
|
|
#define MC_USBD2_PTSA_MAX 0x3a44
|
|
#define MC_SAX_PTSA_RATE 0x4b8
|
|
#define MC_APB_PTSA_MIN 0x4ec
|
|
#define MC_ISPPC_PTSA_RATE 0x3a6c
|
|
#define MC_PVA1XA2_PTSA_RATE 0x3960
|
|
#define MC_PCIE5X2_PTSA_MAX 0x3a08
|
|
#define MC_PCIE4XA_PTSA_MIN 0x3534
|
|
#define MC_RCEPC_PTSA_MAX 0x3120
|
|
#define MC_PVA0XA3_PTSA_RATE 0x3548
|
|
#define MC_AONPC_PTSA_MIN 0x778
|
|
#define MC_PCIE0X2_PTSA_RATE 0x4b0c
|
|
#define MC_MSE3_PTSA_RATE 0x3130
|
|
#define MC_RCEPC_PTSA_RATE 0x3118
|
|
#define MC_RING1_PTSA_MAX 0x484
|
|
#define MC_HDAPC_PTSA_RATE 0x628
|
|
#define MC_MIU0_PTSA_MAX 0x3144
|
|
#define MC_PVA1XB2_PTSA_MIN 0x3970
|
|
#define MC_VICPC3_PTSA_RATE 0x7b0
|
|
#define MC_AUD_PTSA_MAX 0x550
|
|
#define MC_MIU2_PTSA_MIN 0x3158
|
|
#define MC_NVD3_PTSA_MAX 0x7c4
|
|
#define MC_MIU6_PTSA_RATE 0x4b54
|
|
#define MC_NVD_PTSA_MIN 0x57c
|
|
#define MC_PVA0XA2_PTSA_MIN 0x394c
|
|
#define MC_VICPC3_PTSA_MAX 0x7b8
|
|
#define MC_PVA1XA2_PTSA_MIN 0x3964
|
|
#define MC_PVA0XB3_PTSA_MAX 0x3568
|
|
#define MC_PVA1XA3_PTSA_RATE 0x3900
|
|
#define MC_PCIE0X_PTSA_MIN 0x3310
|
|
#define MC_PCIE1XA_PTSA_RATE 0x350c
|
|
#define MC_DIS_PTSA_RATE 0x41c
|
|
#define MC_USBX2_PTSA_RATE 0x3a30
|
|
#define MC_DLA1XA_PTSA_MIN 0x7f0
|
|
#define MC_PVA1XA3_PTSA_MAX 0x3908
|
|
#define MC_PVA1XB_PTSA_RATE 0x390c
|
|
#define MC_DLA1XA2_PTSA_MAX 0x3944
|
|
#define MC_MSEA_PTSA_RATE 0x3a48
|
|
#define MC_MIU2_PTSA_RATE 0x3154
|
|
#define MC_NVD6_PTSA_MAX 0x4b38
|
|
#define MC_PCIE1XA_PTSA_MAX 0x3514
|
|
#define MC_MIU3_PTSA_RATE 0x3160
|
|
#define MC_MIU5_PTSA_MAX 0x4b50
|
|
#define MC_SDM_PTSA_RATE 0x61c
|
|
#define MC_SDM_PTSA_MIN 0x620
|
|
#define MC_APB_PTSA_RATE 0x4e8
|
|
#define MC_RING2_PTSA_MIN 0x444
|
|
#define MC_UFSHCPC_PTSA_RATE 0x744
|
|
#define MC_PVA0XC_PTSA_RATE 0x356c
|
|
#define MC_MSE2_PTSA_RATE 0x7c8
|
|
#define MC_PCIE0XA_PTSA_MAX 0x3508
|
|
#define MC_MSEB_PTSA_MIN 0x3a58
|
|
#define MC_PVA1XB_PTSA_MAX 0x3914
|
|
#define MC_HOST_PTSA_RATE 0x518
|
|
#define MC_NVD3_PTSA_RATE 0x7bc
|
|
#define MC_NVD6_PTSA_MIN 0x4b34
|
|
#define MC_MIU5_PTSA_RATE 0x4b48
|
|
#define MC_PVA1XB_PTSA_MIN 0x3910
|
|
#define MC_PVA1XA_PTSA_RATE 0x310c
|
|
#define MC_MIU4_PTSA_MIN 0x4b40
|
|
#define MC_NIC_PTSA_RATE 0x738
|
|
#define MC_PVA1XB3_PTSA_MIN 0x391c
|
|
#define MC_NVD4_PTSA_MIN 0x4b1c
|
|
#define MC_SAX_PTSA_MAX 0x4c0
|
|
#define MC_MIU7_PTSA_MIN 0x4b64
|
|
#define MC_PVA1XA3_PTSA_MIN 0x3904
|
|
#define MC_VE_PTSA_MIN 0x438
|
|
#define MC_USBD2_PTSA_RATE 0x3a3c
|
|
#define MC_DLA1XA_PTSA_RATE 0x7ec
|
|
#define MC_PVA0XA2_PTSA_MAX 0x3950
|
|
#define MC_DLA0FALPC_PTSA_RATE 0x316c
|
|
#define MC_MSE_PTSA_MAX 0x4cc
|
|
#define MC_PCIE4X_PTSA_MAX 0x3344
|
|
#define MC_MSEB1_PTSA_MAX 0x3a68
|
|
#define MC_USBD2_PTSA_MIN 0x3a40
|
|
#define MC_PVA1XA2_PTSA_MAX 0x3968
|
|
#define MC_PCIE1X_PTSA_MIN 0x331c
|
|
#define MC_NIC_PTSA_MIN 0x73c
|
|
#define MC_PVA1XC_PTSA_MIN 0x3928
|
|
#define MC_PTSA_GRANT_DECREMENT 0x960
|
|
#define MC_LATENCY_ALLOWANCE_AON_0 0x714
|
|
#define MC_LATENCY_ALLOWANCE_NVENC_1 0x1050
|
|
#define MC_LATENCY_ALLOWANCE_BPMP_0 0x70c
|
|
#define MC_LATENCY_ALLOWANCE_MIU0_0 0x1054
|
|
#define MC_LATENCY_ALLOWANCE_NVDEC_1 0x72c
|
|
#define MC_LATENCY_ALLOWANCE_XUSB_1 0x380
|
|
#define MC_LATENCY_ALLOWANCE_NVENC_2 0x1a28
|
|
#define MC_LATENCY_ALLOWANCE_SE_0 0x3e0
|
|
#define MC_LATENCY_ALLOWANCE_PCIE2_0 0x1a04
|
|
#define MC_LATENCY_ALLOWANCE_PCIE1_0 0x1a00
|
|
#define MC_LATENCY_ALLOWANCE_DLA1_0 0x1028
|
|
#define MC_LATENCY_ALLOWANCE_APEDMA_0 0x724
|
|
#define MC_LATENCY_ALLOWANCE_NVDEC_0 0x3d8
|
|
#define MC_LATENCY_ALLOWANCE_ISP3_0 0x1a14
|
|
#define MC_LATENCY_ALLOWANCE_MIU2_0 0x105c
|
|
#define MC_LATENCY_ALLOWANCE_MIU5_0 0x1a38
|
|
#define MC_LATENCY_ALLOWANCE_DLA0_2 0x1a18
|
|
#define MC_LATENCY_ALLOWANCE_PCIE0_0 0x1064
|
|
#define MC_LATENCY_ALLOWANCE_PVA0_2 0x1038
|
|
#define MC_LATENCY_ALLOWANCE_MIU3_0 0x1060
|
|
#define MC_LATENCY_ALLOWANCE_MIU1_0 0x1058
|
|
#define MC_LATENCY_ALLOWANCE_DLA1_1 0x102c
|
|
#define MC_LATENCY_ALLOWANCE_PVA1_0 0x103c
|
|
#define MC_LATENCY_ALLOWANCE_SDMMC_0 0x3c0
|
|
#define MC_LATENCY_ALLOWANCE_DLA0_1 0x1024
|
|
#define MC_LATENCY_ALLOWANCE_DLA0_0 0x1020
|
|
#define MC_LATENCY_ALLOWANCE_NVJPG_0 0x3e4
|
|
#define MC_LATENCY_ALLOWANCE_MPCORE_0 0x320
|
|
#define MC_LATENCY_ALLOWANCE_VI2_0 0x398
|
|
#define MC_LATENCY_ALLOWANCE_MIU7_0 0x1a40
|
|
#define MC_LATENCY_ALLOWANCE_SCEDMA_0 0x720
|
|
#define MC_LATENCY_ALLOWANCE_PVA1_1 0x1040
|
|
#define MC_LATENCY_ALLOWANCE_SATA_0 0x350
|
|
#define MC_LATENCY_ALLOWANCE_AONDMA_0 0x718
|
|
#define MC_LATENCY_ALLOWANCE_HC_0 0x310
|
|
#define MC_LATENCY_ALLOWANCE_UFSHC_0 0x704
|
|
#define MC_LATENCY_ALLOWANCE_NVDEC_2 0x1a30
|
|
#define MC_LATENCY_ALLOWANCE_VIC_1 0x728
|
|
#define MC_LATENCY_ALLOWANCE_SDMMCAB_0 0x3c4
|
|
#define MC_LATENCY_ALLOWANCE_RCEDMA_0 0x104c
|
|
#define MC_LATENCY_ALLOWANCE_HDA_0 0x318
|
|
#define MC_LATENCY_ALLOWANCE_BPMPDMA_0 0x710
|
|
#define MC_LATENCY_ALLOWANCE_PCIE3_0 0x1a08
|
|
#define MC_LATENCY_ALLOWANCE_AXIAP_0 0x3a0
|
|
#define MC_LATENCY_ALLOWANCE_SDMMCA_0 0x3b8
|
|
#define MC_LATENCY_ALLOWANCE_PVA0_3 0x1a1c
|
|
#define MC_LATENCY_ALLOWANCE_ISP2_0 0x370
|
|
#define MC_LATENCY_ALLOWANCE_NVDISPLAY_0 0x708
|
|
#define MC_LATENCY_ALLOWANCE_ISP2_1 0x374
|
|
#define MC_LATENCY_ALLOWANCE_PVA1_3 0x1a20
|
|
#define MC_LATENCY_ALLOWANCE_VIC_0 0x394
|
|
#define MC_LATENCY_ALLOWANCE_PCIE4_0 0x1a0c
|
|
#define MC_LATENCY_ALLOWANCE_PVA1_2 0x1044
|
|
#define MC_LATENCY_ALLOWANCE_EQOS_0 0x700
|
|
#define MC_LATENCY_ALLOWANCE_TSEC_0 0x390
|
|
#define MC_LATENCY_ALLOWANCE_VIFAL_0 0x101c
|
|
#define MC_LATENCY_ALLOWANCE_PVA0_1 0x1034
|
|
#define MC_LATENCY_ALLOWANCE_XUSB_0 0x37c
|
|
#define MC_LATENCY_ALLOWANCE_MIU4_0 0x1a34
|
|
#define MC_LATENCY_ALLOWANCE_TSECB_0 0x3f0
|
|
#define MC_LATENCY_ALLOWANCE_SCE_0 0x71c
|
|
#define MC_LATENCY_ALLOWANCE_APE_0 0x3dc
|
|
#define MC_LATENCY_ALLOWANCE_RCE_0 0x1048
|
|
#define MC_LATENCY_ALLOWANCE_PVA0_0 0x1030
|
|
#define MC_LATENCY_ALLOWANCE_PTC_0 0x34c
|
|
#define MC_LATENCY_ALLOWANCE_ETR_0 0x3ec
|
|
#define MC_LATENCY_ALLOWANCE_PCIE5_0 0x1a10
|
|
#define MC_LATENCY_ALLOWANCE_AXIS_0 0x3f8
|
|
#define MC_LATENCY_ALLOWANCE_NVENC_0 0x328
|
|
#define MC_LATENCY_ALLOWANCE_MIU6_0 0x1a3c
|
|
#define MC_LATENCY_ALLOWANCE_PCIE5_1 0x1a24
|
|
#define MC_EMEM_ARB_OVERRIDE_1 0x968
|
|
#define MC_VIDEO_PROTECT_GPU_OVERRIDE_0 0x984
|
|
#define MC_VIDEO_PROTECT_GPU_OVERRIDE_1 0x988
|
|
#define MC_EMEM_ARB_STATS_0 0x990
|
|
#define MC_EMEM_ARB_STATS_1 0x994
|
|
#define MC_MTS_CARVEOUT_BOM 0x9a0
|
|
#define MC_MTS_CARVEOUT_SIZE_MB 0x9a4
|
|
#define MC_MTS_CARVEOUT_ADR_HI 0x9a8
|
|
#define MC_MTS_CARVEOUT_REG_CTRL 0x9ac
|
|
#define MC_ERR_MTS_STATUS 0x9b0
|
|
#define MC_ERR_MTS_ADR 0x9b4
|
|
#define MC_MTS_CARVEOUT_CLIENT_ACCESS6 0x1918
|
|
#define MC_MTS_CARVEOUT_CLIENT_ACCESS4 0x1910
|
|
#define MC_MTS_CARVEOUT_CLIENT_ACCESS1 0x1904
|
|
#define MC_MTS_CARVEOUT_CLIENT_ACCESS5 0x1914
|
|
#define MC_MTS_CARVEOUT_CLIENT_ACCESS0 0x1900
|
|
#define MC_MTS_CARVEOUT_CLIENT_ACCESS7 0x191c
|
|
#define MC_MTS_CARVEOUT_CLIENT_ACCESS3 0x190c
|
|
#define MC_MTS_CARVEOUT_CLIENT_ACCESS2 0x1908
|
|
#define MC_ERR_ROUTE_SANITY_STATUS 0x9c0
|
|
#define MC_ERR_ROUTE_SANITY_ADR 0x9c4
|
|
#define MC_IGPU_ACCESSIBLE_CARVEOUT_REG_CTRL 0x9c8
|
|
#define MC_REMOTE_DEV_ACCESSIBLE_CARVEOUT_REG_CTRL 0x9cc
|
|
#define MC_IGPU_WPR_ACCESS_CTRL 0x9d8
|
|
#define MC_IGPU_ACCESSIBLE_CARVEOUT1_BOM 0x560
|
|
#define MC_IGPU_ACCESSIBLE_CARVEOUT1_SIZE 0x564
|
|
#define MC_IGPU_ACCESSIBLE_CARVEOUT2_BOM 0x568
|
|
#define MC_IGPU_ACCESSIBLE_CARVEOUT2_SIZE 0x56c
|
|
#define MC_REMOTE_DEV_ACCESSIBLE_CARVEOUT1_BOM 0x5a0
|
|
#define MC_REMOTE_DEV_ACCESSIBLE_CARVEOUT1_SIZE 0x5a4
|
|
#define MC_REMOTE_DEV_ACCESSIBLE_CARVEOUT2_BOM 0x5a8
|
|
#define MC_REMOTE_DEV_ACCESSIBLE_CARVEOUT2_SIZE 0x5ac
|
|
#define MC_ECC_REGION0_SIZE 0x2b0c
|
|
#define MC_ECC_REGION0_CFG0 0x2b00
|
|
#define MC_ECC_REGION3_BOM 0x2b34
|
|
#define MC_ECC_REGION2_BOM 0x2b24
|
|
#define MC_ECC_REGION1_SIZE 0x2b1c
|
|
#define MC_ECC_REGION1_BOM 0x2b14
|
|
#define MC_ECC_REGION2_CFG0 0x2b20
|
|
#define MC_ECC_REGION3_BOM_HI 0x2b38
|
|
#define MC_ECC_REGION1_BOM_HI 0x2b18
|
|
#define MC_ECC_REGION1_CFG0 0x2b10
|
|
#define MC_ECC_REGION0_BOM_HI 0x2b08
|
|
#define MC_ECC_REGION2_SIZE 0x2b2c
|
|
#define MC_ECC_REGION3_CFG0 0x2b30
|
|
#define MC_ECC_REGION2_BOM_HI 0x2b28
|
|
#define MC_ECC_REGION0_BOM 0x2b04
|
|
#define MC_ECC_REGION3_SIZE 0x2b3c
|
|
#define MC_ERR_GENERALIZED_CARVEOUT_STATUS_1 0xbfc
|
|
#define MC_ERR_GENERALIZED_CARVEOUT_STATUS 0xc00
|
|
#define MC_ERR_GENERALIZED_CARVEOUT_ADR 0xc04
|
|
#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS2 0xd78
|
|
#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS6 0xc48
|
|
#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS5 0xc44
|
|
#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS7 0xca4
|
|
#define MC_SECURITY_CARVEOUT4_CFG0 0xcf8
|
|
#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS6 0xd90
|
|
#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS2 0xd10
|
|
#define MC_SECURITY_CARVEOUT4_SIZE_128KB 0xd04
|
|
#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS4 0xc28
|
|
#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS1 0xc34
|
|
#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS4 0xc90
|
|
#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS0 0xd20
|
|
#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS1 0xd74
|
|
#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS5 0xc2c
|
|
#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS0 0xc30
|
|
#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS7 0xd8c
|
|
#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS4 0xd80
|
|
#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS5 0xccc
|
|
#define MC_SECURITY_CARVEOUT3_SIZE_128KB 0xcb4
|
|
#define MC_SECURITY_CARVEOUT2_CFG0 0xc58
|
|
#define MC_SECURITY_CARVEOUT1_CFG0 0xc08
|
|
#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS2 0xc88
|
|
#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS0 0xc68
|
|
#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS7 0xc4c
|
|
#define MC_SECURITY_CARVEOUT3_BOM 0xcac
|
|
#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS2 0xc70
|
|
#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS5 0xd84
|
|
#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS6 0xd40
|
|
#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS3 0xd7c
|
|
#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS0 0xc80
|
|
#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS4 0xd18
|
|
#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS6 0xcf0
|
|
#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS6 0xce8
|
|
#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS5 0xd1c
|
|
#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS1 0xcbc
|
|
#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS3 0xc3c
|
|
#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS2 0xc38
|
|
#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS2 0xcc0
|
|
#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS2 0xd60
|
|
#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS6 0xca0
|
|
#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS7 0xc54
|
|
#define MC_SECURITY_CARVEOUT3_CFG0 0xca8
|
|
#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS0 0xcb8
|
|
#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS3 0xc8c
|
|
#define MC_SECURITY_CARVEOUT2_SIZE_128KB 0xc64
|
|
#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS7 0xcec
|
|
#define MC_SECURITY_CARVEOUT5_BOM_HI 0xd50
|
|
#define MC_SECURITY_CARVEOUT1_SIZE_128KB 0xc14
|
|
#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS3 0xd14
|
|
#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS7 0xd94
|
|
#define MC_SECURITY_CARVEOUT1_BOM 0xc0c
|
|
#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS7 0xd3c
|
|
#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS4 0xd30
|
|
#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS7 0xd44
|
|
#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS4 0xd68
|
|
#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS6 0xd38
|
|
#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS0 0xd58
|
|
#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS4 0xcc8
|
|
#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS5 0xce4
|
|
#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS2 0xd28
|
|
#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS3 0xcc4
|
|
#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS4 0xc78
|
|
#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS7 0xc9c
|
|
#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS7 0xcf4
|
|
#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS1 0xc1c
|
|
#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS6 0xd88
|
|
#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS0 0xc18
|
|
#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS1 0xd5c
|
|
#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS3 0xd2c
|
|
#define MC_SECURITY_CARVEOUT3_BOM_HI 0xcb0
|
|
#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS3 0xcdc
|
|
#define MC_SECURITY_CARVEOUT2_BOM_HI 0xc60
|
|
#define MC_SECURITY_CARVEOUT4_BOM_HI 0xd00
|
|
#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS3 0xd64
|
|
#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS4 0xce0
|
|
#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS1 0xc84
|
|
#define MC_SECURITY_CARVEOUT5_SIZE_128KB 0xd54
|
|
#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS5 0xc94
|
|
#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS1 0xd24
|
|
#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS2 0xcd8
|
|
#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS1 0xd0c
|
|
#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS5 0xd6c
|
|
#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS3 0xc74
|
|
#define MC_SECURITY_CARVEOUT5_CFG0 0xd48
|
|
#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS0 0xcd0
|
|
#define MC_SECURITY_CARVEOUT4_BOM 0xcfc
|
|
#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS6 0xc50
|
|
#define MC_SECURITY_CARVEOUT2_BOM 0xc5c
|
|
#define MC_SECURITY_CARVEOUT5_BOM 0xd4c
|
|
#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS3 0xc24
|
|
#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS0 0xd70
|
|
#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS5 0xc7c
|
|
#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS1 0xcd4
|
|
#define MC_SECURITY_CARVEOUT1_BOM_HI 0xc10
|
|
#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS5 0xd34
|
|
#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS6 0xc98
|
|
#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS2 0xc20
|
|
#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS4 0xc40
|
|
#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0 0xd08
|
|
#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS1 0xc6c
|
|
#define MC_SECURITY_CARVEOUT13_CLIENT_FORCE_INTERNAL_ACCESS1 0x225c
|
|
#define MC_SECURITY_CARVEOUT11_CLIENT_FORCE_INTERNAL_ACCESS3 0x21c4
|
|
#define MC_SECURITY_CARVEOUT22_CLIENT_FORCE_INTERNAL_ACCESS1 0x252c
|
|
#define MC_SECURITY_CARVEOUT12_CFG0 0x21e0
|
|
#define MC_SECURITY_CARVEOUT27_CLIENT_ACCESS7 0x26d4
|
|
#define MC_SECURITY_CARVEOUT7_CLIENT_FORCE_INTERNAL_ACCESS5 0x208c
|
|
#define MC_SECURITY_CARVEOUT26_CLIENT_ACCESS3 0x265c
|
|
#define MC_SECURITY_CARVEOUT9_BOM_HI 0x20f8
|
|
#define MC_SECURITY_CARVEOUT20_CLIENT_ACCESS6 0x24a0
|
|
#define MC_SECURITY_CARVEOUT7_CLIENT_ACCESS6 0x2090
|
|
#define MC_SECURITY_CARVEOUT29_CLIENT_ACCESS6 0x2770
|
|
#define MC_SECURITY_CARVEOUT10_CLIENT_FORCE_INTERNAL_ACCESS2 0x2170
|
|
#define MC_SECURITY_CARVEOUT12_CLIENT_FORCE_INTERNAL_ACCESS0 0x2208
|
|
#define MC_SECURITY_CARVEOUT26_CLIENT_FORCE_INTERNAL_ACCESS4 0x2678
|
|
#define MC_SECURITY_CARVEOUT20_CLIENT_FORCE_INTERNAL_ACCESS0 0x2488
|
|
#define MC_SECURITY_CARVEOUT21_CLIENT_FORCE_INTERNAL_ACCESS5 0x24ec
|
|
#define MC_SECURITY_CARVEOUT10_CLIENT_ACCESS7 0x2184
|
|
#define MC_SECURITY_CARVEOUT15_CFG0 0x22d0
|
|
#define MC_SECURITY_CARVEOUT18_CLIENT_ACCESS1 0x23d4
|
|
#define MC_SECURITY_CARVEOUT7_SIZE_128KB 0x205c
|
|
#define MC_SECURITY_CARVEOUT27_CLIENT_FORCE_INTERNAL_ACCESS7 0x26dc
|
|
#define MC_SECURITY_CARVEOUT20_CLIENT_FORCE_INTERNAL_ACCESS2 0x2490
|
|
#define MC_SECURITY_CARVEOUT17_CLIENT_ACCESS0 0x2380
|
|
#define MC_SECURITY_CARVEOUT17_CLIENT_FORCE_INTERNAL_ACCESS5 0x23ac
|
|
#define MC_SECURITY_CARVEOUT8_CLIENT_ACCESS4 0x20c0
|
|
#define MC_SECURITY_CARVEOUT15_CLIENT_ACCESS2 0x22e8
|
|
#define MC_SECURITY_CARVEOUT16_CFG0 0x2320
|
|
#define MC_SECURITY_CARVEOUT9_BOM 0x20f4
|
|
#define MC_SECURITY_CARVEOUT14_CLIENT_FORCE_INTERNAL_ACCESS3 0x22b4
|
|
#define MC_SECURITY_CARVEOUT13_CLIENT_ACCESS5 0x2254
|
|
#define MC_SECURITY_CARVEOUT7_CLIENT_FORCE_INTERNAL_ACCESS0 0x2078
|
|
#define MC_SECURITY_CARVEOUT24_CLIENT_FORCE_INTERNAL_ACCESS1 0x25cc
|
|
#define MC_SECURITY_CARVEOUT22_BOM_HI 0x2508
|
|
#define MC_SECURITY_CARVEOUT16_CLIENT_FORCE_INTERNAL_ACCESS3 0x2354
|
|
#define MC_SECURITY_CARVEOUT20_CLIENT_ACCESS5 0x2484
|
|
#define MC_SECURITY_CARVEOUT18_CLIENT_ACCESS3 0x23dc
|
|
#define MC_SECURITY_CARVEOUT12_CLIENT_FORCE_INTERNAL_ACCESS2 0x2210
|
|
#define MC_SECURITY_CARVEOUT19_CLIENT_FORCE_INTERNAL_ACCESS0 0x2438
|
|
#define MC_SECURITY_CARVEOUT28_CLIENT_ACCESS6 0x2720
|
|
#define MC_SECURITY_CARVEOUT14_CLIENT_ACCESS0 0x2290
|
|
#define MC_SECURITY_CARVEOUT9_CLIENT_FORCE_INTERNAL_ACCESS6 0x2138
|
|
#define MC_SECURITY_CARVEOUT8_SIZE_128KB 0x20ac
|
|
#define MC_SECURITY_CARVEOUT25_CLIENT_ACCESS3 0x260c
|
|
#define MC_SECURITY_CARVEOUT24_CLIENT_ACCESS1 0x25b4
|
|
#define MC_SECURITY_CARVEOUT22_CLIENT_FORCE_INTERNAL_ACCESS3 0x2534
|
|
#define MC_SECURITY_CARVEOUT26_CLIENT_FORCE_INTERNAL_ACCESS0 0x2668
|
|
#define MC_SECURITY_CARVEOUT30_CLIENT_ACCESS2 0x2798
|
|
#define MC_SECURITY_CARVEOUT7_CLIENT_ACCESS3 0x206c
|
|
#define MC_SECURITY_CARVEOUT27_CLIENT_ACCESS2 0x26a8
|
|
#define MC_SECURITY_CARVEOUT27_CLIENT_FORCE_INTERNAL_ACCESS3 0x26c4
|
|
#define MC_SECURITY_CARVEOUT19_CLIENT_ACCESS4 0x2430
|
|
#define MC_SECURITY_CARVEOUT10_CLIENT_FORCE_INTERNAL_ACCESS7 0x218c
|
|
#define MC_SECURITY_CARVEOUT6_CLIENT_ACCESS4 0x2020
|
|
#define MC_SECURITY_CARVEOUT17_CLIENT_ACCESS5 0x2394
|
|
#define MC_SECURITY_CARVEOUT10_CLIENT_ACCESS6 0x2180
|
|
#define MC_SECURITY_CARVEOUT8_CLIENT_FORCE_INTERNAL_ACCESS5 0x20dc
|
|
#define MC_SECURITY_CARVEOUT18_CLIENT_FORCE_INTERNAL_ACCESS5 0x23fc
|
|
#define MC_SECURITY_CARVEOUT24_CLIENT_FORCE_INTERNAL_ACCESS6 0x25e8
|
|
#define MC_SECURITY_CARVEOUT11_CLIENT_ACCESS3 0x21ac
|
|
#define MC_SECURITY_CARVEOUT7_BOM 0x2054
|
|
#define MC_SECURITY_CARVEOUT28_CLIENT_FORCE_INTERNAL_ACCESS3 0x2714
|
|
#define MC_SECURITY_CARVEOUT7_CLIENT_ACCESS0 0x2060
|
|
#define MC_SECURITY_CARVEOUT25_CLIENT_FORCE_INTERNAL_ACCESS3 0x2624
|
|
#define MC_SECURITY_CARVEOUT8_CLIENT_FORCE_INTERNAL_ACCESS0 0x20c8
|
|
#define MC_SECURITY_CARVEOUT21_CLIENT_ACCESS3 0x24cc
|
|
#define MC_SECURITY_CARVEOUT15_CLIENT_FORCE_INTERNAL_ACCESS2 0x2300
|
|
#define MC_SECURITY_CARVEOUT17_CFG0 0x2370
|
|
#define MC_SECURITY_CARVEOUT14_CLIENT_ACCESS5 0x22a4
|
|
#define MC_SECURITY_CARVEOUT7_CLIENT_FORCE_INTERNAL_ACCESS4 0x2088
|
|
#define MC_SECURITY_CARVEOUT29_SIZE_128KB 0x273c
|
|
#define MC_SECURITY_CARVEOUT29_CLIENT_ACCESS3 0x274c
|
|
#define MC_SECURITY_CARVEOUT26_CLIENT_FORCE_INTERNAL_ACCESS3 0x2674
|
|
#define MC_SECURITY_CARVEOUT27_CFG0 0x2690
|
|
#define MC_SECURITY_CARVEOUT25_CLIENT_FORCE_INTERNAL_ACCESS7 0x263c
|
|
#define MC_SECURITY_CARVEOUT16_SIZE_128KB 0x232c
|
|
#define MC_SECURITY_CARVEOUT31_CLIENT_ACCESS6 0x2810
|
|
#define MC_SECURITY_CARVEOUT7_CLIENT_FORCE_INTERNAL_ACCESS1 0x207c
|
|
#define MC_SECURITY_CARVEOUT30_CLIENT_FORCE_INTERNAL_ACCESS7 0x27cc
|
|
#define MC_SECURITY_CARVEOUT15_CLIENT_ACCESS3 0x22ec
|
|
#define MC_SECURITY_CARVEOUT25_CLIENT_FORCE_INTERNAL_ACCESS1 0x261c
|
|
#define MC_SECURITY_CARVEOUT24_CLIENT_ACCESS0 0x25b0
|
|
#define MC_SECURITY_CARVEOUT18_BOM 0x23c4
|
|
#define MC_SECURITY_CARVEOUT22_CLIENT_FORCE_INTERNAL_ACCESS0 0x2528
|
|
#define MC_SECURITY_CARVEOUT20_CLIENT_FORCE_INTERNAL_ACCESS1 0x248c
|
|
#define MC_SECURITY_CARVEOUT17_CLIENT_FORCE_INTERNAL_ACCESS6 0x23b8
|
|
#define MC_SECURITY_CARVEOUT22_CLIENT_ACCESS0 0x2510
|
|
#define MC_SECURITY_CARVEOUT12_CLIENT_FORCE_INTERNAL_ACCESS3 0x2214
|
|
#define MC_SECURITY_CARVEOUT11_CLIENT_ACCESS2 0x21a8
|
|
#define MC_SECURITY_CARVEOUT25_CLIENT_ACCESS1 0x2604
|
|
#define MC_SECURITY_CARVEOUT16_CLIENT_ACCESS4 0x2340
|
|
#define MC_SECURITY_CARVEOUT13_CLIENT_ACCESS7 0x2274
|
|
#define MC_SECURITY_CARVEOUT29_CFG0 0x2730
|
|
#define MC_SECURITY_CARVEOUT30_CLIENT_FORCE_INTERNAL_ACCESS0 0x27a8
|
|
#define MC_SECURITY_CARVEOUT6_CLIENT_FORCE_INTERNAL_ACCESS6 0x2048
|
|
#define MC_SECURITY_CARVEOUT14_CLIENT_FORCE_INTERNAL_ACCESS4 0x22b8
|
|
#define MC_SECURITY_CARVEOUT12_CLIENT_ACCESS3 0x21fc
|
|
#define MC_SECURITY_CARVEOUT11_CFG0 0x2190
|
|
#define MC_SECURITY_CARVEOUT29_CLIENT_FORCE_INTERNAL_ACCESS3 0x2764
|
|
#define MC_SECURITY_CARVEOUT8_CFG0 0x20a0
|
|
#define MC_SECURITY_CARVEOUT23_CLIENT_FORCE_INTERNAL_ACCESS2 0x2580
|
|
#define MC_SECURITY_CARVEOUT10_CLIENT_ACCESS5 0x2164
|
|
#define MC_SECURITY_CARVEOUT20_CLIENT_ACCESS4 0x2480
|
|
#define MC_SECURITY_CARVEOUT22_CLIENT_FORCE_INTERNAL_ACCESS4 0x2538
|
|
#define MC_SECURITY_CARVEOUT19_CLIENT_ACCESS5 0x2434
|
|
#define MC_SECURITY_CARVEOUT16_CLIENT_FORCE_INTERNAL_ACCESS2 0x2350
|
|
#define MC_SECURITY_CARVEOUT21_CLIENT_FORCE_INTERNAL_ACCESS4 0x24e8
|
|
#define MC_SECURITY_CARVEOUT11_CLIENT_ACCESS5 0x21b4
|
|
#define MC_SECURITY_CARVEOUT18_CLIENT_ACCESS4 0x23e0
|
|
#define MC_SECURITY_CARVEOUT16_CLIENT_ACCESS1 0x2334
|
|
#define MC_SECURITY_CARVEOUT28_BOM 0x26e4
|
|
#define MC_SECURITY_CARVEOUT25_CLIENT_ACCESS6 0x2630
|
|
#define MC_SECURITY_CARVEOUT8_CLIENT_ACCESS1 0x20b4
|
|
#define MC_SECURITY_CARVEOUT15_BOM 0x22d4
|
|
#define MC_SECURITY_CARVEOUT6_BOM 0x2004
|
|
#define MC_SECURITY_CARVEOUT27_CLIENT_ACCESS3 0x26ac
|
|
#define MC_SECURITY_CARVEOUT27_CLIENT_FORCE_INTERNAL_ACCESS2 0x26c0
|
|
#define MC_SECURITY_CARVEOUT6_CLIENT_ACCESS3 0x201c
|
|
#define MC_SECURITY_CARVEOUT10_BOM 0x2144
|
|
#define MC_SECURITY_CARVEOUT28_CLIENT_FORCE_INTERNAL_ACCESS2 0x2710
|
|
#define MC_SECURITY_CARVEOUT29_BOM_HI 0x2738
|
|
#define MC_SECURITY_CARVEOUT10_CLIENT_ACCESS0 0x2150
|
|
#define MC_SECURITY_CARVEOUT28_CLIENT_ACCESS7 0x2724
|
|
#define MC_SECURITY_CARVEOUT23_CLIENT_ACCESS7 0x2594
|
|
#define MC_SECURITY_CARVEOUT7_BOM_HI 0x2058
|
|
#define MC_SECURITY_CARVEOUT31_CLIENT_FORCE_INTERNAL_ACCESS6 0x2818
|
|
#define MC_SECURITY_CARVEOUT9_CLIENT_ACCESS4 0x2110
|
|
#define MC_SECURITY_CARVEOUT22_CLIENT_ACCESS5 0x2524
|
|
#define MC_SECURITY_CARVEOUT19_SIZE_128KB 0x241c
|
|
#define MC_SECURITY_CARVEOUT6_CLIENT_ACCESS6 0x2040
|
|
#define MC_SECURITY_CARVEOUT18_SIZE_128KB 0x23cc
|
|
#define MC_SECURITY_CARVEOUT10_CFG0 0x2140
|
|
#define MC_SECURITY_CARVEOUT11_CLIENT_FORCE_INTERNAL_ACCESS1 0x21bc
|
|
#define MC_SECURITY_CARVEOUT10_CLIENT_FORCE_INTERNAL_ACCESS0 0x2168
|
|
#define MC_SECURITY_CARVEOUT15_CLIENT_FORCE_INTERNAL_ACCESS4 0x2308
|
|
#define MC_SECURITY_CARVEOUT25_CLIENT_FORCE_INTERNAL_ACCESS6 0x2638
|
|
#define MC_SECURITY_CARVEOUT6_BOM_HI 0x2008
|
|
#define MC_SECURITY_CARVEOUT15_SIZE_128KB 0x22dc
|
|
#define MC_SECURITY_CARVEOUT26_CLIENT_FORCE_INTERNAL_ACCESS2 0x2670
|
|
#define MC_SECURITY_CARVEOUT21_CLIENT_ACCESS4 0x24d0
|
|
#define MC_SECURITY_CARVEOUT21_CLIENT_ACCESS2 0x24c8
|
|
#define MC_SECURITY_CARVEOUT20_CLIENT_ACCESS2 0x2478
|
|
#define MC_SECURITY_CARVEOUT19_CFG0 0x2410
|
|
#define MC_SECURITY_CARVEOUT6_CLIENT_ACCESS1 0x2014
|
|
#define MC_SECURITY_CARVEOUT24_CLIENT_ACCESS3 0x25bc
|
|
#define MC_SECURITY_CARVEOUT12_CLIENT_ACCESS1 0x21f4
|
|
#define MC_SECURITY_CARVEOUT6_CLIENT_ACCESS2 0x2018
|
|
#define MC_SECURITY_CARVEOUT20_SIZE_128KB 0x246c
|
|
#define MC_SECURITY_CARVEOUT10_CLIENT_FORCE_INTERNAL_ACCESS5 0x217c
|
|
#define MC_SECURITY_CARVEOUT26_CLIENT_ACCESS1 0x2654
|
|
#define MC_SECURITY_CARVEOUT29_CLIENT_ACCESS0 0x2740
|
|
#define MC_SECURITY_CARVEOUT14_CLIENT_FORCE_INTERNAL_ACCESS1 0x22ac
|
|
#define MC_SECURITY_CARVEOUT18_CLIENT_FORCE_INTERNAL_ACCESS3 0x23f4
|
|
#define MC_SECURITY_CARVEOUT27_BOM 0x2694
|
|
#define MC_SECURITY_CARVEOUT14_CLIENT_ACCESS6 0x22c0
|
|
#define MC_SECURITY_CARVEOUT12_CLIENT_ACCESS7 0x2224
|
|
#define MC_SECURITY_CARVEOUT11_CLIENT_FORCE_INTERNAL_ACCESS2 0x21c0
|
|
#define MC_SECURITY_CARVEOUT12_CLIENT_FORCE_INTERNAL_ACCESS7 0x222c
|
|
#define MC_SECURITY_CARVEOUT27_CLIENT_FORCE_INTERNAL_ACCESS1 0x26bc
|
|
#define MC_SECURITY_CARVEOUT8_CLIENT_FORCE_INTERNAL_ACCESS3 0x20d4
|
|
#define MC_SECURITY_CARVEOUT16_CLIENT_FORCE_INTERNAL_ACCESS1 0x234c
|
|
#define MC_SECURITY_CARVEOUT19_CLIENT_ACCESS6 0x2450
|
|
#define MC_SECURITY_CARVEOUT17_CLIENT_ACCESS4 0x2390
|
|
#define MC_SECURITY_CARVEOUT19_BOM_HI 0x2418
|
|
#define MC_SECURITY_CARVEOUT31_CLIENT_ACCESS0 0x27e0
|
|
#define MC_SECURITY_CARVEOUT27_CLIENT_ACCESS4 0x26b0
|
|
#define MC_SECURITY_CARVEOUT30_CLIENT_ACCESS1 0x2794
|
|
#define MC_SECURITY_CARVEOUT11_BOM_HI 0x2198
|
|
#define MC_SECURITY_CARVEOUT24_CLIENT_FORCE_INTERNAL_ACCESS0 0x25c8
|
|
#define MC_SECURITY_CARVEOUT23_BOM 0x2554
|
|
#define MC_SECURITY_CARVEOUT20_CLIENT_ACCESS3 0x247c
|
|
#define MC_SECURITY_CARVEOUT6_CLIENT_FORCE_INTERNAL_ACCESS0 0x2028
|
|
#define MC_SECURITY_CARVEOUT13_CLIENT_ACCESS0 0x2240
|
|
#define MC_SECURITY_CARVEOUT25_CLIENT_FORCE_INTERNAL_ACCESS0 0x2618
|
|
#define MC_SECURITY_CARVEOUT21_CLIENT_FORCE_INTERNAL_ACCESS3 0x24e4
|
|
#define MC_SECURITY_CARVEOUT6_CLIENT_FORCE_INTERNAL_ACCESS1 0x202c
|
|
#define MC_SECURITY_CARVEOUT22_CLIENT_ACCESS7 0x2544
|
|
#define MC_SECURITY_CARVEOUT21_BOM_HI 0x24b8
|
|
#define MC_SECURITY_CARVEOUT18_CLIENT_FORCE_INTERNAL_ACCESS0 0x23e8
|
|
#define MC_SECURITY_CARVEOUT23_CLIENT_FORCE_INTERNAL_ACCESS4 0x2588
|
|
#define MC_SECURITY_CARVEOUT25_SIZE_128KB 0x25fc
|
|
#define MC_SECURITY_CARVEOUT30_CFG0 0x2780
|
|
#define MC_SECURITY_CARVEOUT7_CLIENT_FORCE_INTERNAL_ACCESS7 0x209c
|
|
#define MC_SECURITY_CARVEOUT16_CLIENT_ACCESS2 0x2338
|
|
#define MC_SECURITY_CARVEOUT6_CLIENT_FORCE_INTERNAL_ACCESS2 0x2030
|
|
#define MC_SECURITY_CARVEOUT14_CLIENT_FORCE_INTERNAL_ACCESS6 0x22c8
|
|
#define MC_SECURITY_CARVEOUT19_CLIENT_ACCESS0 0x2420
|
|
#define MC_SECURITY_CARVEOUT9_CLIENT_FORCE_INTERNAL_ACCESS4 0x2128
|
|
#define MC_SECURITY_CARVEOUT7_CLIENT_ACCESS5 0x2074
|
|
#define MC_SECURITY_CARVEOUT16_CLIENT_ACCESS5 0x2344
|
|
#define MC_SECURITY_CARVEOUT15_CLIENT_ACCESS1 0x22e4
|
|
#define MC_SECURITY_CARVEOUT31_CLIENT_ACCESS4 0x27f0
|
|
#define MC_SECURITY_CARVEOUT15_CLIENT_FORCE_INTERNAL_ACCESS0 0x22f8
|
|
#define MC_SECURITY_CARVEOUT26_CLIENT_ACCESS0 0x2650
|
|
#define MC_SECURITY_CARVEOUT31_CLIENT_FORCE_INTERNAL_ACCESS7 0x281c
|
|
#define MC_SECURITY_CARVEOUT17_CLIENT_ACCESS6 0x23b0
|
|
#define MC_SECURITY_CARVEOUT11_CLIENT_ACCESS4 0x21b0
|
|
#define MC_SECURITY_CARVEOUT13_CLIENT_FORCE_INTERNAL_ACCESS2 0x2260
|
|
#define MC_SECURITY_CARVEOUT29_CLIENT_ACCESS5 0x2754
|
|
#define MC_SECURITY_CARVEOUT10_CLIENT_FORCE_INTERNAL_ACCESS6 0x2188
|
|
#define MC_SECURITY_CARVEOUT10_CLIENT_ACCESS4 0x2160
|
|
#define MC_SECURITY_CARVEOUT9_CLIENT_ACCESS5 0x2114
|
|
#define MC_SECURITY_CARVEOUT26_CLIENT_FORCE_INTERNAL_ACCESS1 0x266c
|
|
#define MC_SECURITY_CARVEOUT11_CLIENT_FORCE_INTERNAL_ACCESS0 0x21b8
|
|
#define MC_SECURITY_CARVEOUT8_CLIENT_ACCESS2 0x20b8
|
|
#define MC_SECURITY_CARVEOUT28_BOM_HI 0x26e8
|
|
#define MC_SECURITY_CARVEOUT8_BOM_HI 0x20a8
|
|
#define MC_SECURITY_CARVEOUT31_CLIENT_ACCESS5 0x27f4
|
|
#define MC_SECURITY_CARVEOUT22_CLIENT_FORCE_INTERNAL_ACCESS2 0x2530
|
|
#define MC_SECURITY_CARVEOUT10_BOM_HI 0x2148
|
|
#define MC_SECURITY_CARVEOUT7_CLIENT_FORCE_INTERNAL_ACCESS6 0x2098
|
|
#define MC_SECURITY_CARVEOUT21_CLIENT_ACCESS5 0x24d4
|
|
#define MC_SECURITY_CARVEOUT6_CLIENT_ACCESS7 0x2044
|
|
#define MC_SECURITY_CARVEOUT23_BOM_HI 0x2558
|
|
#define MC_SECURITY_CARVEOUT24_CLIENT_ACCESS2 0x25b8
|
|
#define MC_SECURITY_CARVEOUT26_BOM_HI 0x2648
|
|
#define MC_SECURITY_CARVEOUT6_CLIENT_ACCESS0 0x2010
|
|
#define MC_SECURITY_CARVEOUT19_CLIENT_FORCE_INTERNAL_ACCESS2 0x2440
|
|
#define MC_SECURITY_CARVEOUT30_BOM 0x2784
|
|
#define MC_SECURITY_CARVEOUT11_CLIENT_FORCE_INTERNAL_ACCESS7 0x21dc
|
|
#define MC_SECURITY_CARVEOUT18_CFG0 0x23c0
|
|
#define MC_SECURITY_CARVEOUT19_CLIENT_ACCESS7 0x2454
|
|
#define MC_SECURITY_CARVEOUT26_CLIENT_ACCESS5 0x2664
|
|
#define MC_SECURITY_CARVEOUT27_BOM_HI 0x2698
|
|
#define MC_SECURITY_CARVEOUT21_CLIENT_ACCESS1 0x24c4
|
|
#define MC_SECURITY_CARVEOUT12_CLIENT_ACCESS0 0x21f0
|
|
#define MC_SECURITY_CARVEOUT18_CLIENT_FORCE_INTERNAL_ACCESS4 0x23f8
|
|
#define MC_SECURITY_CARVEOUT28_CLIENT_FORCE_INTERNAL_ACCESS5 0x271c
|
|
#define MC_SECURITY_CARVEOUT14_CLIENT_FORCE_INTERNAL_ACCESS2 0x22b0
|
|
#define MC_SECURITY_CARVEOUT23_CLIENT_ACCESS0 0x2560
|
|
#define MC_SECURITY_CARVEOUT12_CLIENT_FORCE_INTERNAL_ACCESS1 0x220c
|
|
#define MC_SECURITY_CARVEOUT16_CLIENT_FORCE_INTERNAL_ACCESS6 0x2368
|
|
#define MC_SECURITY_CARVEOUT29_CLIENT_FORCE_INTERNAL_ACCESS4 0x2768
|
|
#define MC_SECURITY_CARVEOUT14_BOM 0x2284
|
|
#define MC_SECURITY_CARVEOUT18_CLIENT_FORCE_INTERNAL_ACCESS6 0x2408
|
|
#define MC_SECURITY_CARVEOUT30_CLIENT_ACCESS0 0x2790
|
|
#define MC_SECURITY_CARVEOUT16_CLIENT_FORCE_INTERNAL_ACCESS0 0x2348
|
|
#define MC_SECURITY_CARVEOUT30_CLIENT_ACCESS3 0x279c
|
|
#define MC_SECURITY_CARVEOUT26_CLIENT_FORCE_INTERNAL_ACCESS6 0x2688
|
|
#define MC_SECURITY_CARVEOUT17_CLIENT_ACCESS3 0x238c
|
|
#define MC_SECURITY_CARVEOUT25_CLIENT_ACCESS4 0x2610
|
|
#define MC_SECURITY_CARVEOUT19_CLIENT_ACCESS1 0x2424
|
|
#define MC_SECURITY_CARVEOUT20_CLIENT_ACCESS1 0x2474
|
|
#define MC_SECURITY_CARVEOUT13_CLIENT_FORCE_INTERNAL_ACCESS7 0x227c
|
|
#define MC_SECURITY_CARVEOUT17_CLIENT_ACCESS7 0x23b4
|
|
#define MC_SECURITY_CARVEOUT30_CLIENT_FORCE_INTERNAL_ACCESS5 0x27bc
|
|
#define MC_SECURITY_CARVEOUT17_BOM 0x2374
|
|
#define MC_SECURITY_CARVEOUT8_CLIENT_FORCE_INTERNAL_ACCESS6 0x20e8
|
|
#define MC_SECURITY_CARVEOUT18_CLIENT_ACCESS2 0x23d8
|
|
#define MC_SECURITY_CARVEOUT14_CLIENT_ACCESS3 0x229c
|
|
#define MC_SECURITY_CARVEOUT22_CLIENT_ACCESS6 0x2540
|
|
#define MC_SECURITY_CARVEOUT20_BOM_HI 0x2468
|
|
#define MC_SECURITY_CARVEOUT21_SIZE_128KB 0x24bc
|
|
#define MC_SECURITY_CARVEOUT23_CLIENT_FORCE_INTERNAL_ACCESS3 0x2584
|
|
#define MC_SECURITY_CARVEOUT11_CLIENT_ACCESS7 0x21d4
|
|
#define MC_SECURITY_CARVEOUT9_CLIENT_FORCE_INTERNAL_ACCESS3 0x2124
|
|
#define MC_SECURITY_CARVEOUT6_CLIENT_FORCE_INTERNAL_ACCESS3 0x2034
|
|
#define MC_SECURITY_CARVEOUT25_CLIENT_FORCE_INTERNAL_ACCESS5 0x262c
|
|
#define MC_SECURITY_CARVEOUT25_BOM 0x25f4
|
|
#define MC_SECURITY_CARVEOUT9_CLIENT_ACCESS6 0x2130
|
|
#define MC_SECURITY_CARVEOUT30_CLIENT_FORCE_INTERNAL_ACCESS6 0x27c8
|
|
#define MC_SECURITY_CARVEOUT6_CLIENT_FORCE_INTERNAL_ACCESS5 0x203c
|
|
#define MC_SECURITY_CARVEOUT16_CLIENT_ACCESS3 0x233c
|
|
#define MC_SECURITY_CARVEOUT7_CFG0 0x2050
|
|
#define MC_SECURITY_CARVEOUT19_CLIENT_FORCE_INTERNAL_ACCESS1 0x243c
|
|
#define MC_SECURITY_CARVEOUT10_CLIENT_ACCESS3 0x215c
|
|
#define MC_SECURITY_CARVEOUT24_CLIENT_ACCESS5 0x25c4
|
|
#define MC_SECURITY_CARVEOUT29_CLIENT_FORCE_INTERNAL_ACCESS0 0x2758
|
|
#define MC_SECURITY_CARVEOUT15_BOM_HI 0x22d8
|
|
#define MC_SECURITY_CARVEOUT13_CLIENT_ACCESS2 0x2248
|
|
#define MC_SECURITY_CARVEOUT12_CLIENT_FORCE_INTERNAL_ACCESS5 0x221c
|
|
#define MC_SECURITY_CARVEOUT15_CLIENT_ACCESS0 0x22e0
|
|
#define MC_SECURITY_CARVEOUT22_BOM 0x2504
|
|
#define MC_SECURITY_CARVEOUT9_CLIENT_ACCESS3 0x210c
|
|
#define MC_SECURITY_CARVEOUT21_CLIENT_ACCESS6 0x24f0
|
|
#define MC_SECURITY_CARVEOUT9_CFG0 0x20f0
|
|
#define MC_SECURITY_CARVEOUT9_CLIENT_FORCE_INTERNAL_ACCESS2 0x2120
|
|
#define MC_SECURITY_CARVEOUT17_CLIENT_ACCESS1 0x2384
|
|
#define MC_SECURITY_CARVEOUT17_BOM_HI 0x2378
|
|
#define MC_SECURITY_CARVEOUT16_CLIENT_FORCE_INTERNAL_ACCESS4 0x2358
|
|
#define MC_SECURITY_CARVEOUT31_CLIENT_FORCE_INTERNAL_ACCESS4 0x2808
|
|
#define MC_SECURITY_CARVEOUT21_CLIENT_ACCESS0 0x24c0
|
|
#define MC_SECURITY_CARVEOUT17_CLIENT_FORCE_INTERNAL_ACCESS2 0x23a0
|
|
#define MC_SECURITY_CARVEOUT23_CLIENT_FORCE_INTERNAL_ACCESS6 0x2598
|
|
#define MC_SECURITY_CARVEOUT17_CLIENT_FORCE_INTERNAL_ACCESS1 0x239c
|
|
#define MC_SECURITY_CARVEOUT24_CLIENT_FORCE_INTERNAL_ACCESS3 0x25d4
|
|
#define MC_SECURITY_CARVEOUT26_CLIENT_FORCE_INTERNAL_ACCESS5 0x267c
|
|
#define MC_SECURITY_CARVEOUT7_CLIENT_ACCESS1 0x2064
|
|
#define MC_SECURITY_CARVEOUT27_SIZE_128KB 0x269c
|
|
#define MC_SECURITY_CARVEOUT27_CLIENT_FORCE_INTERNAL_ACCESS0 0x26b8
|
|
#define MC_SECURITY_CARVEOUT29_CLIENT_FORCE_INTERNAL_ACCESS5 0x276c
|
|
#define MC_SECURITY_CARVEOUT13_CLIENT_ACCESS4 0x2250
|
|
#define MC_SECURITY_CARVEOUT12_BOM_HI 0x21e8
|
|
#define MC_SECURITY_CARVEOUT28_CLIENT_FORCE_INTERNAL_ACCESS4 0x2718
|
|
#define MC_SECURITY_CARVEOUT20_CLIENT_ACCESS0 0x2470
|
|
#define MC_SECURITY_CARVEOUT31_CLIENT_ACCESS2 0x27e8
|
|
#define MC_SECURITY_CARVEOUT20_CLIENT_FORCE_INTERNAL_ACCESS6 0x24a8
|
|
#define MC_SECURITY_CARVEOUT12_CLIENT_ACCESS6 0x2220
|
|
#define MC_SECURITY_CARVEOUT25_CLIENT_FORCE_INTERNAL_ACCESS4 0x2628
|
|
#define MC_SECURITY_CARVEOUT14_CLIENT_ACCESS4 0x22a0
|
|
#define MC_SECURITY_CARVEOUT19_CLIENT_FORCE_INTERNAL_ACCESS4 0x2448
|
|
#define MC_SECURITY_CARVEOUT8_CLIENT_FORCE_INTERNAL_ACCESS1 0x20cc
|
|
#define MC_SECURITY_CARVEOUT11_BOM 0x2194
|
|
#define MC_SECURITY_CARVEOUT28_CLIENT_ACCESS1 0x26f4
|
|
#define MC_SECURITY_CARVEOUT12_CLIENT_FORCE_INTERNAL_ACCESS6 0x2228
|
|
#define MC_SECURITY_CARVEOUT28_SIZE_128KB 0x26ec
|
|
#define MC_SECURITY_CARVEOUT9_CLIENT_FORCE_INTERNAL_ACCESS7 0x213c
|
|
#define MC_SECURITY_CARVEOUT22_CLIENT_ACCESS3 0x251c
|
|
#define MC_SECURITY_CARVEOUT23_CLIENT_ACCESS4 0x2570
|
|
#define MC_SECURITY_CARVEOUT12_CLIENT_ACCESS4 0x2200
|
|
#define MC_SECURITY_CARVEOUT22_CLIENT_FORCE_INTERNAL_ACCESS5 0x253c
|
|
#define MC_SECURITY_CARVEOUT29_CLIENT_ACCESS1 0x2744
|
|
#define MC_SECURITY_CARVEOUT13_SIZE_128KB 0x223c
|
|
#define MC_SECURITY_CARVEOUT16_CLIENT_ACCESS0 0x2330
|
|
#define MC_SECURITY_CARVEOUT21_CLIENT_FORCE_INTERNAL_ACCESS2 0x24e0
|
|
#define MC_SECURITY_CARVEOUT30_CLIENT_ACCESS7 0x27c4
|
|
#define MC_SECURITY_CARVEOUT19_BOM 0x2414
|
|
#define MC_SECURITY_CARVEOUT23_SIZE_128KB 0x255c
|
|
#define MC_SECURITY_CARVEOUT17_CLIENT_FORCE_INTERNAL_ACCESS0 0x2398
|
|
#define MC_SECURITY_CARVEOUT8_CLIENT_ACCESS5 0x20c4
|
|
#define MC_SECURITY_CARVEOUT23_CFG0 0x2550
|
|
#define MC_SECURITY_CARVEOUT23_CLIENT_ACCESS2 0x2568
|
|
#define MC_SECURITY_CARVEOUT12_SIZE_128KB 0x21ec
|
|
#define MC_SECURITY_CARVEOUT19_CLIENT_FORCE_INTERNAL_ACCESS3 0x2444
|
|
#define MC_SECURITY_CARVEOUT26_CLIENT_ACCESS7 0x2684
|
|
#define MC_SECURITY_CARVEOUT30_BOM_HI 0x2788
|
|
#define MC_SECURITY_CARVEOUT13_BOM 0x2234
|
|
#define MC_SECURITY_CARVEOUT13_CLIENT_ACCESS1 0x2244
|
|
#define MC_SECURITY_CARVEOUT27_CLIENT_ACCESS5 0x26b4
|
|
#define MC_SECURITY_CARVEOUT11_CLIENT_ACCESS6 0x21d0
|
|
#define MC_SECURITY_CARVEOUT20_CLIENT_FORCE_INTERNAL_ACCESS7 0x24ac
|
|
#define MC_SECURITY_CARVEOUT15_CLIENT_FORCE_INTERNAL_ACCESS3 0x2304
|
|
#define MC_SECURITY_CARVEOUT19_CLIENT_FORCE_INTERNAL_ACCESS7 0x245c
|
|
#define MC_SECURITY_CARVEOUT9_CLIENT_FORCE_INTERNAL_ACCESS1 0x211c
|
|
#define MC_SECURITY_CARVEOUT30_CLIENT_FORCE_INTERNAL_ACCESS3 0x27b4
|
|
#define MC_SECURITY_CARVEOUT24_BOM_HI 0x25a8
|
|
#define MC_SECURITY_CARVEOUT24_CLIENT_FORCE_INTERNAL_ACCESS2 0x25d0
|
|
#define MC_SECURITY_CARVEOUT18_CLIENT_ACCESS7 0x2404
|
|
#define MC_SECURITY_CARVEOUT15_CLIENT_ACCESS5 0x22f4
|
|
#define MC_SECURITY_CARVEOUT31_CFG0 0x27d0
|
|
#define MC_SECURITY_CARVEOUT9_CLIENT_ACCESS2 0x2108
|
|
#define MC_SECURITY_CARVEOUT16_CLIENT_FORCE_INTERNAL_ACCESS7 0x236c
|
|
#define MC_SECURITY_CARVEOUT31_BOM 0x27d4
|
|
#define MC_SECURITY_CARVEOUT28_CLIENT_FORCE_INTERNAL_ACCESS0 0x2708
|
|
#define MC_SECURITY_CARVEOUT23_CLIENT_FORCE_INTERNAL_ACCESS5 0x258c
|
|
#define MC_SECURITY_CARVEOUT18_CLIENT_FORCE_INTERNAL_ACCESS2 0x23f0
|
|
#define MC_SECURITY_CARVEOUT8_CLIENT_FORCE_INTERNAL_ACCESS4 0x20d8
|
|
#define MC_SECURITY_CARVEOUT24_CLIENT_ACCESS4 0x25c0
|
|
#define MC_SECURITY_CARVEOUT13_CLIENT_FORCE_INTERNAL_ACCESS5 0x226c
|
|
#define MC_SECURITY_CARVEOUT25_CLIENT_ACCESS7 0x2634
|
|
#define MC_SECURITY_CARVEOUT31_CLIENT_FORCE_INTERNAL_ACCESS5 0x280c
|
|
#define MC_SECURITY_CARVEOUT8_CLIENT_ACCESS0 0x20b0
|
|
#define MC_SECURITY_CARVEOUT25_CLIENT_ACCESS0 0x2600
|
|
#define MC_SECURITY_CARVEOUT24_CFG0 0x25a0
|
|
#define MC_SECURITY_CARVEOUT28_CFG0 0x26e0
|
|
#define MC_SECURITY_CARVEOUT24_SIZE_128KB 0x25ac
|
|
#define MC_SECURITY_CARVEOUT6_CFG0 0x2000
|
|
#define MC_SECURITY_CARVEOUT21_BOM 0x24b4
|
|
#define MC_SECURITY_CARVEOUT14_CLIENT_FORCE_INTERNAL_ACCESS7 0x22cc
|
|
#define MC_SECURITY_CARVEOUT20_CLIENT_FORCE_INTERNAL_ACCESS5 0x249c
|
|
#define MC_SECURITY_CARVEOUT28_CLIENT_FORCE_INTERNAL_ACCESS7 0x272c
|
|
#define MC_SECURITY_CARVEOUT29_CLIENT_ACCESS7 0x2774
|
|
#define MC_SECURITY_CARVEOUT14_BOM_HI 0x2288
|
|
#define MC_SECURITY_CARVEOUT9_SIZE_128KB 0x20fc
|
|
#define MC_SECURITY_CARVEOUT21_CLIENT_ACCESS7 0x24f4
|
|
#define MC_SECURITY_CARVEOUT20_BOM 0x2464
|
|
#define MC_SECURITY_CARVEOUT11_CLIENT_FORCE_INTERNAL_ACCESS5 0x21cc
|
|
#define MC_SECURITY_CARVEOUT14_CLIENT_ACCESS1 0x2294
|
|
#define MC_SECURITY_CARVEOUT29_CLIENT_ACCESS2 0x2748
|
|
#define MC_SECURITY_CARVEOUT22_CLIENT_ACCESS4 0x2520
|
|
#define MC_SECURITY_CARVEOUT9_CLIENT_ACCESS7 0x2134
|
|
#define MC_SECURITY_CARVEOUT29_CLIENT_FORCE_INTERNAL_ACCESS6 0x2778
|
|
#define MC_SECURITY_CARVEOUT11_CLIENT_ACCESS1 0x21a4
|
|
#define MC_SECURITY_CARVEOUT10_CLIENT_FORCE_INTERNAL_ACCESS3 0x2174
|
|
#define MC_SECURITY_CARVEOUT31_CLIENT_ACCESS3 0x27ec
|
|
#define MC_SECURITY_CARVEOUT13_CLIENT_FORCE_INTERNAL_ACCESS0 0x2258
|
|
#define MC_SECURITY_CARVEOUT18_CLIENT_ACCESS0 0x23d0
|
|
#define MC_SECURITY_CARVEOUT28_CLIENT_ACCESS0 0x26f0
|
|
#define MC_SECURITY_CARVEOUT30_CLIENT_FORCE_INTERNAL_ACCESS1 0x27ac
|
|
#define MC_SECURITY_CARVEOUT29_CLIENT_FORCE_INTERNAL_ACCESS2 0x2760
|
|
#define MC_SECURITY_CARVEOUT30_SIZE_128KB 0x278c
|
|
#define MC_SECURITY_CARVEOUT19_CLIENT_ACCESS2 0x2428
|
|
#define MC_SECURITY_CARVEOUT15_CLIENT_FORCE_INTERNAL_ACCESS1 0x22fc
|
|
#define MC_SECURITY_CARVEOUT26_CFG0 0x2640
|
|
#define MC_SECURITY_CARVEOUT28_CLIENT_FORCE_INTERNAL_ACCESS1 0x270c
|
|
#define MC_SECURITY_CARVEOUT19_CLIENT_FORCE_INTERNAL_ACCESS6 0x2458
|
|
#define MC_SECURITY_CARVEOUT31_SIZE_128KB 0x27dc
|
|
#define MC_SECURITY_CARVEOUT26_CLIENT_ACCESS4 0x2660
|
|
#define MC_SECURITY_CARVEOUT14_SIZE_128KB 0x228c
|
|
#define MC_SECURITY_CARVEOUT6_SIZE_128KB 0x200c
|
|
#define MC_SECURITY_CARVEOUT24_CLIENT_FORCE_INTERNAL_ACCESS5 0x25dc
|
|
#define MC_SECURITY_CARVEOUT8_CLIENT_ACCESS6 0x20e0
|
|
#define MC_SECURITY_CARVEOUT13_CLIENT_ACCESS6 0x2270
|
|
#define MC_SECURITY_CARVEOUT31_CLIENT_FORCE_INTERNAL_ACCESS2 0x2800
|
|
#define MC_SECURITY_CARVEOUT8_CLIENT_FORCE_INTERNAL_ACCESS7 0x20ec
|
|
#define MC_SECURITY_CARVEOUT26_CLIENT_FORCE_INTERNAL_ACCESS7 0x268c
|
|
#define MC_SECURITY_CARVEOUT27_CLIENT_FORCE_INTERNAL_ACCESS5 0x26cc
|
|
#define MC_SECURITY_CARVEOUT30_CLIENT_FORCE_INTERNAL_ACCESS4 0x27b8
|
|
#define MC_SECURITY_CARVEOUT28_CLIENT_ACCESS4 0x2700
|
|
#define MC_SECURITY_CARVEOUT20_CLIENT_FORCE_INTERNAL_ACCESS4 0x2498
|
|
#define MC_SECURITY_CARVEOUT21_CLIENT_FORCE_INTERNAL_ACCESS7 0x24fc
|
|
#define MC_SECURITY_CARVEOUT23_CLIENT_ACCESS1 0x2564
|
|
#define MC_SECURITY_CARVEOUT13_CLIENT_ACCESS3 0x224c
|
|
#define MC_SECURITY_CARVEOUT9_CLIENT_ACCESS1 0x2104
|
|
#define MC_SECURITY_CARVEOUT22_CLIENT_ACCESS1 0x2514
|
|
#define MC_SECURITY_CARVEOUT24_CLIENT_ACCESS7 0x25e4
|
|
#define MC_SECURITY_CARVEOUT29_CLIENT_FORCE_INTERNAL_ACCESS7 0x277c
|
|
#define MC_SECURITY_CARVEOUT7_CLIENT_ACCESS4 0x2070
|
|
#define MC_SECURITY_CARVEOUT10_CLIENT_ACCESS1 0x2154
|
|
#define MC_SECURITY_CARVEOUT18_CLIENT_ACCESS5 0x23e4
|
|
#define MC_SECURITY_CARVEOUT25_CLIENT_ACCESS2 0x2608
|
|
#define MC_SECURITY_CARVEOUT11_CLIENT_ACCESS0 0x21a0
|
|
#define MC_SECURITY_CARVEOUT23_CLIENT_ACCESS3 0x256c
|
|
#define MC_SECURITY_CARVEOUT27_CLIENT_FORCE_INTERNAL_ACCESS6 0x26d8
|
|
#define MC_SECURITY_CARVEOUT16_CLIENT_ACCESS7 0x2364
|
|
#define MC_SECURITY_CARVEOUT13_CLIENT_FORCE_INTERNAL_ACCESS4 0x2268
|
|
#define MC_SECURITY_CARVEOUT15_CLIENT_ACCESS4 0x22f0
|
|
#define MC_SECURITY_CARVEOUT24_BOM 0x25a4
|
|
#define MC_SECURITY_CARVEOUT9_CLIENT_FORCE_INTERNAL_ACCESS5 0x212c
|
|
#define MC_SECURITY_CARVEOUT12_CLIENT_FORCE_INTERNAL_ACCESS4 0x2218
|
|
#define MC_SECURITY_CARVEOUT30_CLIENT_FORCE_INTERNAL_ACCESS2 0x27b0
|
|
#define MC_SECURITY_CARVEOUT14_CLIENT_FORCE_INTERNAL_ACCESS5 0x22bc
|
|
#define MC_SECURITY_CARVEOUT18_CLIENT_FORCE_INTERNAL_ACCESS7 0x240c
|
|
#define MC_SECURITY_CARVEOUT12_CLIENT_ACCESS2 0x21f8
|
|
#define MC_SECURITY_CARVEOUT11_CLIENT_FORCE_INTERNAL_ACCESS4 0x21c8
|
|
#define MC_SECURITY_CARVEOUT28_CLIENT_ACCESS3 0x26fc
|
|
#define MC_SECURITY_CARVEOUT16_BOM 0x2324
|
|
#define MC_SECURITY_CARVEOUT10_CLIENT_FORCE_INTERNAL_ACCESS4 0x2178
|
|
#define MC_SECURITY_CARVEOUT8_CLIENT_FORCE_INTERNAL_ACCESS2 0x20d0
|
|
#define MC_SECURITY_CARVEOUT18_BOM_HI 0x23c8
|
|
#define MC_SECURITY_CARVEOUT7_CLIENT_FORCE_INTERNAL_ACCESS3 0x2084
|
|
#define MC_SECURITY_CARVEOUT21_CLIENT_FORCE_INTERNAL_ACCESS0 0x24d8
|
|
#define MC_SECURITY_CARVEOUT15_CLIENT_FORCE_INTERNAL_ACCESS5 0x230c
|
|
#define MC_SECURITY_CARVEOUT28_CLIENT_FORCE_INTERNAL_ACCESS6 0x2728
|
|
#define MC_SECURITY_CARVEOUT30_CLIENT_ACCESS4 0x27a0
|
|
#define MC_SECURITY_CARVEOUT15_CLIENT_ACCESS7 0x2314
|
|
#define MC_SECURITY_CARVEOUT26_CLIENT_ACCESS2 0x2658
|
|
#define MC_SECURITY_CARVEOUT27_CLIENT_ACCESS6 0x26d0
|
|
#define MC_SECURITY_CARVEOUT16_CLIENT_FORCE_INTERNAL_ACCESS5 0x235c
|
|
#define MC_SECURITY_CARVEOUT19_CLIENT_ACCESS3 0x242c
|
|
#define MC_SECURITY_CARVEOUT21_CLIENT_FORCE_INTERNAL_ACCESS6 0x24f8
|
|
#define MC_SECURITY_CARVEOUT30_CLIENT_ACCESS5 0x27a4
|
|
#define MC_SECURITY_CARVEOUT29_BOM 0x2734
|
|
#define MC_SECURITY_CARVEOUT11_CLIENT_FORCE_INTERNAL_ACCESS6 0x21d8
|
|
#define MC_SECURITY_CARVEOUT25_CLIENT_ACCESS5 0x2614
|
|
#define MC_SECURITY_CARVEOUT15_CLIENT_FORCE_INTERNAL_ACCESS7 0x231c
|
|
#define MC_SECURITY_CARVEOUT23_CLIENT_FORCE_INTERNAL_ACCESS1 0x257c
|
|
#define MC_SECURITY_CARVEOUT24_CLIENT_FORCE_INTERNAL_ACCESS7 0x25ec
|
|
#define MC_SECURITY_CARVEOUT24_CLIENT_ACCESS6 0x25e0
|
|
#define MC_SECURITY_CARVEOUT13_BOM_HI 0x2238
|
|
#define MC_SECURITY_CARVEOUT22_CLIENT_FORCE_INTERNAL_ACCESS7 0x254c
|
|
#define MC_SECURITY_CARVEOUT9_CLIENT_FORCE_INTERNAL_ACCESS0 0x2118
|
|
#define MC_SECURITY_CARVEOUT28_CLIENT_ACCESS2 0x26f8
|
|
#define MC_SECURITY_CARVEOUT17_CLIENT_ACCESS2 0x2388
|
|
#define MC_SECURITY_CARVEOUT21_CFG0 0x24b0
|
|
#define MC_SECURITY_CARVEOUT12_BOM 0x21e4
|
|
#define MC_SECURITY_CARVEOUT27_CLIENT_ACCESS0 0x26a0
|
|
#define MC_SECURITY_CARVEOUT6_CLIENT_ACCESS5 0x2024
|
|
#define MC_SECURITY_CARVEOUT27_CLIENT_FORCE_INTERNAL_ACCESS4 0x26c8
|
|
#define MC_SECURITY_CARVEOUT17_CLIENT_FORCE_INTERNAL_ACCESS3 0x23a4
|
|
#define MC_SECURITY_CARVEOUT31_CLIENT_ACCESS1 0x27e4
|
|
#define MC_SECURITY_CARVEOUT14_CLIENT_ACCESS2 0x2298
|
|
#define MC_SECURITY_CARVEOUT10_SIZE_128KB 0x214c
|
|
#define MC_SECURITY_CARVEOUT22_CLIENT_ACCESS2 0x2518
|
|
#define MC_SECURITY_CARVEOUT13_CLIENT_FORCE_INTERNAL_ACCESS6 0x2278
|
|
#define MC_SECURITY_CARVEOUT23_CLIENT_FORCE_INTERNAL_ACCESS7 0x259c
|
|
#define MC_SECURITY_CARVEOUT6_CLIENT_FORCE_INTERNAL_ACCESS4 0x2038
|
|
#define MC_SECURITY_CARVEOUT20_CLIENT_ACCESS7 0x24a4
|
|
#define MC_SECURITY_CARVEOUT9_CLIENT_ACCESS0 0x2100
|
|
#define MC_SECURITY_CARVEOUT17_CLIENT_FORCE_INTERNAL_ACCESS7 0x23bc
|
|
#define MC_SECURITY_CARVEOUT31_CLIENT_ACCESS7 0x2814
|
|
#define MC_SECURITY_CARVEOUT31_CLIENT_FORCE_INTERNAL_ACCESS3 0x2804
|
|
#define MC_SECURITY_CARVEOUT23_CLIENT_ACCESS6 0x2590
|
|
#define MC_SECURITY_CARVEOUT23_CLIENT_FORCE_INTERNAL_ACCESS0 0x2578
|
|
#define MC_SECURITY_CARVEOUT22_SIZE_128KB 0x250c
|
|
#define MC_SECURITY_CARVEOUT24_CLIENT_FORCE_INTERNAL_ACCESS4 0x25d8
|
|
#define MC_SECURITY_CARVEOUT27_CLIENT_ACCESS1 0x26a4
|
|
#define MC_SECURITY_CARVEOUT7_CLIENT_ACCESS7 0x2094
|
|
#define MC_SECURITY_CARVEOUT10_CLIENT_ACCESS2 0x2158
|
|
#define MC_SECURITY_CARVEOUT31_CLIENT_FORCE_INTERNAL_ACCESS0 0x27f8
|
|
#define MC_SECURITY_CARVEOUT7_CLIENT_ACCESS2 0x2068
|
|
#define MC_SECURITY_CARVEOUT23_CLIENT_ACCESS5 0x2574
|
|
#define MC_SECURITY_CARVEOUT6_CLIENT_FORCE_INTERNAL_ACCESS7 0x204c
|
|
#define MC_SECURITY_CARVEOUT28_CLIENT_ACCESS5 0x2704
|
|
#define MC_SECURITY_CARVEOUT7_CLIENT_FORCE_INTERNAL_ACCESS2 0x2080
|
|
#define MC_SECURITY_CARVEOUT11_SIZE_128KB 0x219c
|
|
#define MC_SECURITY_CARVEOUT31_CLIENT_FORCE_INTERNAL_ACCESS1 0x27fc
|
|
#define MC_SECURITY_CARVEOUT8_CLIENT_ACCESS7 0x20e4
|
|
#define MC_SECURITY_CARVEOUT25_BOM_HI 0x25f8
|
|
#define MC_SECURITY_CARVEOUT16_CLIENT_ACCESS6 0x2360
|
|
#define MC_SECURITY_CARVEOUT31_BOM_HI 0x27d8
|
|
#define MC_SECURITY_CARVEOUT18_CLIENT_FORCE_INTERNAL_ACCESS1 0x23ec
|
|
#define MC_SECURITY_CARVEOUT16_BOM_HI 0x2328
|
|
#define MC_SECURITY_CARVEOUT20_CFG0 0x2460
|
|
#define MC_SECURITY_CARVEOUT20_CLIENT_FORCE_INTERNAL_ACCESS3 0x2494
|
|
#define MC_SECURITY_CARVEOUT21_CLIENT_FORCE_INTERNAL_ACCESS1 0x24dc
|
|
#define MC_SECURITY_CARVEOUT14_CLIENT_FORCE_INTERNAL_ACCESS0 0x22a8
|
|
#define MC_SECURITY_CARVEOUT17_CLIENT_FORCE_INTERNAL_ACCESS4 0x23a8
|
|
#define MC_SECURITY_CARVEOUT25_CLIENT_FORCE_INTERNAL_ACCESS2 0x2620
|
|
#define MC_SECURITY_CARVEOUT25_CFG0 0x25f0
|
|
#define MC_SECURITY_CARVEOUT8_CLIENT_ACCESS3 0x20bc
|
|
#define MC_SECURITY_CARVEOUT13_CLIENT_FORCE_INTERNAL_ACCESS3 0x2264
|
|
#define MC_SECURITY_CARVEOUT10_CLIENT_FORCE_INTERNAL_ACCESS1 0x216c
|
|
#define MC_SECURITY_CARVEOUT14_CFG0 0x2280
|
|
#define MC_SECURITY_CARVEOUT8_BOM 0x20a4
|
|
#define MC_SECURITY_CARVEOUT22_CFG0 0x2500
|
|
#define MC_SECURITY_CARVEOUT29_CLIENT_ACCESS4 0x2750
|
|
#define MC_SECURITY_CARVEOUT26_SIZE_128KB 0x264c
|
|
#define MC_SECURITY_CARVEOUT13_CFG0 0x2230
|
|
#define MC_SECURITY_CARVEOUT22_CLIENT_FORCE_INTERNAL_ACCESS6 0x2548
|
|
#define MC_SECURITY_CARVEOUT26_BOM 0x2644
|
|
#define MC_SECURITY_CARVEOUT29_CLIENT_FORCE_INTERNAL_ACCESS1 0x275c
|
|
#define MC_SECURITY_CARVEOUT26_CLIENT_ACCESS6 0x2680
|
|
#define MC_SECURITY_CARVEOUT30_CLIENT_ACCESS6 0x27c0
|
|
#define MC_SECURITY_CARVEOUT12_CLIENT_ACCESS5 0x2204
|
|
#define MC_SECURITY_CARVEOUT17_SIZE_128KB 0x237c
|
|
#define MC_SECURITY_CARVEOUT19_CLIENT_FORCE_INTERNAL_ACCESS5 0x244c
|
|
#define MC_SECURITY_CARVEOUT14_CLIENT_ACCESS7 0x22c4
|
|
#define MC_SECURITY_CARVEOUT18_CLIENT_ACCESS6 0x2400
|
|
#define MC_SECURITY_CARVEOUT15_CLIENT_ACCESS6 0x2310
|
|
#define MC_SECURITY_CARVEOUT15_CLIENT_FORCE_INTERNAL_ACCESS6 0x2318
|
|
#define MC_ERR_APB_ASID_UPDATE_STATUS 0x9d0
|
|
#define MC_DA_CONFIG0 0x9dc
|
|
#define MC_TXN_OVERRIDE_CONFIG_HDAR 0x10a8
|
|
#define MC_TXN_OVERRIDE_CONFIG_DLA1WRA 0x1624
|
|
#define MC_TXN_OVERRIDE_CONFIG_PCIE1W 0x16dc
|
|
#define MC_TXN_OVERRIDE_CONFIG_PVA0RDC 0x1644
|
|
#define MC_TXN_OVERRIDE_CONFIG_PTCR 0x1000
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_APEDMAW 0x1504
|
|
#define MC_TXN_OVERRIDE_CONFIG_EQOSW 0x1478
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_PVA1WRA 0x1680
|
|
#define MC_TXN_OVERRIDE_CONFIG_MPCOREW 0x11c8
|
|
#define MC_TXN_OVERRIDE_CONFIG_DLA1FALWRB 0x162c
|
|
#define MC_TXN_OVERRIDE_CONFIG_AXISR 0x1460
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_DLA0RDA1 0x1750
|
|
#define MC_TXN_OVERRIDE_CONFIG_PVA0WRB 0x1654
|
|
#define MC_TXN_OVERRIDE_CONFIG_MIU6R 0x17f4
|
|
#define MC_TXN_OVERRIDE_CONFIG_MIU5R 0x17e4
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_RCEW 0x16a0
|
|
#define MC_TXN_OVERRIDE_CONFIG_NVENCSRD1 0x1784
|
|
#define MC_TXN_OVERRIDE_CONFIG_PCIE0R 0x16c4
|
|
#define MC_TXN_OVERRIDE_CONFIG_EQOSR 0x1470
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_ISPFALR 0x122c
|
|
#define MC_TXN_OVERRIDE_CONFIG_NVENCSRD 0x10e0
|
|
#define MC_TXN_OVERRIDE_CONFIG_NVENC1SRD1 0x178c
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_XUSB_DEVW 0x126c
|
|
#define MC_TXN_OVERRIDE_CONFIG_PVA1RDB1 0x1774
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_AXISR 0x1464
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_DLA0WRA 0x1608
|
|
#define MC_TXN_OVERRIDE_CONFIG_NVENC1SWR 0x16bc
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_MIU1W 0x154c
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_SATAW 0x11ec
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE3W 0x1700
|
|
#define MC_TXN_OVERRIDE_CONFIG_VICSRD1 0x1510
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_XUSB_HOSTR 0x1254
|
|
#define MC_TXN_OVERRIDE_CONFIG_BPMPDMAR 0x14a8
|
|
#define MC_TXN_OVERRIDE_CONFIG_VIW 0x1390
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_BPMPDMAW 0x14b4
|
|
#define MC_TXN_OVERRIDE_CONFIG_PCIE5R 0x1714
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_PVA1RDB 0x1670
|
|
#define MC_TXN_OVERRIDE_CONFIG_AXISW 0x1468
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_XUSB_HOSTW 0x125c
|
|
#define MC_TXN_OVERRIDE_CONFIG_MIU6W 0x17fc
|
|
#define MC_TXN_OVERRIDE_CONFIG_UFSHCR 0x1480
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_MIU6R 0x17f8
|
|
#define MC_TXN_OVERRIDE_CONFIG_PCIE0R1 0x179c
|
|
#define MC_TXN_OVERRIDE_CONFIG_PVA0RDB1 0x1764
|
|
#define MC_TXN_OVERRIDE_CONFIG_TSECSWR 0x12a8
|
|
#define MC_TXN_OVERRIDE_CONFIG_MIU7R 0x1008
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE2AW 0x16f0
|
|
#define MC_TXN_OVERRIDE_CONFIG_SATAR 0x10f8
|
|
#define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTW 0x1258
|
|
#define MC_TXN_OVERRIDE_CONFIG_DLA0RDA 0x15f4
|
|
#define MC_TXN_OVERRIDE_CONFIG_TSECSWRB 0x1438
|
|
#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SWR 0x17dc
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE0R 0x16c8
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_RCEDMAR 0x16a8
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_NVENC1SRD1 0x1790
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_TSECSRD 0x12a4
|
|
#define MC_TXN_OVERRIDE_CONFIG_PVA1RDA1 0x176c
|
|
#define MC_TXN_OVERRIDE_CONFIG_PVA1RDB 0x166c
|
|
#define MC_TXN_OVERRIDE_CONFIG_AONDMAW 0x14d0
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_ISPWA 0x1234
|
|
#define MC_TXN_OVERRIDE_CONFIG_AONW 0x14c0
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_RCEDMAW 0x16b0
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE2AR 0x16e8
|
|
#define MC_TXN_OVERRIDE_CONFIG_ETRR 0x1420
|
|
#define MC_TXN_OVERRIDE_CONFIG_PCIE2AW 0x16ec
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_VIW 0x1394
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_BPMPR 0x149c
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_NVDECSRD 0x13c4
|
|
#define MC_TXN_OVERRIDE_CONFIG_PCIE1R 0x16d4
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_EQOSR 0x1474
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_PVA0RDC 0x1648
|
|
#define MC_TXN_OVERRIDE_CONFIG_PVA1RDC 0x1674
|
|
#define MC_TXN_OVERRIDE_CONFIG_PVA0WRA 0x164c
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_SDMMCR 0x1314
|
|
#define MC_TXN_OVERRIDE_CONFIG_TSECSRDB 0x1430
|
|
#define MC_TXN_OVERRIDE_CONFIG_MIU1W 0x1548
|
|
#define MC_TXN_OVERRIDE_CONFIG_PCIE0W 0x16cc
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_MIU3R 0x1584
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_MIU6W 0x4c00
|
|
#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SRD 0x17cc
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_UFSHCW 0x148c
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_AONR 0x14bc
|
|
#define MC_TXN_OVERRIDE_CONFIG_MIU7W 0x1010
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_MIU4W 0x15a0
|
|
#define MC_TXN_OVERRIDE_CONFIG_NVDECSRD1 0x1518
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_PVA1RDC 0x1678
|
|
#define MC_TXN_OVERRIDE_CONFIG_MIU3R 0x1580
|
|
#define MC_TXN_OVERRIDE_CONFIG_MIU3W 0x158c
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_AONDMAW 0x14d4
|
|
#define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTR 0x1250
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_MIU2R 0x1574
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_MIU5R 0x17e8
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_SATAR 0x10fc
|
|
#define MC_TXN_OVERRIDE_CONFIG_SESRD 0x1400
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_SESRD 0x1404
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_SDMMCWAB 0x133c
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_AXISW 0x146c
|
|
#define MC_TXN_OVERRIDE_CONFIG_SCER 0x14d8
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_DLA1RDA 0x1618
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_TSECSWRB 0x143c
|
|
#define MC_TXN_OVERRIDE_CONFIG_MPCORER 0x1138
|
|
#define MC_TXN_OVERRIDE_CONFIG_SDMMCWA 0x1320
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE3R 0x16f8
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_MIU3W 0x1590
|
|
#define MC_TXN_OVERRIDE_CONFIG_HDAW 0x11a8
|
|
#define MC_TXN_OVERRIDE_CONFIG_NVDECSWR 0x13c8
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE4R 0x1708
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_PTCR 0x1004
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_DLA1RDA1 0x1758
|
|
#define MC_TXN_OVERRIDE_CONFIG_PVA0RDA 0x1634
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_NVDECSWR 0x13cc
|
|
#define MC_TXN_OVERRIDE_CONFIG_AONDMAR 0x14c8
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_DLA1FALWRB 0x1630
|
|
#define MC_TXN_OVERRIDE_CONFIG_SDMMCWAB 0x1338
|
|
#define MC_TXN_OVERRIDE_CONFIG_ISPFALR 0x1228
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_SCEW 0x14e4
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_SDMMCWA 0x1324
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE1W 0x16e0
|
|
#define MC_TXN_OVERRIDE_CONFIG_PVA0RDA1 0x175c
|
|
#define MC_TXN_OVERRIDE_CONFIG_NVENC1SRD 0x16b4
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_HDAR 0x10ac
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_BPMPW 0x14a4
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_AXIAPW 0x141c
|
|
#define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR1 0x1508
|
|
#define MC_TXN_OVERRIDE_CONFIG_PVA1RDA 0x1664
|
|
#define MC_TXN_OVERRIDE_CONFIG_DLA0RDA1 0x174c
|
|
#define MC_TXN_OVERRIDE_CONFIG_ISPWB 0x1238
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE1R 0x16d8
|
|
#define MC_TXN_OVERRIDE_CONFIG_APEW 0x13d8
|
|
#define MC_TXN_OVERRIDE_CONFIG_AXIAPR 0x1410
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_ETRW 0x142c
|
|
#define MC_TXN_OVERRIDE_CONFIG_PCIE2AR 0x16e4
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_DLA1FALRDB 0x1620
|
|
#define MC_TXN_OVERRIDE_CONFIG_ISPFALW 0x1724
|
|
#define MC_TXN_OVERRIDE_CONFIG_SDMMCR 0x1310
|
|
#define MC_TXN_OVERRIDE_CONFIG_MIU2W 0x1578
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_DLA0FALRDB 0x1600
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_MIU7W 0x1014
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_DLA0FALWRB 0x1610
|
|
#define MC_TXN_OVERRIDE_CONFIG_RCER 0x1694
|
|
#define MC_TXN_OVERRIDE_CONFIG_PCIE4W 0x170c
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_VIFALR 0x15e8
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_VICSRD 0x1364
|
|
#define MC_TXN_OVERRIDE_CONFIG_BPMPW 0x14a0
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_AONDMAR 0x14cc
|
|
#define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR 0x1490
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_PVA0RDA 0x1638
|
|
#define MC_TXN_OVERRIDE_CONFIG_ISPRA 0x1220
|
|
#define MC_TXN_OVERRIDE_CONFIG_NVJPGSWR 0x13f8
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_PVA1RDA1 0x1770
|
|
#define MC_TXN_OVERRIDE_CONFIG_VICSRD 0x1360
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_MIU5W 0x17f0
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_NVDECSRD1 0x151c
|
|
#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SRD1 0x17d4
|
|
#define MC_TXN_OVERRIDE_CONFIG_DLA1RDA 0x1614
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_VICSRD1 0x1514
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_BPMPDMAR 0x14ac
|
|
#define MC_TXN_OVERRIDE_CONFIG_SCEDMAW 0x14f0
|
|
#define MC_TXN_OVERRIDE_CONFIG_SDMMCW 0x1330
|
|
#define MC_TXN_OVERRIDE_CONFIG_DLA1FALRDB 0x161c
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_SESWR 0x140c
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_EQOSW 0x147c
|
|
#define MC_TXN_OVERRIDE_CONFIG_APEDMAR 0x14f8
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_ETRR 0x1424
|
|
#define MC_TXN_OVERRIDE_CONFIG_RCEW 0x169c
|
|
#define MC_TXN_OVERRIDE_CONFIG_SDMMCRAB 0x1318
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_MPCORER 0x113c
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_MIU0R 0x1534
|
|
#define MC_TXN_OVERRIDE_CONFIG_DLA0WRA 0x1604
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_XUSB_DEVR 0x1264
|
|
#define MC_TXN_OVERRIDE_CONFIG_VIFALR 0x15e4
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_NVJPGSRD 0x13f4
|
|
#define MC_TXN_OVERRIDE_CONFIG_PCIE3R 0x16f4
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_NVENC1SWR 0x16c0
|
|
#define MC_TXN_OVERRIDE_CONFIG_MIU1R 0x1540
|
|
#define MC_TXN_OVERRIDE_CONFIG_PCIE5W 0x171c
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE5R1 0x1780
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE5W 0x1720
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_SDMMCW 0x1334
|
|
#define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVR 0x1260
|
|
#define MC_TXN_OVERRIDE_CONFIG_MIU0W 0x1538
|
|
#define MC_TXN_OVERRIDE_CONFIG_DLA0FALWRB 0x160c
|
|
#define MC_TXN_OVERRIDE_CONFIG_VIFALW 0x15ec
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_ISPRA1 0x1798
|
|
#define MC_TXN_OVERRIDE_CONFIG_DLA0FALRDB 0x15fc
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_DLA0RDA 0x15f8
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_PVA0RDB1 0x1768
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_APER 0x13d4
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_ISPRA 0x1224
|
|
#define MC_TXN_OVERRIDE_CONFIG_PCIE3W 0x16fc
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_DLA1WRA 0x1628
|
|
#define MC_TXN_OVERRIDE_CONFIG_MIU0R 0x1530
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_PVA1WRC 0x1690
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_VICSWR 0x136c
|
|
#define MC_TXN_OVERRIDE_CONFIG_PVA0WRC 0x165c
|
|
#define MC_TXN_OVERRIDE_CONFIG_SCEDMAR 0x14e8
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_AONW 0x14c4
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_SCEDMAR 0x14ec
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_AXIAPR 0x1414
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_PVA1RDA 0x1668
|
|
#define MC_TXN_OVERRIDE_CONFIG_APEDMAW 0x1500
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_MIU4R 0x1598
|
|
#define MC_TXN_OVERRIDE_CONFIG_HOST1XDMAR 0x10b0
|
|
#define MC_TXN_OVERRIDE_CONFIG_SESWR 0x1408
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_SDMMCRA 0x1304
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_TSECSWR 0x12ac
|
|
#define MC_TXN_OVERRIDE_CONFIG_AXIAPW 0x1418
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_TSECSRDB 0x1434
|
|
#define MC_TXN_OVERRIDE_CONFIG_MIU4R 0x1594
|
|
#define MC_TXN_OVERRIDE_CONFIG_MIU4W 0x159c
|
|
#define MC_TXN_OVERRIDE_CONFIG_NVJPGSRD 0x13f0
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_PVA0WRB 0x1658
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_RCER 0x1698
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_PVA1RDB1 0x1778
|
|
#define MC_TXN_OVERRIDE_CONFIG_NVDECSRD 0x13c0
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_APEDMAR 0x14fc
|
|
#define MC_TXN_OVERRIDE_CONFIG_BPMPDMAW 0x14b0
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_UFSHCR 0x1484
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_MIU7R 0x100c
|
|
#define MC_TXN_OVERRIDE_CONFIG_APER 0x13d0
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_MPCOREW 0x11cc
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE4W 0x1710
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE0R1 0x17a0
|
|
#define MC_TXN_OVERRIDE_CONFIG_DLA1RDA1 0x1754
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_NVENCSRD1 0x1788
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_HOST1XDMAR 0x10b4
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_MIU2W 0x157c
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_NVDEC1SRD1 0x17d8
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_PVA1WRB 0x1688
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE0W 0x16d0
|
|
#define MC_TXN_OVERRIDE_CONFIG_PVA1WRB 0x1684
|
|
#define MC_TXN_OVERRIDE_CONFIG_ISPWA 0x1230
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_PVA0WRA 0x1650
|
|
#define MC_TXN_OVERRIDE_CONFIG_PVA1WRC 0x168c
|
|
#define MC_TXN_OVERRIDE_CONFIG_RCEDMAR 0x16a4
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_MIU1R 0x1544
|
|
#define MC_TXN_OVERRIDE_CONFIG_ISPRA1 0x1794
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_ISPWB 0x123c
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_MIU0W 0x153c
|
|
#define MC_TXN_OVERRIDE_CONFIG_AONR 0x14b8
|
|
#define MC_TXN_OVERRIDE_CONFIG_RCEDMAW 0x16ac
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE5R 0x1718
|
|
#define MC_TXN_OVERRIDE_CONFIG_UFSHCW 0x1488
|
|
#define MC_TXN_OVERRIDE_CONFIG_ETRW 0x1428
|
|
#define MC_TXN_OVERRIDE_CONFIG_SATAW 0x11e8
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_SDMMCRAB 0x131c
|
|
#define MC_TXN_OVERRIDE_CONFIG_VICSWR 0x1368
|
|
#define MC_TXN_OVERRIDE_CONFIG_NVENCSWR 0x1158
|
|
#define MC_TXN_OVERRIDE_CONFIG_PCIE5R1 0x177c
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_SCER 0x14dc
|
|
#define MC_TXN_OVERRIDE_CONFIG_PVA0RDB 0x163c
|
|
#define MC_TXN_OVERRIDE_CONFIG_SDMMCRA 0x1300
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_NVDISPLAYR1 0x150c
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_NVENCSWR 0x115c
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_NVJPGSWR 0x13fc
|
|
#define MC_TXN_OVERRIDE_CONFIG_PVA1WRA 0x167c
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_PVA0RDA1 0x1760
|
|
#define MC_TXN_OVERRIDE_CONFIG_MIU5W 0x17ec
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_VIFALW 0x15f0
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_SCEDMAW 0x14f4
|
|
#define MC_TXN_OVERRIDE_CONFIG_BPMPR 0x1498
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_NVDEC1SRD 0x17d0
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_NVDEC1SWR 0x17e0
|
|
#define MC_TXN_OVERRIDE_CONFIG_MIU2R 0x1570
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_NVDISPLAYR 0x1494
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_HDAW 0x11ac
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_NVENCSRD 0x10e4
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_PVA0RDB 0x1640
|
|
#define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVW 0x1268
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_NVENC1SRD 0x16b8
|
|
#define MC_TXN_OVERRIDE_CONFIG_TSECSRD 0x12a0
|
|
#define MC_TXN_OVERRIDE_CONFIG_PCIE4R 0x1704
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_APEW 0x13dc
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_ISPFALW 0x1728
|
|
#define MC_TXN_OVERRIDE_CONFIG_SCEW 0x14e0
|
|
#define MC_TBU_CLIENT_STEERING_CONFIG_PVA0WRC 0x1660
|
|
#define MC_TBU_ADR_MASK_0 0x1800
|
|
#define MC_TBU_ADR_MASK_1 0x1804
|
|
#define MC_TBU_ADR_MASK_2 0x18bc
|
|
#define MC_CLIENT_TRAFFIC_TYPE_CONFIG_0 0x1808
|
|
#define MC_CLIENT_TRAFFIC_TYPE_CONFIG_1 0x180c
|
|
#define MC_CLIENT_TRAFFIC_TYPE_CONFIG_2 0x1810
|
|
#define MC_CLIENT_TRAFFIC_TYPE_CONFIG_3 0x1814
|
|
#define MC_CLIENT_TRAFFIC_TYPE_CONFIG_4 0x1818
|
|
#define MC_CLIENT_TRAFFIC_TYPE_CONFIG_5 0x181c
|
|
#define MC_CLIENT_TRAFFIC_TYPE_CONFIG_6 0x18b0
|
|
#define MC_CLIENT_TRAFFIC_TYPE_CONFIG_7 0x18b4
|
|
#define MC_MC_TBU_TRANSACTION_ATTR_CTRL 0x18b8
|
|
#define MC_CLIENT_ORDER_ID_27 0x2a6c
|
|
#define MC_CLIENT_ORDER_ID_13 0x2a34
|
|
#define MC_CLIENT_ORDER_ID_9 0x2a24
|
|
#define MC_CLIENT_ORDER_ID_4 0x2a10
|
|
#define MC_CLIENT_ORDER_ID_10 0x2a28
|
|
#define MC_CLIENT_ORDER_ID_21 0x2a54
|
|
#define MC_CLIENT_ORDER_ID_26 0x2a68
|
|
#define MC_CLIENT_ORDER_ID_17 0x2a44
|
|
#define MC_CLIENT_ORDER_ID_15 0x2a3c
|
|
#define MC_CLIENT_ORDER_ID_6 0x2a18
|
|
#define MC_CLIENT_ORDER_ID_30 0x2d00
|
|
#define MC_CLIENT_ORDER_ID_18 0x2a48
|
|
#define MC_CLIENT_ORDER_ID_5 0x2a14
|
|
#define MC_CLIENT_ORDER_ID_23 0x2a5c
|
|
#define MC_CLIENT_ORDER_ID_29 0x2a74
|
|
#define MC_CLIENT_ORDER_ID_14 0x2a38
|
|
#define MC_CLIENT_ORDER_ID_24 0x2a60
|
|
#define MC_CLIENT_ORDER_ID_3 0x2a0c
|
|
#define MC_CLIENT_ORDER_ID_19 0x2a4c
|
|
#define MC_CLIENT_ORDER_ID_7 0x2a1c
|
|
#define MC_CLIENT_ORDER_ID_0 0x2a00
|
|
#define MC_CLIENT_ORDER_ID_2 0x2a08
|
|
#define MC_CLIENT_ORDER_ID_16 0x2a40
|
|
#define MC_CLIENT_ORDER_ID_22 0x2a58
|
|
#define MC_CLIENT_ORDER_ID_12 0x2a30
|
|
#define MC_CLIENT_ORDER_ID_28 0x2a70
|
|
#define MC_CLIENT_ORDER_ID_31 0x2d04
|
|
#define MC_CLIENT_ORDER_ID_25 0x2a64
|
|
#define MC_CLIENT_ORDER_ID_20 0x2a50
|
|
#define MC_CLIENT_ORDER_ID_8 0x2a20
|
|
#define MC_HUB_PC_VC_ID_11 0x2aa4
|
|
#define MC_HUB_PC_VC_ID_12 0x2aa8
|
|
#define MC_HUB_PC_VC_ID_2 0x2a80
|
|
#define MC_HUB_PC_VC_ID_10 0x2aa0
|
|
#define MC_HUB_PC_VC_ID_6 0x2a90
|
|
#define MC_HUB_PC_VC_ID_13 0x2d78
|
|
#define MC_HUB_PC_VC_ID_1 0x2a7c
|
|
#define MC_HUB_PC_VC_ID_7 0x2a94
|
|
#define MC_HUB_PC_VC_ID_0 0x2a78
|
|
#define MC_HUB_PC_VC_ID_9 0x2a9c
|
|
#define MC_HUB_PC_VC_ID_5 0x2a8c
|
|
#define MC_HUB_PC_VC_ID_3 0x2a84
|
|
#define MC_HUB_PC_VC_ID_8 0x2a98
|
|
#define MC_HUB_PC_VC_ID_14 0x2d7c
|
|
#define MC_HUB_PC_VC_ID_4 0x2a88
|
|
#define MC_COALESCE_CTRL 0x2930
|
|
#define MC_CLIENT_COALESCE_CONFIG_0 0x2934
|
|
#define MC_CLIENT_COALESCE_CONFIG_1 0x2938
|
|
#define MC_CLIENT_COALESCE_CONFIG_2 0x293c
|
|
#define MC_CLIENT_COALESCE_CONFIG_3 0x2940
|
|
#define MC_CLIENT_COALESCE_CONFIG_4 0x2944
|
|
#define MC_CLIENT_COALESCE_CONFIG_5 0x2948
|
|
#define MC_CLIENT_COALESCE_CONFIG_6 0x294c
|
|
#define MC_CLIENT_COALESCE_CONFIG_7 0x2950
|
|
#define MC_HUB_VC_ARB_SEL 0x2954
|
|
#define MC_MC_SMMU_ARB_MAX_OUTSTANDING_NISO 0x2958
|
|
#define MC_MC_SMMU_ARB_MAX_OUTSTANDING_SISO 0x295c
|
|
#define MC_MC_SMMU_ARB_MAX_OUTSTANDING_ISO 0x2960
|
|
#define MC_MC_SMMU_ARB_MAX_THROTTLE 0x2964
|
|
#define MC_MC_SMMU_PTC2H_REQ_MAPPING_OVERRIDE 0x296c
|
|
#define MC_MC_SMMU_PTC2H_REQ_MAPPING 0x2970
|
|
#define MC_COALESCE_ERR_STATUS 0x3000
|
|
#define MC_COALESCE_ERR_ADR_HI 0x3004
|
|
#define MC_COALESCE_ERR_ADR 0x3008
|
|
#define MC_CLIENT_CCI_CAPABLE_0 0x1824
|
|
#define MC_CLIENT_CCI_CAPABLE_1 0x1828
|
|
#define MC_CLIENT_CCI_CAPABLE_2 0x182c
|
|
#define MC_CLIENT_CCI_CAPABLE_3 0x1830
|
|
#define MC_CLIENT_CCI_CAPABLE_4 0x1834
|
|
#define MC_CLIENT_CCI_CAPABLE_5 0x1838
|
|
#define MC_CLIENT_CCI_CAPABLE_6 0x183c
|
|
#define MC_CLIENT_CCI_CAPABLE_8 0x1c34
|
|
#define MC_CLIENT_CCI_CAPABLE_7 0x193c
|
|
#define MC_MAX_OUTSTANDING_CCI 0x1840
|
|
#define MC_NV_CACHE_CONFIG 0x1844
|
|
#define MC_NV_CACHE_HUB_MASK 0x184c
|
|
#define MC_SYSRAM_BOM 0x1850
|
|
#define MC_SYSRAM_TOM 0x1854
|
|
#define MC_SYSRAM_ADR_HI 0x1588
|
|
#define MC_SYSRAM_REG_CTRL 0x185c
|
|
#define MC_MSSNVLINK_BOM 0x1860
|
|
#define MC_MSSNVLINK_TOM 0x1864
|
|
#define MC_MSSNVLINK_REG_CTRL 0x186c
|
|
#define MC_SYNCPOINT_BOM 0x1870
|
|
#define MC_SYNCPOINT_TOM 0x1874
|
|
#define MC_SYNCPOINT_REG_CTRL 0x187c
|
|
#define MC_ECC_CONTROL 0x1880
|
|
#define MC_MSSNVLINK_IGPU_LATENCY_ALLOWANCE 0x1890
|
|
#define MC_MSSNVLINK_DGPU_LATENCY_ALLOWANCE 0x1894
|
|
#define MC_CIFLL_NVLRHP_LATENCY_ALLOWANCE 0x189c
|
|
#define MC_CLIENT_HOTRESET_STATUS_2 0x1898
|
|
#define MC_CFG_WCAM_GOB_REMAP 0xed4
|
|
#define MC_ECC_RAW_MODE_CONTROL 0xed8
|
|
#define MC_ECC_CFG 0x1884
|
|
#define MC_TR_BIT_CTL 0xed0
|
|
#define MC_CH_INTSTATUS 0xe54
|
|
#define MC_LATENCY_ALLOWANCE_WCAM 0xe5c
|
|
#define MC_CFG_WCAM 0xe60
|
|
#define MC_WCAM_ENCR_KEY_STATUS 0xe64
|
|
#define MC_WCAM_STATE 0xeb0
|
|
#define MC_WCAM_IRQ_TEST 0xedc
|
|
#define MC_WCAM_IRQ_P0_STATUS0 0xee0
|
|
#define MC_WCAM_IRQ_P0_STATUS1 0xee4
|
|
#define MC_WCAM_IRQ_P1_STATUS0 0xee8
|
|
#define MC_WCAM_IRQ_P1_STATUS1 0xeec
|
|
#define MC_ROC_DMA_R_PTSA_MIN 0xe68
|
|
#define MC_ROC_DMA_R_PTSA_MAX 0xe6c
|
|
#define MC_ROC_DMA_R_PTSA_RATE 0xe70
|
|
#define MC_RING1_WR_B_PTSA_MIN 0xe74
|
|
#define MC_RING1_WR_B_PTSA_MAX 0xe78
|
|
#define MC_RING1_WR_B_PTSA_RATE 0xe7c
|
|
#define MC_RING1_WR_NB_PTSA_MIN 0xe80
|
|
#define MC_RING1_WR_NB_PTSA_MAX 0xe84
|
|
#define MC_RING1_WR_NB_PTSA_RATE 0xe88
|
|
#define MC_RING1_RD_B_PTSA_MIN 0xe8c
|
|
#define MC_RING1_RD_B_PTSA_MAX 0xe90
|
|
#define MC_RING1_RD_B_PTSA_RATE 0xe94
|
|
#define MC_RING1_RD_NB_PTSA_MIN 0xe98
|
|
#define MC_RING1_RD_NB_PTSA_MAX 0xe9c
|
|
#define MC_RING1_RD_NB_PTSA_RATE 0xea0
|
|
#define MC_FREE_BANK_QUEUES 0xea4
|
|
#define MC_RING0_MT_FIFO_CREDITS 0xea8
|
|
#define MC_LATENCY_ALLOWANCE_ROC_DMA_R_0 0xeac
|
|
#define MC_LATENCY_ALLOWANCE_CIFLL_WR_0 0x1100
|
|
#define MC_CIFLL_NISO_PTSA_MIN 0x1104
|
|
#define MC_CIFLL_NISO_PTSA_MAX 0x1108
|
|
#define MC_CIFLL_NISO_PTSA_RATE 0x110c
|
|
#define MC_CIFLL_SISO_PTSA_MIN 0x1110
|
|
#define MC_CIFLL_SISO_PTSA_MAX 0x1114
|
|
#define MC_CIFLL_SISO_PTSA_RATE 0x1118
|
|
#define MC_CIFLL_ISO_PTSA_MIN 0x111c
|
|
#define MC_CIFLL_ISO_PTSA_MAX 0x1120
|
|
#define MC_CIFLL_ISO_PTSA_RATE 0x1124
|
|
#define MC_CIFLL_RING0X_PTSA_MIN 0x1128
|
|
#define MC_CIFLL_RING0X_PTSA_MAX 0x112c
|
|
#define MC_CIFLL_RING0X_PTSA_RATE 0x1130
|
|
#define MC_CIFLL_CPU_RD_PRI_CTRL 0x1174
|
|
#define MC_MEM_SCRUBBER_ECC_ADDR 0xf18
|
|
#define MC_MEM_SCRUBBER_ECC_ADDR_HI 0xf1c
|
|
#define MC_MEM_SCRUBBER_ECC_REG_CTRL 0xf20
|
|
#define MC_CONFIG_TSA_SINGLE_ARB_ENABLE 0xfe8
|
|
#define MC_DBB_RINGFENCE_CTRL 0xfec
|
|
#define MC_DBB_RINGFENCE_STATUS 0xff0
|
|
#define MC_CCITRX_ENABLE_CONFIG 0xf3c
|
|
#define MC_CCI_WR_LATENCY_ALLOWANCE_CONFIG 0xf40
|
|
#define MC_EMEM_ARB_THROTTLE_CFG 0xf44
|
|
#define MC_MSS_SYSRAM_EC_FEATURE 0x9000
|
|
#define MC_MSS_SYSRAM_EC_SWRESET 0x9004
|
|
#define MC_MSS_SYSRAM_EC_MISSIONERR_TYPE 0x9008
|
|
#define MC_MSS_SYSRAM_EC_CURRENT_COUNTER_VALUE 0x900c
|
|
#define MC_MSS_SYSRAM_EC_MISSIONERR_USERVALUE 0x9010
|
|
#define MC_MSS_SYSRAM_EC_MISSIONERR_INDEX 0x9014
|
|
#define MC_MSS_SYSRAM_EC_CORRECTABLE_THRESHOLD 0x9018
|
|
#define MC_MSS_SYSRAM_EC_MISSIONERR_INJECT_UNLOCK 0x901c
|
|
#define MC_MSS_SYSRAM_EC_ERRSLICE0_MISSIONERR_ENABLE 0x9030
|
|
#define MC_MSS_SYSRAM_EC_ERRSLICE0_MISSIONERR_FORCE 0x9034
|
|
#define MC_MSS_SYSRAM_EC_ERRSLICE0_MISSIONERR_STATUS 0x9038
|
|
#define MC_MSS_SYSRAM_EC_ERRSLICE0_MISSIONERR_INJECT 0x903c
|
|
#define MC_MSS_SYSRAM_EC_ERRSLICE0_LATENTERR_ENABLE 0x9040
|
|
#define MC_MSS_SYSRAM_EC_ERRSLICE0_LATENTERR_FORCE 0x9044
|
|
#define MC_MSS_SYSRAM_EC_ERRSLICE0_LATENTERR_STATUS 0x9048
|
|
#define MC_MSS_SYSRAM_EC_ERRSLICE0_COUNTER_RELOAD 0x9050
|
|
#define MC_TCU_WRAP_EC_FEATURE 0x9100
|
|
#define MC_TCU_WRAP_EC_SWRESET 0x9104
|
|
#define MC_TCU_WRAP_EC_MISSIONERR_TYPE 0x9108
|
|
#define MC_TCU_WRAP_EC_CURRENT_COUNTER_VALUE 0x910c
|
|
#define MC_TCU_WRAP_EC_MISSIONERR_USERVALUE 0x9110
|
|
#define MC_TCU_WRAP_EC_MISSIONERR_INDEX 0x9114
|
|
#define MC_TCU_WRAP_EC_CORRECTABLE_THRESHOLD 0x9118
|
|
#define MC_TCU_WRAP_EC_MISSIONERR_INJECT_UNLOCK 0x911c
|
|
#define MC_TCU_WRAP_EC_ERRSLICE0_MISSIONERR_ENABLE 0x9130
|
|
#define MC_TCU_WRAP_EC_ERRSLICE0_MISSIONERR_FORCE 0x9134
|
|
#define MC_TCU_WRAP_EC_ERRSLICE0_MISSIONERR_STATUS 0x9138
|
|
#define MC_TCU_WRAP_EC_ERRSLICE0_MISSIONERR_INJECT 0x913c
|
|
#define MC_TCU_WRAP_EC_ERRSLICE0_LATENTERR_ENABLE 0x9140
|
|
#define MC_TCU_WRAP_EC_ERRSLICE0_LATENTERR_FORCE 0x9144
|
|
#define MC_TCU_WRAP_EC_ERRSLICE0_LATENTERR_STATUS 0x9148
|
|
#define MC_TCU_WRAP_EC_ERRSLICE0_COUNTER_RELOAD 0x9150
|
|
#define MC_TCU_WRAP_EC_ERRSLICE1_MISSIONERR_ENABLE 0x9160
|
|
#define MC_TCU_WRAP_EC_ERRSLICE1_MISSIONERR_FORCE 0x9164
|
|
#define MC_TCU_WRAP_EC_ERRSLICE1_MISSIONERR_STATUS 0x9168
|
|
#define MC_TCU_WRAP_EC_ERRSLICE1_MISSIONERR_INJECT 0x916c
|
|
#define MC_TCU_WRAP_EC_ERRSLICE1_LATENTERR_ENABLE 0x9170
|
|
#define MC_TCU_WRAP_EC_ERRSLICE1_LATENTERR_FORCE 0x9174
|
|
#define MC_TCU_WRAP_EC_ERRSLICE1_LATENTERR_STATUS 0x9178
|
|
#define MC_TCU_WRAP_EC_ERRSLICE1_COUNTER_RELOAD 0x9180
|
|
#define MC_MSS_SBS_EC_FEATURE 0x9200
|
|
#define MC_MSS_SBS_EC_SWRESET 0x9204
|
|
#define MC_MSS_SBS_EC_MISSIONERR_TYPE 0x9208
|
|
#define MC_MSS_SBS_EC_CURRENT_COUNTER_VALUE 0x920c
|
|
#define MC_MSS_SBS_EC_MISSIONERR_USERVALUE 0x9210
|
|
#define MC_MSS_SBS_EC_MISSIONERR_INDEX 0x9214
|
|
#define MC_MSS_SBS_EC_CORRECTABLE_THRESHOLD 0x9218
|
|
#define MC_MSS_SBS_EC_MISSIONERR_INJECT_UNLOCK 0x921c
|
|
#define MC_MSS_SBS_EC_ERRSLICE0_MISSIONERR_ENABLE 0x9230
|
|
#define MC_MSS_SBS_EC_ERRSLICE0_MISSIONERR_FORCE 0x9234
|
|
#define MC_MSS_SBS_EC_ERRSLICE0_MISSIONERR_STATUS 0x9238
|
|
#define MC_MSS_SBS_EC_ERRSLICE0_MISSIONERR_INJECT 0x923c
|
|
#define MC_MSS_SBS_EC_ERRSLICE0_LATENTERR_ENABLE 0x9240
|
|
#define MC_MSS_SBS_EC_ERRSLICE0_LATENTERR_FORCE 0x9244
|
|
#define MC_MSS_SBS_EC_ERRSLICE0_LATENTERR_STATUS 0x9248
|
|
#define MC_MSS_SBS_EC_ERRSLICE0_COUNTER_RELOAD 0x9250
|
|
#define MC_MCF_SLICE_EC_FEATURE 0x9300
|
|
#define MC_MCF_SLICE_EC_SWRESET 0x9304
|
|
#define MC_MCF_SLICE_EC_MISSIONERR_TYPE 0x9308
|
|
#define MC_MCF_SLICE_EC_CURRENT_COUNTER_VALUE 0x930c
|
|
#define MC_MCF_SLICE_EC_MISSIONERR_USERVALUE 0x9310
|
|
#define MC_MCF_SLICE_EC_MISSIONERR_INDEX 0x9314
|
|
#define MC_MCF_SLICE_EC_CORRECTABLE_THRESHOLD 0x9318
|
|
#define MC_MCF_SLICE_EC_MISSIONERR_INJECT_UNLOCK 0x931c
|
|
#define MC_MCF_SLICE_EC_ERRSLICE0_MISSIONERR_ENABLE 0x9330
|
|
#define MC_MCF_SLICE_EC_ERRSLICE0_MISSIONERR_FORCE 0x9334
|
|
#define MC_MCF_SLICE_EC_ERRSLICE0_MISSIONERR_STATUS 0x9338
|
|
#define MC_MCF_SLICE_EC_ERRSLICE0_MISSIONERR_INJECT 0x933c
|
|
#define MC_MCF_SLICE_EC_ERRSLICE0_LATENTERR_ENABLE 0x9340
|
|
#define MC_MCF_SLICE_EC_ERRSLICE0_LATENTERR_FORCE 0x9344
|
|
#define MC_MCF_SLICE_EC_ERRSLICE0_LATENTERR_STATUS 0x9348
|
|
#define MC_MCF_SLICE_EC_ERRSLICE0_COUNTER_RELOAD 0x9350
|
|
#define MC_MCF_IREQX_EC_FEATURE 0x9400
|
|
#define MC_MCF_IREQX_EC_SWRESET 0x9404
|
|
#define MC_MCF_IREQX_EC_MISSIONERR_TYPE 0x9408
|
|
#define MC_MCF_IREQX_EC_CURRENT_COUNTER_VALUE 0x940c
|
|
#define MC_MCF_IREQX_EC_MISSIONERR_INDEX 0x9414
|
|
#define MC_MCF_IREQX_EC_CORRECTABLE_THRESHOLD 0x9418
|
|
#define MC_MCF_IREQX_EC_MISSIONERR_INJECT_UNLOCK 0x941c
|
|
#define MC_MCF_IREQX_EC_ERRSLICE0_MISSIONERR_ENABLE 0x9430
|
|
#define MC_MCF_IREQX_EC_ERRSLICE0_MISSIONERR_FORCE 0x9434
|
|
#define MC_MCF_IREQX_EC_ERRSLICE0_MISSIONERR_STATUS 0x9438
|
|
#define MC_MCF_IREQX_EC_ERRSLICE0_MISSIONERR_INJECT 0x943c
|
|
#define MC_MCF_IREQX_EC_ERRSLICE0_LATENTERR_ENABLE 0x9440
|
|
#define MC_MCF_IREQX_EC_ERRSLICE0_LATENTERR_FORCE 0x9444
|
|
#define MC_MCF_IREQX_EC_ERRSLICE0_LATENTERR_STATUS 0x9448
|
|
#define MC_MCF_IREQX_EC_ERRSLICE0_COUNTER_RELOAD 0x9450
|
|
#define MC_MCF_IRSPX_EC_FEATURE 0x9500
|
|
#define MC_MCF_IRSPX_EC_SWRESET 0x9504
|
|
#define MC_MCF_IRSPX_EC_MISSIONERR_TYPE 0x9508
|
|
#define MC_MCF_IRSPX_EC_CURRENT_COUNTER_VALUE 0x950c
|
|
#define MC_MCF_IRSPX_EC_MISSIONERR_USERVALUE 0x9510
|
|
#define MC_MCF_IRSPX_EC_MISSIONERR_INDEX 0x9514
|
|
#define MC_MCF_IRSPX_EC_CORRECTABLE_THRESHOLD 0x9518
|
|
#define MC_MCF_IRSPX_EC_MISSIONERR_INJECT_UNLOCK 0x951c
|
|
#define MC_MCF_IRSPX_EC_ERRSLICE0_MISSIONERR_ENABLE 0x9530
|
|
#define MC_MCF_IRSPX_EC_ERRSLICE0_MISSIONERR_FORCE 0x9534
|
|
#define MC_MCF_IRSPX_EC_ERRSLICE0_MISSIONERR_STATUS 0x9538
|
|
#define MC_MCF_IRSPX_EC_ERRSLICE0_MISSIONERR_INJECT 0x953c
|
|
#define MC_MCF_IRSPX_EC_ERRSLICE0_LATENTERR_ENABLE 0x9540
|
|
#define MC_MCF_IRSPX_EC_ERRSLICE0_LATENTERR_FORCE 0x9544
|
|
#define MC_MCF_IRSPX_EC_ERRSLICE0_LATENTERR_STATUS 0x9548
|
|
#define MC_MCF_IRSPX_EC_ERRSLICE0_COUNTER_RELOAD 0x9550
|
|
#define MC_MCF_OREQX_EC_FEATURE 0x9600
|
|
#define MC_MCF_OREQX_EC_SWRESET 0x9604
|
|
#define MC_MCF_OREQX_EC_MISSIONERR_TYPE 0x9608
|
|
#define MC_MCF_OREQX_EC_CURRENT_COUNTER_VALUE 0x960c
|
|
#define MC_MCF_OREQX_EC_MISSIONERR_USERVALUE 0x9610
|
|
#define MC_MCF_OREQX_EC_MISSIONERR_INDEX 0x9614
|
|
#define MC_MCF_OREQX_EC_CORRECTABLE_THRESHOLD 0x9618
|
|
#define MC_MCF_OREQX_EC_MISSIONERR_INJECT_UNLOCK 0x961c
|
|
#define MC_MCF_OREQX_EC_ERRSLICE0_MISSIONERR_ENABLE 0x9630
|
|
#define MC_MCF_OREQX_EC_ERRSLICE0_MISSIONERR_FORCE 0x9634
|
|
#define MC_MCF_OREQX_EC_ERRSLICE0_MISSIONERR_STATUS 0x9638
|
|
#define MC_MCF_OREQX_EC_ERRSLICE0_MISSIONERR_INJECT 0x963c
|
|
#define MC_MCF_OREQX_EC_ERRSLICE0_LATENTERR_ENABLE 0x9640
|
|
#define MC_MCF_OREQX_EC_ERRSLICE0_LATENTERR_FORCE 0x9644
|
|
#define MC_MCF_OREQX_EC_ERRSLICE0_LATENTERR_STATUS 0x9648
|
|
#define MC_MCF_OREQX_EC_ERRSLICE0_COUNTER_RELOAD 0x9650
|
|
#define MC_MCF_OREQX_EC_ERRSLICE1_MISSIONERR_ENABLE 0x9660
|
|
#define MC_MCF_OREQX_EC_ERRSLICE1_MISSIONERR_FORCE 0x9664
|
|
#define MC_MCF_OREQX_EC_ERRSLICE1_MISSIONERR_STATUS 0x9668
|
|
#define MC_MCF_OREQX_EC_ERRSLICE1_MISSIONERR_INJECT 0x966c
|
|
#define MC_MCF_OREQX_EC_ERRSLICE1_LATENTERR_ENABLE 0x9670
|
|
#define MC_MCF_OREQX_EC_ERRSLICE1_LATENTERR_FORCE 0x9674
|
|
#define MC_MCF_OREQX_EC_ERRSLICE1_LATENTERR_STATUS 0x9678
|
|
#define MC_MCF_OREQX_EC_ERRSLICE1_COUNTER_RELOAD 0x9680
|
|
#define MC_MCF_ORSPX_EC_FEATURE 0x9700
|
|
#define MC_MCF_ORSPX_EC_SWRESET 0x9704
|
|
#define MC_MCF_ORSPX_EC_MISSIONERR_TYPE 0x9708
|
|
#define MC_MCF_ORSPX_EC_CURRENT_COUNTER_VALUE 0x970c
|
|
#define MC_MCF_ORSPX_EC_MISSIONERR_INDEX 0x9714
|
|
#define MC_MCF_ORSPX_EC_CORRECTABLE_THRESHOLD 0x9718
|
|
#define MC_MCF_ORSPX_EC_MISSIONERR_INJECT_UNLOCK 0x971c
|
|
#define MC_MCF_ORSPX_EC_ERRSLICE0_MISSIONERR_ENABLE 0x9730
|
|
#define MC_MCF_ORSPX_EC_ERRSLICE0_MISSIONERR_FORCE 0x9734
|
|
#define MC_MCF_ORSPX_EC_ERRSLICE0_MISSIONERR_STATUS 0x9738
|
|
#define MC_MCF_ORSPX_EC_ERRSLICE0_MISSIONERR_INJECT 0x973c
|
|
#define MC_MCF_ORSPX_EC_ERRSLICE0_LATENTERR_ENABLE 0x9740
|
|
#define MC_MCF_ORSPX_EC_ERRSLICE0_LATENTERR_FORCE 0x9744
|
|
#define MC_MCF_ORSPX_EC_ERRSLICE0_LATENTERR_STATUS 0x9748
|
|
#define MC_MCF_ORSPX_EC_ERRSLICE0_COUNTER_RELOAD 0x9750
|
|
#define MC_CHANNEL_EC_FEATURE 0x9800
|
|
#define MC_CHANNEL_EC_SWRESET 0x9804
|
|
#define MC_CHANNEL_EC_MISSIONERR_TYPE 0x9808
|
|
#define MC_CHANNEL_EC_CURRENT_COUNTER_VALUE 0x980c
|
|
#define MC_CHANNEL_EC_MISSIONERR_USERVALUE 0x9810
|
|
#define MC_CHANNEL_EC_MISSIONERR_INDEX 0x9814
|
|
#define MC_CHANNEL_EC_CORRECTABLE_THRESHOLD 0x9818
|
|
#define MC_CHANNEL_EC_MISSIONERR_INJECT_UNLOCK 0x981c
|
|
#define MC_CHANNEL_EC_ERRSLICE0_MISSIONERR_ENABLE 0x9830
|
|
#define MC_CHANNEL_EC_ERRSLICE0_MISSIONERR_FORCE 0x9834
|
|
#define MC_CHANNEL_EC_ERRSLICE0_MISSIONERR_STATUS 0x9838
|
|
#define MC_CHANNEL_EC_ERRSLICE0_MISSIONERR_INJECT 0x983c
|
|
#define MC_CHANNEL_EC_ERRSLICE0_LATENTERR_ENABLE 0x9840
|
|
#define MC_CHANNEL_EC_ERRSLICE0_LATENTERR_FORCE 0x9844
|
|
#define MC_CHANNEL_EC_ERRSLICE0_LATENTERR_STATUS 0x9848
|
|
#define MC_CHANNEL_EC_ERRSLICE0_COUNTER_RELOAD 0x9850
|
|
#define MC_CHANNEL_EC_ERRSLICE1_MISSIONERR_ENABLE 0x9860
|
|
#define MC_CHANNEL_EC_ERRSLICE1_MISSIONERR_FORCE 0x9864
|
|
#define MC_CHANNEL_EC_ERRSLICE1_MISSIONERR_STATUS 0x9868
|
|
#define MC_CHANNEL_EC_ERRSLICE1_MISSIONERR_INJECT 0x986c
|
|
#define MC_CHANNEL_EC_ERRSLICE1_LATENTERR_ENABLE 0x9870
|
|
#define MC_CHANNEL_EC_ERRSLICE1_LATENTERR_FORCE 0x9874
|
|
#define MC_CHANNEL_EC_ERRSLICE1_LATENTERR_STATUS 0x9878
|
|
#define MC_CHANNEL_EC_ERRSLICE1_COUNTER_RELOAD 0x9880
|
|
#define MC_HUB_EC_FEATURE 0x9900
|
|
#define MC_HUB_EC_SWRESET 0x9904
|
|
#define MC_HUB_EC_MISSIONERR_TYPE 0x9908
|
|
#define MC_HUB_EC_CURRENT_COUNTER_VALUE 0x990c
|
|
#define MC_HUB_EC_MISSIONERR_USERVALUE 0x9910
|
|
#define MC_HUB_EC_MISSIONERR_INDEX 0x9914
|
|
#define MC_HUB_EC_CORRECTABLE_THRESHOLD 0x9918
|
|
#define MC_HUB_EC_MISSIONERR_INJECT_UNLOCK 0x991c
|
|
#define MC_HUB_EC_ERRSLICE0_MISSIONERR_ENABLE 0x9930
|
|
#define MC_HUB_EC_ERRSLICE0_MISSIONERR_FORCE 0x9934
|
|
#define MC_HUB_EC_ERRSLICE0_MISSIONERR_STATUS 0x9938
|
|
#define MC_HUB_EC_ERRSLICE0_MISSIONERR_INJECT 0x993c
|
|
#define MC_HUB_EC_ERRSLICE0_LATENTERR_ENABLE 0x9940
|
|
#define MC_HUB_EC_ERRSLICE0_LATENTERR_FORCE 0x9944
|
|
#define MC_HUB_EC_ERRSLICE0_LATENTERR_STATUS 0x9948
|
|
#define MC_HUB_EC_ERRSLICE0_COUNTER_RELOAD 0x9950
|
|
#define MC_HUBC_EC_FEATURE 0x9a00
|
|
#define MC_HUBC_EC_SWRESET 0x9a04
|
|
#define MC_HUBC_EC_MISSIONERR_TYPE 0x9a08
|
|
#define MC_HUBC_EC_CURRENT_COUNTER_VALUE 0x9a0c
|
|
#define MC_HUBC_EC_MISSIONERR_USERVALUE 0x9a10
|
|
#define MC_HUBC_EC_MISSIONERR_INDEX 0x9a14
|
|
#define MC_HUBC_EC_CORRECTABLE_THRESHOLD 0x9a18
|
|
#define MC_HUBC_EC_MISSIONERR_INJECT_UNLOCK 0x9a1c
|
|
#define MC_HUBC_EC_ERRSLICE0_MISSIONERR_ENABLE 0x9a30
|
|
#define MC_HUBC_EC_ERRSLICE0_MISSIONERR_FORCE 0x9a34
|
|
#define MC_HUBC_EC_ERRSLICE0_MISSIONERR_STATUS 0x9a38
|
|
#define MC_HUBC_EC_ERRSLICE0_MISSIONERR_INJECT 0x9a3c
|
|
#define MC_HUBC_EC_ERRSLICE0_LATENTERR_ENABLE 0x9a40
|
|
#define MC_HUBC_EC_ERRSLICE0_LATENTERR_FORCE 0x9a44
|
|
#define MC_HUBC_EC_ERRSLICE0_LATENTERR_STATUS 0x9a48
|
|
#define MC_HUBC_EC_ERRSLICE0_COUNTER_RELOAD 0x9a50
|
|
|
|
#endif
|