575 lines
19 KiB
C
575 lines
19 KiB
C
/*
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* include/linux/platform/tegra12_emc.h
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*
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* Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#ifndef _MACH_TEGRA_TEGRA12_EMC_H
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#define _MACH_TEGRA_TEGRA12_EMC_H
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#include <linux/platform/tegra/tegra_emc.h>
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#include <linux/platform_data/tegra_emc_pdata.h>
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int tegra12_emc_init(void);
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enum {
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DRAM_DEV_SEL_ALL = 0,
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DRAM_DEV_SEL_0 = (2 << 30),
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DRAM_DEV_SEL_1 = (1 << 30),
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};
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void tegra12_mc_holdoff_enable(void);
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#define DRAM_BROADCAST(num) \
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(((num) > 1) ? DRAM_DEV_SEL_ALL : DRAM_DEV_SEL_0)
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#define EMC_INTSTATUS 0x0
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#define EMC_INTSTATUS_CLKCHANGE_COMPLETE (0x1 << 4)
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#define EMC_DBG 0x8
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#define EMC_DBG_WRITE_MUX_ACTIVE (0x1 << 1)
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#define EMC_CFG 0xc
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#define EMC_CFG_DRAM_CLKSTOP_PD (0x1 << 31)
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#define EMC_CFG_DRAM_CLKSTOP_SR (0x1 << 30)
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#define EMC_CFG_DRAM_ACPD (0x1 << 29)
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#define EMC_CFG_DYN_SREF (0x1 << 28)
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#define EMC_CFG_PWR_MASK ((0xF << 28) | (0x1 << 18))
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#define EMC_CFG_REQACT_ASYNC (0x1 << 26)
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#define EMC_CFG_AUTO_PRE_WR (0x1 << 25)
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#define EMC_CFG_AUTO_PRE_RD (0x1 << 24)
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#define EMC_CFG_MAM_PRE_WR (0x1 << 23)
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#define EMC_CFG_MAN_PRE_RD (0x1 << 22)
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#define EMC_CFG_PERIODIC_QRST (0x1 << 21)
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#define EMC_CFG_EN_DYNAMIC_PUTERM (0x1 << 20)
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#define EMC_CFG_DLY_WR_DQ_HALF_CLOCK (0x1 << 19)
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#define EMC_CFG_DSR_VTTGEN_DRV_EN (0x1 << 18)
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#define EMC_CFG_EMC2MC_CLK_RATIO (0x3 << 16)
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#define EMC_CFG_WAIT_FOR_ISP2B_READY_B4_CC (0x1 << 9)
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#define EMC_CFG_WAIT_FOR_VI2_READY_B4_CC (0x1 << 8)
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#define EMC_CFG_WAIT_FOR_ISP2_READY_B4_CC (0x1 << 7)
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#define EMC_CFG_INVERT_DQM (0x1 << 6)
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#define EMC_CFG_WAIT_FOR_DISPLAYB_READY_B4_CC (0x1 << 5)
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#define EMC_CFG_WAIT_FOR_DISPLAY_READY_B4_CC (0x1 << 4)
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#define EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE2 (0x1 << 3)
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#define EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE1 (0x1 << 2)
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#define EMC_CFG_EMC2PMACRO_CFG_BYPASS_ADDRPIPE (0x1 << 1)
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#define EMC_ADR_CFG 0x10
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#define EMC_REFCTRL 0x20
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#define EMC_REFCTRL_DEV_SEL_SHIFT 0
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#define EMC_REFCTRL_DEV_SEL_MASK \
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(0x3 << EMC_REFCTRL_DEV_SEL_SHIFT)
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#define EMC_REFCTRL_ENABLE (0x1 << 31)
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#define EMC_REFCTRL_ENABLE_ALL(num) \
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(((((num) > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT) \
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| EMC_REFCTRL_ENABLE)
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#define EMC_REFCTRL_DISABLE_ALL(num) \
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((((num) > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT)
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#define EMC_TIMING_CONTROL 0x28
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#define EMC_RC 0x2c
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#define EMC_RFC 0x30
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#define EMC_RAS 0x34
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#define EMC_RP 0x38
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#define EMC_R2W 0x3c
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#define EMC_W2R 0x40
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#define EMC_R2P 0x44
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#define EMC_W2P 0x48
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#define EMC_RD_RCD 0x4c
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#define EMC_WR_RCD 0x50
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#define EMC_RRD 0x54
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#define EMC_REXT 0x58
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#define EMC_WDV 0x5c
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#define EMC_QUSE 0x60
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#define EMC_QRST 0x64
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#define EMC_QSAFE 0x68
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#define EMC_RDV 0x6c
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#define EMC_REFRESH 0x70
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#define EMC_BURST_REFRESH_NUM 0x74
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#define EMC_PDEX2WR 0x78
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#define EMC_PDEX2RD 0x7c
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#define EMC_PCHG2PDEN 0x80
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#define EMC_ACT2PDEN 0x84
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#define EMC_AR2PDEN 0x88
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#define EMC_RW2PDEN 0x8c
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#define EMC_TXSR 0x90
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#define EMC_TCKE 0x94
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#define EMC_TFAW 0x98
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#define EMC_TRPAB 0x9c
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#define EMC_TCLKSTABLE 0xa0
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#define EMC_TCLKSTOP 0xa4
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#define EMC_TREFBW 0xa8
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#define EMC_ODT_WRITE 0xb0
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#define EMC_ODT_READ 0xb4
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#define EMC_WEXT 0xb8
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#define EMC_CTT 0xbc
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#define EMC_RFC_SLR 0xc0
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#define EMC_MRS_WAIT_CNT2 0xc4
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#define EMC_MRS_WAIT_CNT 0xc8
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#define EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT 0
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#define EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK \
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(0x3FF << EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT)
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#define EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT 16
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#define EMC_MRS_WAIT_CNT_LONG_WAIT_MASK \
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(0x3FF << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT)
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#define EMC_MRS 0xcc
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#define EMC_MODE_SET_DLL_RESET (0x1 << 8)
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#define EMC_MODE_SET_LONG_CNT (0x1 << 26)
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#define EMC_EMRS 0xd0
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#define EMC_REF 0xd4
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#define EMC_REF_FORCE_CMD 1
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#define EMC_PRE 0xd8
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#define EMC_NOP 0xdc
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#define EMC_SELF_REF 0xe0
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#define EMC_SELF_REF_CMD_ENABLED (0x1 << 0)
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#define EMC_SELF_REF_DEV_SEL_SHIFT 30
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#define EMC_SELF_REF_DEV_SEL_MASK \
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(0x3 << EMC_SELF_REF_DEV_SEL_SHIFT)
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#define EMC_DPD 0xe4
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#define EMC_MRW 0xe8
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#define EMC_MRR 0xec
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#define EMC_MRR_DEV_SEL_SHIFT 30
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#define EMC_MRR_DEV_SEL_MASK \
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(0x3 << EMC_SELF_REF_DEV_SEL_SHIFT)
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#define EMC_MRR_MA_SHIFT 16
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#define EMC_MRR_MA_MASK (0xFF << EMC_MRR_MA_SHIFT)
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#define EMC_MRR_DATA_MASK ((0x1 << EMC_MRR_MA_SHIFT) - 1)
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#define LPDDR2_MR4_TEMP_SHIFT 0
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#define LPDDR2_MR4_TEMP_MASK (0x7 << LPDDR2_MR4_TEMP_SHIFT)
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#define EMC_CMDQ 0xf0
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#define EMC_MC2EMCQ 0xf4
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#define EMC_XM2DQSPADCTRL3 0xf8
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#define EMC_XM2DQSPADCTRL3_VREF_ENABLE (0x1 << 5)
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#define EMC_FBIO_SPARE 0x100
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#define EMC_FBIO_CFG5 0x104
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#define EMC_CFG5_TYPE_SHIFT 0x0
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#define EMC_CFG5_TYPE_MASK (0x3 << EMC_CFG5_TYPE_SHIFT)
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#define EMC_CFG5_QUSE_MODE_SHIFT 13
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#define EMC_CFG5_QUSE_MODE_MASK \
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(0x7 << EMC_CFG5_QUSE_MODE_SHIFT)
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enum {
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EMC_CFG5_QUSE_MODE_NORMAL = 0,
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EMC_CFG5_QUSE_MODE_ALWAYS_ON,
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EMC_CFG5_QUSE_MODE_INTERNAL_LPBK,
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EMC_CFG5_QUSE_MODE_PULSE_INTERN,
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EMC_CFG5_QUSE_MODE_PULSE_EXTERN,
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EMC_CFG5_QUSE_MODE_DIRECT_QUSE,
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};
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#define EMC_FBIO_WRPTR_EQ_2 0x108
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#define EMC_FBIO_CFG6 0x114
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#define EMC_CFG_RSV 0x120
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#define EMC_ACPD_CONTROL 0x124
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#define EMC_EMRS2 0x12c
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#define EMC_EMRS3 0x130
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#define EMC_MRW2 0x134
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#define EMC_MRW3 0x138
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#define EMC_MRW4 0x13c
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#define EMC_CLKEN_OVERRIDE 0x140
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#define EMC_R2R 0x144
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#define EMC_W2W 0x148
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#define EMC_EINPUT 0x14c
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#define EMC_EINPUT_DURATION 0x150
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#define EMC_PUTERM_EXTRA 0x154
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#define EMC_TCKESR 0x158
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#define EMC_TPD 0x15c
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#define EMC_AUTO_CAL_CONFIG 0x2a4
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#define EMC_AUTO_CAL_CONFIG_AUTO_CAL_START_SHIFT 31
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#define EMC_AUTO_CAL_INTERVAL 0x2a8
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#define EMC_AUTO_CAL_STATUS 0x2ac
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#define EMC_AUTO_CAL_STATUS_ACTIVE (0x1 << 31)
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#define EMC_AUTO_CAL_STATUS_SHIFT 31
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#define EMC_REQ_CTRL 0x2b0
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#define EMC_STATUS 0x2b4
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#define EMC_STATUS_TIMING_UPDATE_STALLED (0x1 << 23)
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#define EMC_STATUS_MRR_DIVLD (0x1 << 20)
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#define EMC_CFG_2 0x2b8
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#define EMC_CFG_2_MODE_SHIFT 0
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#define EMC_CFG_2_MODE_MASK (0x3 << EMC_CFG_2_MODE_SHIFT)
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#define EMC_CFG_2_SREF_MODE 0x1
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#define EMC_CFG_2_PD_MODE 0x3
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#define EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR (0x1 << 6)
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#define EMC_CFG_DIG_DLL 0x2bc
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#define EMC_CFG_DIG_DLL_PERIOD 0x2c0
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#define EMC_DIG_DLL_STATUS 0x2c8
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#define EMC_RDV_MASK 0x2cc
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#define EMC_WDV_MASK 0x2d0
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#define EMC_CTT_DURATION 0x2d8
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#define EMC_CTT_TERM_CTRL 0x2dc
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#define EMC_ZCAL_INTERVAL 0x2e0
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#define EMC_ZCAL_WAIT_CNT 0x2e4
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#define EMC_ZCAL_MRW_CMD 0x2e8
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#define EMC_ZQ_CAL 0x2ec
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#define EMC_ZQ_CAL_DEV_SEL_SHIFT 30
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#define EMC_ZQ_CAL_DEV_SEL_MASK \
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(0x3 << EMC_SELF_REF_DEV_SEL_SHIFT)
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#define EMC_ZQ_CAL_CMD (0x1 << 0)
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#define EMC_ZQ_CAL_LONG (0x1 << 4)
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#define EMC_ZQ_CAL_LONG_CMD_DEV0 \
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(DRAM_DEV_SEL_0 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
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#define EMC_ZQ_CAL_LONG_CMD_DEV1 \
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(DRAM_DEV_SEL_1 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
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#define EMC_XM2CMDPADCTRL 0x2f0
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#define EMC_XM2CMDPADCTRL2 0x2f4
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#define EMC_XM2DQSPADCTRL 0x2f8
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#define EMC_XM2DQSPADCTRL2 0x2fc
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#define EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE (0x1 << 0)
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#define EMC_XM2DQSPADCTRL2_VREF_ENABLE (0x1 << 5)
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#define EMC_XM2DQPADCTRL 0x300
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#define EMC_XM2DQPADCTRL2 0x304
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#define EMC_XM2CLKPADCTRL 0x308
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#define EMC_XM2COMPPADCTRL 0x30c
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#define EMC_XM2COMPPADCTRL_VREF_CAL_ENABLE (0x1 << 10)
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#define EMC_XM2VTTGENPADCTRL 0x310
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#define EMC_XM2VTTGENPADCTRL2 0x314
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#define EMC_XM2VTTGENPADCTRL3 0x318
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#define EMC_EMCPADEN 0x31c
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#define EMC_XM2DQSPADCTRL4 0x320
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#define EMC_SCRATCH0 0x324
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#define EMC_DLL_XFORM_DQS0 0x328
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#define EMC_DLL_XFORM_DQS1 0x32c
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#define EMC_DLL_XFORM_DQS2 0x330
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#define EMC_DLL_XFORM_DQS3 0x334
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#define EMC_DLL_XFORM_DQS4 0x338
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#define EMC_DLL_XFORM_DQS5 0x33c
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#define EMC_DLL_XFORM_DQS6 0x340
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#define EMC_DLL_XFORM_DQS7 0x344
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#define EMC_DLL_XFORM_QUSE0 0x348
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#define EMC_DLL_XFORM_QUSE1 0x34c
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#define EMC_DLL_XFORM_QUSE2 0x350
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#define EMC_DLL_XFORM_QUSE3 0x354
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#define EMC_DLL_XFORM_QUSE4 0x358
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#define EMC_DLL_XFORM_QUSE5 0x35c
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#define EMC_DLL_XFORM_QUSE6 0x360
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#define EMC_DLL_XFORM_QUSE7 0x364
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#define EMC_DLL_XFORM_DQ0 0x368
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#define EMC_DLL_XFORM_DQ1 0x36c
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#define EMC_DLL_XFORM_DQ2 0x370
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#define EMC_DLL_XFORM_DQ3 0x374
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#define EMC_DLI_RX_TRIM0 0x378
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#define EMC_DLI_RX_TRIM1 0x37c
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#define EMC_DLI_RX_TRIM2 0x380
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#define EMC_DLI_RX_TRIM3 0x384
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#define EMC_DLI_RX_TRIM4 0x388
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#define EMC_DLI_RX_TRIM5 0x38c
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#define EMC_DLI_RX_TRIM6 0x390
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#define EMC_DLI_RX_TRIM7 0x394
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#define EMC_DLI_TX_TRIM0 0x398
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#define EMC_DLI_TX_TRIM1 0x39c
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#define EMC_DLI_TX_TRIM2 0x3a0
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#define EMC_DLI_TX_TRIM3 0x3a4
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#define EMC_DLI_TRIM_TXDQS0 0x3a8
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#define EMC_DLI_TRIM_TXDQS1 0x3ac
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#define EMC_DLI_TRIM_TXDQS2 0x3b0
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#define EMC_DLI_TRIM_TXDQS3 0x3b4
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#define EMC_DLI_TRIM_TXDQS4 0x3b8
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#define EMC_DLI_TRIM_TXDQS5 0x3bc
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#define EMC_DLI_TRIM_TXDQS6 0x3c0
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#define EMC_DLI_TRIM_TXDQS7 0x3c4
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#define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE 0x3cc
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#define EMC_AUTO_CAL_CLK_STATUS 0x3d4
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#define EMC_SEL_DPD_CTRL 0x3d8
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#define EMC_SEL_DPD_CTRL_DATA_SEL_DPD (0x1 << 8)
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#define EMC_SEL_DPD_CTRL_ODT_SEL_DPD (0x1 << 5)
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#define EMC_SEL_DPD_CTRL_RESET_SEL_DPD (0x1 << 4)
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#define EMC_SEL_DPD_CTRL_CA_SEL_DPD (0x1 << 3)
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#define EMC_SEL_DPD_CTRL_CLK_SEL_DPD (0x1 << 2)
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#define EMC_SEL_DPD_CTRL_DDR3_MASK \
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((0xf << 2) | (0x1 << 8))
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#define EMC_SEL_DPD_CTRL_MASK \
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((0x3 << 2) | (0x1 << 5) | (0x1 << 8))
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#define EMC_PRE_REFRESH_REQ_CNT 0x3dc
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#define EMC_DYN_SELF_REF_CONTROL 0x3e0
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#define EMC_TXSRDLL 0x3e4
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#define EMC_CCFIFO_ADDR 0x3e8
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#define EMC_CCFIFO_DATA 0x3ec
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#define EMC_CCFIFO_STATUS 0x3f0
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#define EMC_CDB_CNTL_1 0x3f4
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#define EMC_CDB_CNTL_2 0x3f8
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#define EMC_XM2CLKPADCTRL2 0x3fc
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#define EMC_SWIZZLE_RANK0_BYTE_CFG 0x400
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#define EMC_SWIZZLE_RANK0_BYTE0 0x404
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#define EMC_SWIZZLE_RANK0_BYTE1 0x408
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#define EMC_SWIZZLE_RANK0_BYTE2 0x40c
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#define EMC_SWIZZLE_RANK0_BYTE3 0x410
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#define EMC_SWIZZLE_RANK1_BYTE_CFG 0x414
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#define EMC_SWIZZLE_RANK1_BYTE0 0x418
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#define EMC_SWIZZLE_RANK1_BYTE1 0x41c
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#define EMC_SWIZZLE_RANK1_BYTE2 0x420
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#define EMC_SWIZZLE_RANK1_BYTE3 0x424
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#define EMC_CA_TRAINING_START 0x428
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#define EMC_CA_TRAINING_BUSY 0x42c
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#define EMC_CA_TRAINING_CFG 0x430
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#define EMC_CA_TRAINING_TIMING_CNTL1 0x434
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#define EMC_CA_TRAINING_TIMING_CNTL2 0x438
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#define EMC_CA_TRAINING_CA_LEAD_IN 0x43c
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#define EMC_CA_TRAINING_CA 0x440
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#define EMC_CA_TRAINING_CA_LEAD_OUT 0x444
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#define EMC_CA_TRAINING_RESULT1 0x448
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#define EMC_CA_TRAINING_RESULT2 0x44c
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#define EMC_CA_TRAINING_RESULT3 0x450
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#define EMC_CA_TRAINING_RESULT4 0x454
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#define EMC_AUTO_CAL_CONFIG2 0x458
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#define EMC_AUTO_CAL_CONFIG3 0x45c
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#define EMC_AUTO_CAL_STATUS2 0x460
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#define EMC_XM2CMDPADCTRL3 0x464
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#define EMC_IBDLY 0x468
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#define EMC_DLL_XFORM_ADDR0 0x46c
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#define EMC_DLL_XFORM_ADDR1 0x470
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#define EMC_DLL_XFORM_ADDR2 0x474
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#define EMC_DLI_ADDR_TRIM 0x478
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#define EMC_DSR_VTTGEN_DRV 0x47c
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#define EMC_TXDSRVTTGEN 0x480
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#define EMC_XM2CMDPADCTRL4 0x484
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#define EMC_XM2CMDPADCTRL5 0x488
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#define EMC_DLL_XFORM_DQS8 0x4a0
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#define EMC_DLL_XFORM_DQS9 0x4a4
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#define EMC_DLL_XFORM_DQS10 0x4a8
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#define EMC_DLL_XFORM_DQS11 0x4ac
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#define EMC_DLL_XFORM_DQS12 0x4b0
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#define EMC_DLL_XFORM_DQS13 0x4b4
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#define EMC_DLL_XFORM_DQS14 0x4b8
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#define EMC_DLL_XFORM_DQS15 0x4bc
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#define EMC_DLL_XFORM_QUSE8 0x4c0
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#define EMC_DLL_XFORM_QUSE9 0x4c4
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#define EMC_DLL_XFORM_QUSE10 0x4c8
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#define EMC_DLL_XFORM_QUSE11 0x4cc
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#define EMC_DLL_XFORM_QUSE12 0x4d0
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#define EMC_DLL_XFORM_QUSE13 0x4d4
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#define EMC_DLL_XFORM_QUSE14 0x4d8
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#define EMC_DLL_XFORM_QUSE15 0x4dc
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#define EMC_DLL_XFORM_DQ4 0x4e0
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#define EMC_DLL_XFORM_DQ5 0x4e4
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#define EMC_DLL_XFORM_DQ6 0x4e8
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#define EMC_DLL_XFORM_DQ7 0x4ec
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#define EMC_DLI_TRIM_TXDQS8 0x520
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#define EMC_DLI_TRIM_TXDQS9 0x524
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#define EMC_DLI_TRIM_TXDQS10 0x528
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#define EMC_DLI_TRIM_TXDQS11 0x52c
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#define EMC_DLI_TRIM_TXDQS12 0x530
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#define EMC_DLI_TRIM_TXDQS13 0x534
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#define EMC_DLI_TRIM_TXDQS14 0x538
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#define EMC_DLI_TRIM_TXDQS15 0x53c
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#define EMC_CDB_CNTL_3 0x540
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#define EMC_XM2DQSPADCTRL5 0x544
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#define EMC_XM2DQSPADCTRL6 0x548
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#define EMC_XM2DQPADCTRL3 0x54c
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#define EMC_DLL_XFORM_ADDR3 0x550
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#define EMC_DLL_XFORM_ADDR4 0x554
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#define EMC_DLL_XFORM_ADDR5 0x558
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#define EMC_CFG_PIPE 0x560
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#define EMC_QPOP 0x564
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#define EMC_QUSE_WIDTH 0x568
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#define EMC_PUTERM_WIDTH 0x56c
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#define EMC_BGBIAS_CTL0 0x570
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#define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX_SHIFT 0x3
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#define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN_SHIFT 0x2
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#define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_SHIFT 0x1
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#define EMC_PUTERM_ADJ 0x574
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#define MC_EMEM_CFG 0x50
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#define MC_EMEM_ADR_CFG 0x54
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#define MC_EMEM_ADR_CFG_DEV0 0x58
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#define MC_EMEM_ADR_CFG_DEV1 0x5c
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#define MC_EMEM_ADR_CFG_BANK_MASK_0 0x64
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#define MC_EMEM_ADR_CFG_BANK_MASK_1 0x68
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#define MC_EMEM_ADR_CFG_BANK_MASK_2 0x6c
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#define MC_EMEM_ARB_CFG 0x90
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#define MC_EMEM_ARB_OUTSTANDING_REQ 0x94
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#define MC_EMEM_ARB_TIMING_RCD 0x98
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#define MC_EMEM_ARB_TIMING_RP 0x9c
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#define MC_EMEM_ARB_TIMING_RC 0xa0
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#define MC_EMEM_ARB_TIMING_RAS 0xa4
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#define MC_EMEM_ARB_TIMING_FAW 0xa8
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#define MC_EMEM_ARB_TIMING_RRD 0xac
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#define MC_EMEM_ARB_TIMING_RAP2PRE 0xb0
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#define MC_EMEM_ARB_TIMING_WAP2PRE 0xb4
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#define MC_EMEM_ARB_TIMING_R2R 0xb8
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#define MC_EMEM_ARB_TIMING_W2W 0xbc
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#define MC_EMEM_ARB_TIMING_R2W 0xc0
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#define MC_EMEM_ARB_TIMING_W2R 0xc4
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#define MC_EMEM_ARB_DA_TURNS 0xd0
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#define MC_EMEM_ARB_DA_COVERS 0xd4
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#define MC_EMEM_ARB_MISC0 0xd8
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#define MC_EMEM_ARB_MISC0_EMC_SAME_FREQ (0x1 << 27)
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#define MC_EMEM_ARB_MISC1 0xdc
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#define MC_EMEM_ARB_RING1_THROTTLE 0xe0
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#define MC_EMEM_ARB_RING3_THROTTLE 0xe4
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#define MC_EMEM_ARB_OVERRIDE 0xe8
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#define MC_EMEM_ARB_RSV 0xec
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#define MC_CLKEN_OVERRIDE 0xf4
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#define MC_TIMING_CONTROL_DBG 0xf8
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#define MC_TIMING_CONTROL 0xfc
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#define MC_EMEM_ARB_ISOCHRONOUS_0 0x208
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#define MC_EMEM_ARB_ISOCHRONOUS_1 0x20c
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#define MC_EMEM_ARB_ISOCHRONOUS_2 0x210
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#define MC_EMEM_ARB_HYSTERESIS_0_0 0x218
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#define MC_EMEM_ARB_HYSTERESIS_1_0 0x21c
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#define MC_EMEM_ARB_HYSTERESIS_2_0 0x220
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#define MC_EMEM_ARB_HYSTERESIS_3_0 0x224
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#define HYST_SATAR (0x1 << 31)
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#define HYST_PPCSAHBSLVR (0x1 << 30)
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#define HYST_PPCSAHBDMAR (0x1 << 29)
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#define HYST_MSENCSRD (0x1 << 28)
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#define HYST_HOST1XR (0x1 << 23)
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#define HYST_HOST1XDMAR (0x1 << 22)
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#define HYST_HDAR (0x1 << 21)
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#define HYST_DISPLAYHCB (0x1 << 17)
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#define HYST_DISPLAYHC (0x1 << 16)
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#define HYST_AVPCARM7R (0x1 << 15)
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#define HYST_AFIR (0x1 << 14)
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#define HYST_DISPLAY0CB (0x1 << 6)
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#define HYST_DISPLAY0C (0x1 << 5)
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#define HYST_DISPLAY0BB (0x1 << 4)
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#define HYST_DISPLAY0B (0x1 << 3)
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#define HYST_DISPLAY0AB (0x1 << 2)
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#define HYST_DISPLAY0A (0x1 << 1)
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#define HYST_PTCR (0x1 << 0)
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#define HYST_VDEDBGW (0x1 << 31)
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#define HYST_VDEBSEVW (0x1 << 30)
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#define HYST_SATAW (0x1 << 29)
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#define HYST_PPCSAHBSLVW (0x1 << 28)
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#define HYST_PPCSAHBDMAW (0x1 << 27)
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#define HYST_MPCOREW (0x1 << 25)
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#define HYST_MPCORELPW (0x1 << 24)
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#define HYST_HOST1XW (0x1 << 22)
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#define HYST_HDAW (0x1 << 21)
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#define HYST_AVPCARM7W (0x1 << 18)
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#define HYST_AFIW (0x1 << 17)
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#define HYST_MSENCSWR (0x1 << 11)
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#define HYST_MPCORER (0x1 << 7)
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#define HYST_MPCORELPR (0x1 << 6)
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#define HYST_VDETPER (0x1 << 5)
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#define HYST_VDEMCER (0x1 << 4)
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#define HYST_VDEMBER (0x1 << 3)
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#define HYST_VDEBSEVR (0x1 << 2)
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#define HYST_DISPLAYT (0x1 << 26)
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#define HYST_GPUSWR (0x1 << 25)
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#define HYST_GPUSRD (0x1 << 24)
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#define HYST_A9AVPSCW (0x1 << 23)
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#define HYST_A9AVPSCR (0x1 << 22)
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#define HYST_TSECSWR (0x1 << 21)
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#define HYST_TSECSRD (0x1 << 20)
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#define HYST_ISPWBB (0x1 << 17)
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#define HYST_ISPWAB (0x1 << 16)
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#define HYST_ISPRAB (0x1 << 14)
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#define HYST_XUSB_DEVW (0x1 << 13)
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#define HYST_XUSB_DEVR (0x1 << 12)
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#define HYST_XUSB_HOSTW (0x1 << 11)
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#define HYST_XUSB_HOSTR (0x1 << 10)
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#define HYST_ISPWB (0x1 << 7)
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#define HYST_ISPWA (0x1 << 6)
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#define HYST_ISPRA (0x1 << 4)
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#define HYST_VDETPMW (0x1 << 1)
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#define HYST_VDEMBEW (0x1 << 0)
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#define HYST_DISPLAYD (0x1 << 19)
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#define HYST_VIW (0x1 << 18)
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#define HYST_VICSWR (0x1 << 13)
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#define HYST_VICSRD (0x1 << 12)
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#define HYST_SDMMCWAB (0x1 << 7)
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#define HYST_SDMMCW (0x1 << 6)
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#define HYST_SDMMCWAA (0x1 << 5)
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#define HYST_SDMMCWA (0x1 << 4)
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#define HYST_SDMMCRAB (0x1 << 3)
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#define HYST_SDMMCR (0x1 << 2)
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#define HYST_SDMMCRAA (0x1 << 1)
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#define HYST_SDMMCRA (0x1 << 0)
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#define MC_DIS_EXTRA_SNAP_LEVELS 0x2ac
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#define MC_LATENCY_ALLOWANCE_AFI_0 0x2e0
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#define MC_LATENCY_ALLOWANCE_AVPC_0 0x2e4
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#define MC_LATENCY_ALLOWANCE_DC_0 0x2e8
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#define MC_LATENCY_ALLOWANCE_DC_1 0x2ec
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#define MC_LATENCY_ALLOWANCE_DC_2 0x2f0
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#define MC_LATENCY_ALLOWANCE_DCB_0 0x2f4
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#define MC_LATENCY_ALLOWANCE_DCB_1 0x2f8
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#define MC_LATENCY_ALLOWANCE_DCB_2 0x2fc
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#define MC_LATENCY_ALLOWANCE_HC_0 0x310
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#define MC_LATENCY_ALLOWANCE_HC_1 0x314
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#define MC_LATENCY_ALLOWANCE_HDA_0 0x318
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#define MC_LATENCY_ALLOWANCE_MPCORE_0 0x320
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#define MC_LATENCY_ALLOWANCE_MPCORELP_0 0x324
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#define MC_LATENCY_ALLOWANCE_MSENC_0 0x328
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#define MC_LATENCY_ALLOWANCE_PPCS_0 0x344
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#define MC_LATENCY_ALLOWANCE_PPCS_1 0x348
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#define MC_LATENCY_ALLOWANCE_PTC_0 0x34c
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#define MC_LATENCY_ALLOWANCE_SATA_0 0x350
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#define MC_LATENCY_ALLOWANCE_VDE_0 0x354
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#define MC_LATENCY_ALLOWANCE_VDE_1 0x358
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#define MC_LATENCY_ALLOWANCE_VDE_2 0x35c
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#define MC_LATENCY_ALLOWANCE_VDE_3 0x360
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#define MC_LATENCY_ALLOWANCE_ISP2_0 0x370
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#define MC_LATENCY_ALLOWANCE_ISP2_1 0x374
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#define MC_LATENCY_ALLOWANCE_XUSB_0 0x37c
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#define MC_LATENCY_ALLOWANCE_XUSB_1 0x380
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#define MC_LATENCY_ALLOWANCE_ISP2B_0 0x384
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#define MC_LATENCY_ALLOWANCE_ISP2B_1 0x388
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#define MC_LATENCY_ALLOWANCE_TSEC_0 0x390
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#define MC_LATENCY_ALLOWANCE_VIC_0 0x394
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#define MC_LATENCY_ALLOWANCE_VI2_0 0x398
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#define MC_LATENCY_ALLOWANCE_A9AVP_0 0x3a4
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#define MC_LATENCY_ALLOWANCE_GPU_0 0x3ac
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#define MC_LATENCY_ALLOWANCE_SDMMCA_0 0x3b8
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#define MC_LATENCY_ALLOWANCE_SDMMCAA_0 0x3bc
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#define MC_LATENCY_ALLOWANCE_SDMMC_0 0x3c0
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#define MC_LATENCY_ALLOWANCE_SDMMCAB_0 0x3c4
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#define MC_LATENCY_ALLOWANCE_DC_3 0x3c8
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/* NOTE: this must match the # of MC_LATENCY_XXX above */
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#define T12X_MC_LATENCY_ALLOWANCE_NUM_REGS 38
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#define MC_VIDEO_PROTECT_VPR_OVERRIDE 0x418
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#define MC_MLL_MPCORER_PTSA_RATE 0x44c
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#define MC_VIDEO_PROTECT_BOM 0x648
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#define MC_VIDEO_PROTECT_SIZE_MB 0x64c
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#define MC_VIDEO_PROTECT_REG_CTRL 0x650
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#define MC_SEC_CARVEOUT_BOM 0x670
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#define MC_SEC_CARVEOUT_SIZE_MB 0x674
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#define MC_SEC_CARVEOUT_REG_CTRL 0x678
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#define MC_PTSA_GRANT_DECREMENT 0x960
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#define MC_RESERVED_RSV 0x3fc
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#define MC_RESERVED_RSV_1 0x958
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#define MC_EMEM_ARB_OUTSTANDING_REQ_RING3 0x66c
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#define MC_EMEM_ARB_OVERRIDE_1 0x968
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#endif
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