97 lines
2.8 KiB
C
97 lines
2.8 KiB
C
/*
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* arch/arm/mach-tegra/tegra_emc.h
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*
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* Copyright (c) 2013-2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*
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*/
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#ifndef _MACH_TEGRA_TEGRA_EMC_H
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#define _MACH_TEGRA_TEGRA_EMC_H
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#define TEGRA_EMC_ISO_USE_CASES_MAX_NUM 8
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extern u8 tegra_emc_bw_efficiency;
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extern u8 tegra_emc_iso_share;
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enum {
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DRAM_OVER_TEMP_NONE = 0,
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DRAM_OVER_TEMP_REFRESH_X2,
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DRAM_OVER_TEMP_REFRESH_X4,
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DRAM_OVER_TEMP_THROTTLE, /* 4x Refresh + derating. */
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};
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enum emc_user_id {
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EMC_USER_DC1 = 0,
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EMC_USER_DC2,
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EMC_USER_VI,
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EMC_USER_MSENC,
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EMC_USER_2D,
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EMC_USER_3D,
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EMC_USER_BB,
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EMC_USER_VDE,
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EMC_USER_VI2,
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EMC_USER_ISP1,
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EMC_USER_ISP2,
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EMC_USER_NVDEC,
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EMC_USER_NVJPG,
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EMC_USER_NUM,
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};
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struct emc_iso_usage {
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u32 emc_usage_flags;
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u8 iso_usage_share;
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u8 (*iso_share_calculator)(unsigned long iso_bw);
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};
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struct tegra_emc_dvfs_table_ops {
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u32 (*get_dvfs_clk_change_latency_nsec)(unsigned long emc_freq_khz);
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};
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struct clk;
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struct dentry;
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void tegra_emc_timer_mr4_start(void);
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void tegra_emc_timer_mr4_stop(void);
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void tegra_emc_timer_training_start(void);
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void tegra_emc_timer_training_stop(void);
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void tegra_emc_iso_usage_table_init(struct emc_iso_usage *table, int size);
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int tegra_emc_iso_usage_debugfs_init(struct dentry *emc_debugfs_root);
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int tegra_emc_timers_init(struct dentry *parent);
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void tegra_emc_dvfs_table_ops_init(
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struct tegra_emc_dvfs_table_ops *dvfs_table_ops_to_copy);
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unsigned long tegra_emc_apply_efficiency(unsigned long total_bw,
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unsigned long iso_bw, unsigned long max_rate, u32 usage_flags,
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unsigned long *iso_bw_min);
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void tegra_emc_dram_type_init(struct clk *c);
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int tegra_emc_get_dram_type(void);
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int tegra_emc_get_dram_temperature(void);
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int tegra_emc_set_over_temp_state(unsigned long state);
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void tegra_emc_mr4_set_freq_thresh(unsigned long thresh);
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void tegra_emc_mr4_freq_check(unsigned long freq);
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u32 emc_do_periodic_compensation(void);
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long tegra_emc_round_rate(unsigned long rate);
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long tegra_emc_round_rate_updown(unsigned long rate, bool up);
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struct clk *tegra_emc_predict_parent(unsigned long rate, u32 *div_value);
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void tegra_emc_timing_invalidate(void);
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void tegra_mc_divider_update(struct clk *emc);
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u32 tegra_get_dvfs_clk_change_latency_nsec(unsigned long emc_freq_khz);
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#endif
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