96 lines
2.5 KiB
C
96 lines
2.5 KiB
C
/*
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* tc358840.h - Toshiba UH2C/D HDMI-CSI bridge driver
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*
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* Copyright (c) 2015, Armin Weiss <weii@zhaw.ch>
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* Copyright (c) 2016 - 2018, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _TC358840_
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#define _TC358840_
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enum tc358840_csi_port {
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CSI_TX_NONE = 0,
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CSI_TX_0,
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CSI_TX_1,
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CSI_TX_BOTH
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};
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enum tc358840_clock_mode {
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CSI_NON_CONT_CLK = 0,
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CSI_CONT_CLK
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};
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enum tc358840_ddc5v_delays {
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DDC5V_DELAY_0MS,
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DDC5V_DELAY_50MS,
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DDC5V_DELAY_100MS,
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DDC5V_DELAY_200MS,
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DDC5V_DELAY_MAX = DDC5V_DELAY_200MS,
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};
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struct tc358840_platform_data {
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/* GPIOs */
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int reset_gpio; /* Pin K8 */
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#ifdef CONFIG_V4L2_FWNODE
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struct v4l2_fwnode_endpoint endpoint;
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#else
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struct v4l2_of_endpoint endpoint;
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#endif
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/* System clock connected to REFCLK (pin K9) */
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u32 refclk_hz; /* 40 - 50 MHz */
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/* DDC +5V debounce delay */
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enum tc358840_ddc5v_delays ddc5v_delay;
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/* HDCP */
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/* TODO: Not yet implemented */
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bool enable_hdcp;
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/* CSI Output */
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enum tc358840_csi_port csi_port;
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/* CSI */
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/* The values in brackets can serve as a starting point. */
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u32 lineinitcnt; /* (0x00000FA0) */
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u32 lptxtimecnt; /* (0x00000004) */
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u32 tclk_headercnt; /* (0x00180203) */
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u32 tclk_trailcnt; /* (0x00040005) */
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u32 ths_headercnt; /* (0x000D0004) */
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u32 twakeup; /* (0x00003E80) */
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u32 tclk_postcnt; /* (0x0000000A) */
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u32 ths_trailcnt; /* (0x00080006) */
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u32 hstxvregcnt; /* (0x00000020) */
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/* PLL */
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/* Bps pr lane is (refclk_hz / pll_prd) * pll_fbd */
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u16 pll_prd; /* PRD from Macro + 1 (0x0A) */
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u16 pll_fbd; /* FBD from Macro + 1 (0x7D) */
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};
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/* custom controls */
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#define TEGRA_CAMERA_CID_USER_TC358840_BASE (TEGRA_CAMERA_CID_BASE + 0x1000)
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/* Audio sample rate in Hz */
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#define TC358840_CID_AUDIO_SAMPLING_RATE \
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(TEGRA_CAMERA_CID_USER_TC358840_BASE + 1)
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/* Audio present status */
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#define TC358840_CID_AUDIO_PRESENT \
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(TEGRA_CAMERA_CID_USER_TC358840_BASE + 2)
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/* Splitter width */
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#define TC358840_CID_SPLITTER_WIDTH \
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(TEGRA_CAMERA_CID_USER_TC358840_BASE + 3)
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#endif /* _TC358840_ */
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