101 lines
2.7 KiB
C
101 lines
2.7 KiB
C
/*
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* Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _ABI_BPMP_T210_ABI_H_
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#define _ABI_BPMP_T210_ABI_H_
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/**
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* This header file documents the T210 only specific Application
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* Binary Interface (ABI) of BPMP processor complex and CCPLEX
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*
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* Table of Contents
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* 1. Message payloads
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* 3.2 Do idle (MRQ_DO_IDLE)
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* 3.3 Tolerate idle (MRQ_TOLERATE_IDLE)
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* 3.6 Switch cluster (MRQ_SWITCH_CLUSTER)
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* 3.12 SCx enable (MRQ_SCX_ENABLE)
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* 3.16 SCLK skip set rate (MRQ_SCLK_SKIP_SET_RATE)
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* 3.17 Enable suspend (MRQ_ENABLE_SUSPEND)
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* 3.18 PASR mask (MRQ_PASR_MASK)
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* 3.32 EMC DVFS table (MRQ_EMC_DVFS_TABLE)
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*/
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#define MRQ_DO_IDLE 2
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#define MRQ_TOLERATE_IDLE 3
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#define MRQ_SWITCH_CLUSTER 6
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#define MRQ_CPUIDLE_USAGE 10
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#define MRQ_SCX_ENABLE 12
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#define MRQ_CPU_FROZEN 13
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#define MRQ_SCLK_SKIP_SET_RATE 16
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#define MRQ_ENABLE_SUSPEND 17
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#define MRQ_PASR_MASK 18
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#define MRQ_EMC_DVFS_TABLE 32
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/* Tegra PM states as known to BPMP */
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#define TEGRA_PM_CC0 8
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#define TEGRA_PM_CC1 9
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#define TEGRA_PM_CC4 12
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#define TEGRA_PM_CC6 14
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#define TEGRA_PM_CC7 15
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#define TEGRA_PM_SC1 17
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#define TEGRA_PM_SC2 18
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#define TEGRA_PM_SC3 19
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#define TEGRA_PM_SC4 20
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#define TEGRA_PM_SC7 23
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#ifndef __ABI_PACKED
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#define __ABI_PACKED __attribute__((packed))
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#endif
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/**
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* @ingroup MRQ_Codes
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* @def MRQ_EMC_DVFS_TABLE
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* @brief query frequency dependent EMC DVFS table
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*
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* * Platforms: T210 rev b
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* * Initiators: CCPLEX
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* * Targets: BPMP
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* * Request Payload: N/A
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* * Response Payload: @ref mrq_emc_dvfs_table_response
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* @addtogroup EMC
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* @{
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*/
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/**
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* @brief used by @ref mrq_emc_dvfs_table_response
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*/
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struct emc_dvfs_table {
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/** @brief EMC frequency in kHz */
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uint32_t freq;
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/** @brief EMC voltage in millivolts */
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uint32_t mv;
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} __ABI_PACKED;
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#define EMC_DVFS_TABLE_MAX_SIZE 14
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/**
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* @brief response to #MRQ_EMC_DVFS_TABLE
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*/
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struct mrq_emc_dvfs_table_response {
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/** @brief the number valid entries in #pairs */
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uint32_t num_pairs;
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/** @brief EMC <frequency, voltage> information */
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struct emc_dvfs_table pairs[EMC_DVFS_TABLE_MAX_SIZE];
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} __ABI_PACKED;
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/** @} */
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#endif
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