635 lines
20 KiB
C
635 lines
20 KiB
C
/*
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* tegra-nvlink-uapi.h:
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* This header contains the structures and variables needed for
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* the NVLINK userspace APIs exported by the Tegra NVLINK endpoint driver.
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*
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* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef TEGRA_NVLINK_UAPI_H
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#define TEGRA_NVLINK_UAPI_H
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#include <linux/ioctl.h>
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#include <linux/types.h>
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#if defined(__KERNEL__)
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#include <linux/bitops.h>
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#else
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#define __user
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#ifndef BIT
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#define BIT(b) (1UL << (b))
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#endif
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#endif
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/* TEGRA_CTRL_CMD_NVLINK_GET_NVLINK_CAPS */
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#define TEGRA_NVLINK_VERSION_10 0x00000001U
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#define TEGRA_NVLINK_VERSION_20 0x00000002U
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#define TEGRA_NVLINK_VERSION_22 0x00000004U
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#define TEGRA_CTRL_NVLINK_CAPS_NVLINK_VERSION_INVALID (0x00000000U)
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#define TEGRA_CTRL_NVLINK_CAPS_NVLINK_VERSION_1_0 (0x00000001U)
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#define TEGRA_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_0 (0x00000002U)
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#define TEGRA_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_2 (0x00000004U)
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#define TEGRA_CTRL_NVLINK_CAPS_NCI_VERSION_INVALID (0x00000000U)
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#define TEGRA_CTRL_NVLINK_CAPS_NCI_VERSION_1_0 (0x00000001U)
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#define TEGRA_CTRL_NVLINK_CAPS_NCI_VERSION_2_0 (0x00000002U)
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#define TEGRA_CTRL_NVLINK_CAPS_NCI_VERSION_2_2 (0x00000004U)
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#define TEGRA_CTRL_NVLINK_CAPS_SUPPORTED BIT(0U)
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#define TEGRA_CTRL_NVLINK_CAPS_P2P_SUPPORTED BIT(1U)
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#define TEGRA_CTRL_NVLINK_CAPS_SYSMEM_ACCESS BIT(2U)
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#define TEGRA_CTRL_NVLINK_CAPS_P2P_ATOMICS BIT(3U)
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#define TEGRA_CTRL_NVLINK_CAPS_SYSMEM_ATOMICS BIT(4U)
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#define TEGRA_CTRL_NVLINK_CAPS_PEX_TUNNELING BIT(5U)
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#define TEGRA_CTRL_NVLINK_CAPS_SLI_BRIDGE BIT(6U)
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#define TEGRA_CTRL_NVLINK_CAPS_SLI_BRIDGE_SENSABLE BIT(7U)
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#define TEGRA_CTRL_NVLINK_CAPS_POWER_STATE_L0 BIT(8U)
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#define TEGRA_CTRL_NVLINK_CAPS_POWER_STATE_L1 BIT(9U)
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#define TEGRA_CTRL_NVLINK_CAPS_POWER_STATE_L2 BIT(10U)
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#define TEGRA_CTRL_NVLINK_CAPS_POWER_STATE_L3 BIT(11U)
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#define TEGRA_CTRL_NVLINK_CAPS_VALID BIT(12U)
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struct tegra_nvlink_caps {
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__u16 nvlink_caps;
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__u8 lowest_nvlink_version;
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__u8 highest_nvlink_version;
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__u8 lowest_nci_version;
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__u8 highest_nci_version;
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__u32 discovered_link_mask;
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__u32 enabled_link_mask;
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};
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/* TEGRA_CTRL_CMD_NVLINK_GET_NVLINK_STATUS */
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/* NVLink link states */
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#define TEGRA_CTRL_NVLINK_STATUS_LINK_STATE_INIT (0x00000000U)
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#define TEGRA_CTRL_NVLINK_STATUS_LINK_STATE_HWCFG (0x00000001U)
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#define TEGRA_CTRL_NVLINK_STATUS_LINK_STATE_SWCFG (0x00000002U)
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#define TEGRA_CTRL_NVLINK_STATUS_LINK_STATE_ACTIVE (0x00000003U)
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#define TEGRA_CTRL_NVLINK_STATUS_LINK_STATE_FAULT (0x00000004U)
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#define TEGRA_CTRL_NVLINK_STATUS_LINK_STATE_RECOVERY (0x00000006U)
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#define TEGRA_CTRL_NVLINK_STATUS_LINK_STATE_INVALID (0xFFFFFFFFU)
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/* NVLink Tx sublink states */
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#define TEGRA_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_HIGH_SPEED_1 (0x00000000U)
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#define TEGRA_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_SINGLE_LANE (0x00000004U)
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#define TEGRA_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_TRAINING (0x00000005U)
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#define TEGRA_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_SAFE_MODE (0x00000006U)
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#define TEGRA_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_OFF (0x00000007U)
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#define TEGRA_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_INVALID (0x000000FFU)
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/* NVLink Rx sublink states */
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#define TEGRA_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_HIGH_SPEED_1 (0x00000000U)
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#define TEGRA_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_SINGLE_LANE (0x00000004U)
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#define TEGRA_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_TRAINING (0x00000005U)
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#define TEGRA_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_SAFE_MODE (0x00000006U)
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#define TEGRA_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_OFF (0x00000007U)
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#define TEGRA_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_INVALID (0x000000FFU)
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#define TEGRA_CTRL_NVLINK_STATUS_PHY_NVHS (0x00000001U)
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#define TEGRA_CTRL_NVLINK_STATUS_PHY_GRS (0x00000002U)
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#define TEGRA_CTRL_NVLINK_STATUS_PHY_INVALID (0x000000FFU)
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/* Version information */
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#define TEGRA_CTRL_NVLINK_STATUS_NVLINK_VERSION_1_0 (0x00000001U)
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#define TEGRA_CTRL_NVLINK_STATUS_NVLINK_VERSION_2_0 (0x00000002U)
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#define TEGRA_CTRL_NVLINK_STATUS_NVLINK_VERSION_2_2 (0x00000004U)
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#define TEGRA_CTRL_NVLINK_STATUS_NVLINK_VERSION_INVALID (0x000000FFU)
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#define TEGRA_CTRL_NVLINK_STATUS_NCI_VERSION_1_0 (0x00000001U)
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#define TEGRA_CTRL_NVLINK_STATUS_NCI_VERSION_2_0 (0x00000002U)
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#define TEGRA_CTRL_NVLINK_STATUS_NCI_VERSION_2_2 (0x00000004U)
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#define TEGRA_CTRL_NVLINK_STATUS_NCI_VERSION_INVALID (0x000000FFU)
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#define TEGRA_CTRL_NVLINK_STATUS_NVHS_VERSION_1_0 (0x00000001U)
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#define TEGRA_CTRL_NVLINK_STATUS_NVHS_VERSION_INVALID (0x000000FFU)
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#define TEGRA_CTRL_NVLINK_STATUS_GRS_VERSION_1_0 (0x00000001U)
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#define TEGRA_CTRL_NVLINK_STATUS_GRS_VERSION_INVALID (0x000000FFU)
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/* Connection properties */
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#define TEGRA_CTRL_NVLINK_STATUS_CONNECTED_TRUE (0x00000001U)
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#define TEGRA_CTRL_NVLINK_STATUS_CONNECTED_FALSE (0x00000000U)
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#define TEGRA_CTRL_NVLINK_STATUS_LOOP_PROPERTY_LOOPBACK (0x00000001U)
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#define TEGRA_CTRL_NVLINK_STATUS_LOOP_PROPERTY_LOOPOUT (0x00000002U)
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#define TEGRA_CTRL_NVLINK_STATUS_LOOP_PROPERTY_NONE (0x00000000U)
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#define TEGRA_CTRL_NVLINK_STATUS_REMOTE_LINK_NUMBER_INVALID (0x000000FFU)
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/* NVLink REFCLK types */
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#define TEGRA_CTRL_NVLINK_REFCLK_TYPE_INVALID (0x00U)
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#define TEGRA_CTRL_NVLINK_REFCLK_TYPE_NVHS (0x01U)
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#define TEGRA_CTRL_NVLINK_REFCLK_TYPE_PEX (0x02U)
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#define TEGRA_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_NONE (0x00000000U)
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#define TEGRA_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_PCI (0x00000001U)
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#define TEGRA_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_UUID (0x00000002U)
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#define TEGRA_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_EBRIDGE (0x00000000U)
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#define TEGRA_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NPU (0x00000001U)
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#define TEGRA_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_GPU (0x00000002U)
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#define TEGRA_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_SWITCH (0x00000003U)
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#define TEGRA_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_TEGRA (0x00000004U)
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#define TEGRA_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NONE (0x000000FFU)
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#define TEGRA_CTRL_NVLINK_DEVICE_INFO_DEVICE_UUID_INVALID (0xFFFFFFFFU)
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struct tegra_nvlink_device_info {
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/* ID Flags */
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__u32 device_id_flags;
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/* PCI Information */
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__u16 domain;
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__u16 bus;
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__u16 device;
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__u16 function;
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__u32 pci_device_id;
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/* Device Type */
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__u64 device_type;
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/* Device UUID */
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__u8 device_uuid[16];
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};
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struct tegra_nvlink_link_status_info {
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/* Top level capablilites */
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__u16 caps;
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__u8 phy_type;
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__u8 sublink_width;
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/* Link and sublink states */
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__u32 link_state;
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__u8 rx_sublink_status;
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__u8 tx_sublink_status;
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/* Indicates that lane reveral is in effect on this link */
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bool bLane_reversal;
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__u8 nvlink_version;
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__u8 nci_version;
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__u8 phy_version;
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/* Clock information */
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__u32 nvlink_link_clockKHz;
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__u32 nvlink_common_clock_speedKHz;
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__u32 nvlink_ref_clk_speedKHz;
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__u8 nvlink_ref_clk_type;
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__u32 nvlink_link_clockMhz;
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__u32 nvlink_common_clock_speedMhz;
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__u32 nvlink_ref_clk_speedMhz;
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/* Connection information */
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bool connected;
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__u8 loop_property;
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__u8 remote_device_link_number;
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__u8 local_device_link_number;
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struct tegra_nvlink_device_info remote_device_info;
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struct tegra_nvlink_device_info local_device_info;
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};
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struct tegra_nvlink_status {
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__u32 enabled_link_mask;
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struct tegra_nvlink_link_status_info link_info;
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};
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/* TEGRA_CTRL_CMD_NVLINK_CLEAR_COUNTERS */
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/* These are the bitmask definitions for different counter types */
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#define TEGRA_CTRL_NVLINK_COUNTER_INVALID 0x00000000U
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#define TEGRA_CTRL_NVLINK_COUNTER_TL_TX0 0x00000001U
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#define TEGRA_CTRL_NVLINK_COUNTER_TL_TX1 0x00000002U
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#define TEGRA_CTRL_NVLINK_COUNTER_TL_RX0 0x00000004U
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#define TEGRA_CTRL_NVLINK_COUNTER_TL_RX1 0x00000008U
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#define TEGRA_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_FLIT 0x00010000U
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#define TEGRA_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L(i) (1U << (i + 17U))
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#define TEGRA_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_SIZE 8U
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#define TEGRA_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L0 0x00020000U
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#define TEGRA_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L1 0x00040000U
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#define TEGRA_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L2 0x00080000U
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#define TEGRA_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L3 0x00100000U
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#define TEGRA_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L4 0x00200000U
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#define TEGRA_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L5 0x00400000U
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#define TEGRA_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L6 0x00800000U
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#define TEGRA_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L7 0x01000000U
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#define TEGRA_CTRL_NVLINK_COUNTER_DL_TX_ERR_REPLAY 0x02000000U
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#define TEGRA_CTRL_NVLINK_COUNTER_DL_TX_ERR_RECOVERY 0x04000000U
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#define TEGRA_CTRL_NVLINK_COUNTER_MAX_TYPES 32U
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/*
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* Return index of the bit that is set in 'n'. This assumes there is only
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* one such set bit in 'n'. Even if multiple bits are set,
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* result is in range of 0-31.
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*/
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#define TEGRA_BIT_IDX_32(n) \
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((((n) & 0xFFFF0000U) ? 0x10U : 0U) | \
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(((n) & 0xFF00FF00U) ? 0x08U : 0U) | \
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(((n) & 0xF0F0F0F0U) ? 0x04U : 0U) | \
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(((n) & 0xCCCCCCCCU) ? 0x02U : 0U) | \
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(((n) & 0xAAAAAAAAU) ? 0x01U : 0U))
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struct tegra_nvlink_clear_counters {
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__u32 link_mask;
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__u32 counter_mask;
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};
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/* TEGRA_CTRL_CMD_NVLINK_GET_COUNTERS */
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#define tegra_nvlink_counter(x) \
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TEGRA_BIT_IDX_32(TEGRA_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L(x))
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struct tegra_nvlink_get_counters {
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__u8 link_id;
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__u32 counter_mask;
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bool bTx0_tl_counter_overflow;
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bool bTx1_tl_counter_overflow;
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bool bRx0_tl_counter_overflow;
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bool bRx1_tl_counter_overflow;
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__u64 nvlink_counters[TEGRA_CTRL_NVLINK_COUNTER_MAX_TYPES];
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};
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/* TEGRA_CTRL_CMD_NVLINK_GET_ERR_INFO */
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struct tegra_nvlink_err_info {
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__u32 tl_err_log;
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__u32 tl_intr_en;
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__u32 tlc_tx_err_status0;
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__u32 tlc_rx_err_status0;
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__u32 tlc_rx_err_status1;
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__u32 tlc_tx_err_log_en0;
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__u32 tlc_rx_err_log_en0;
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__u32 tlc_rx_err_log_en1;
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__u32 mif_tx_err_status0;
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__u32 mif_rx_err_status0;
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__u32 dl_speed_status_tx;
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__u32 dl_speed_status_rx;
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bool bExcess_error_dl;
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};
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struct tegra_nvlink_get_err_info {
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__u32 link_mask;
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struct tegra_nvlink_err_info link_err_info;
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};
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/* TEGRA_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES */
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struct tegra_nvlink_get_error_recoveries {
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__u32 link_mask;
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__u32 num_recoveries;
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};
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/* TEGRA_CTRL_CMD_NVLINK_SETUP_EOM */
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struct tegra_nvlink_setup_eom {
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__u8 link_id;
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__u32 params;
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};
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/* TEGRA_CTRL_NVLINK_TRAIN_INTRANODE_CONN */
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enum tegra_ctrl_link_mode {
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TEGRA_CTRL_NVLINK_LINK_OFF,
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TEGRA_CTRL_NVLINK_LINK_HS,
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TEGRA_CTRL_NVLINK_LINK_SAFE,
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TEGRA_CTRL_NVLINK_LINK_FAULT,
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TEGRA_CTRL_NVLINK_LINK_RCVY_AC,
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TEGRA_CTRL_NVLINK_LINK_RCVY_SW,
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TEGRA_CTRL_NVLINK_LINK_RCVY_RX,
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TEGRA_CTRL_NVLINK_LINK_DETECT,
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TEGRA_CTRL_NVLINK_LINK_RESET,
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TEGRA_CTRL_NVLINK_LINK_ENABLE_PM,
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TEGRA_CTRL_NVLINK_LINK_DISABLE_PM,
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TEGRA_CTRL_NVLINK_LINK_DISABLE_ERR_DETECT,
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TEGRA_CTRL_NVLINK_LINK_LANE_DISABLE,
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TEGRA_CTRL_NVLINK_LINK_LANE_SHUTDOWN
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};
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enum tegra_ctrl_tx_mode {
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TEGRA_CTRL_NVLINK_TX_HS,
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TEGRA_CTRL_NVLINK_TX_ENABLE_PM,
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TEGRA_CTRL_NVLINK_TX_DISABLE_PM,
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TEGRA_CTRL_NVLINK_TX_SINGLE_LANE,
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TEGRA_CTRL_NVLINK_TX_SAFE,
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TEGRA_CTRL_NVLINK_TX_OFF,
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TEGRA_CTRL_NVLINK_TX_COMMON,
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TEGRA_CTRL_NVLINK_TX_COMMON_DISABLE,
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TEGRA_CTRL_NVLINK_TX_DATA_READY,
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TEGRA_CTRL_NVLINK_TX_PRBS_EN,
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};
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enum tegra_ctrl_rx_mode {
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TEGRA_CTRL_NVLINK_RX_HS,
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TEGRA_CTRL_NVLINK_RX_ENABLE_PM,
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TEGRA_CTRL_NVLINK_RX_DISABLE_PM,
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TEGRA_CTRL_NVLINK_RX_SINGLE_LANE,
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TEGRA_CTRL_NVLINK_RX_SAFE,
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TEGRA_CTRL_NVLINK_RX_OFF,
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TEGRA_CTRL_NVLINK_RX_RXCAL,
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};
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struct tegra_nvlink_pci_dev_info {
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__u16 domain;
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__u8 bus;
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__u8 device;
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__u8 function;
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};
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struct tegra_nvlink_endpoint {
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__u16 node_id;
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__u32 link_index;
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struct tegra_nvlink_pci_dev_info pci_info;
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};
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/* link and sublink state of an nvlink endpoint */
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struct tegra_nvlink_link_state {
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__u64 link_mode;
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__u64 tx_sublink_mode;
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__u64 rx_sublink_mode;
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};
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enum tegra_nvlink_conn_train_type {
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tegra_nvlink_train_conn_off_to_swcfg = 0U,
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tegra_nvlink_train_conn_swcfg_to_active,
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tegra_nvlink_train_conn_to_off,
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tegra_nvlink_train_conn_active_to_swcfg,
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tegra_nvlink_train_conn_swcfg_to_off,
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};
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struct tegra_nvlink_train_intranode_conn {
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/* input fields */
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enum tegra_nvlink_conn_train_type train_to;
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struct tegra_nvlink_endpoint src_end_point;
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struct tegra_nvlink_endpoint dst_end_point;
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/* output fields */
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int status;
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struct tegra_nvlink_link_state src_end_state;
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struct tegra_nvlink_link_state dst_end_state;
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};
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/* TEGRA_CTRL_CMD_NVLINK_GET_LP_COUNTERS */
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#define TEGRA_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_NVHS 0U
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#define TEGRA_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_EIGHTH 1U
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#define TEGRA_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_OTHER 2U
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#define TEGRA_CTRL_NVLINK_GET_LP_COUNTERS_NUM_TX_LP_ENTER 3U
|
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#define TEGRA_CTRL_NVLINK_GET_LP_COUNTERS_NUM_TX_LP_EXIT 4U
|
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#define TEGRA_CTRL_NVLINK_GET_LP_COUNTERS_MAX_COUNTERS 5U
|
|
|
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struct tegra_nvlink_get_lp_counters {
|
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/* input field */
|
|
__u32 link_id;
|
|
/* input, output field */
|
|
__u32 counter_valid_mask;
|
|
/* output field */
|
|
__u32 counter_values[TEGRA_CTRL_NVLINK_GET_LP_COUNTERS_MAX_COUNTERS];
|
|
};
|
|
|
|
/* TEGRA_CTRL_CMD_NVLINK_CLEAR_LP_COUNTERS */
|
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struct tegra_nvlink_clear_lp_counters {
|
|
__u32 link_id;
|
|
};
|
|
|
|
/* TEGRA_CTRL_CMD_NVLINK_ENABLE_DEVICE_INTERRUPTS */
|
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struct tegra_nvlink_enable_device_interrupts {
|
|
__u32 link_mask;
|
|
};
|
|
|
|
/* TEGRA_CTRL_CMD_NVLINK_SERVICE_DEVICE */
|
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struct tegra_nvlink_service_device {
|
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__u32 link_mask;
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__u32 retrain_from_safe_mask;
|
|
};
|
|
|
|
/* TEGRA_CTRL_CMD_NVLINK_DISABLE_DEVICE_INTERRUPTS */
|
|
struct tegra_nvlink_disable_device_interrupts {
|
|
__u32 link_mask;
|
|
};
|
|
|
|
/* TEGRA_CTRL_CMD_NVLINK_INJECT_ERR */
|
|
struct tegra_nvlink_inject_err {
|
|
__u32 link_mask;
|
|
bool is_fatal_error;
|
|
};
|
|
|
|
/* TEGRA_CTRL_CMD_NVLINK_SET_LINK_MODE */
|
|
struct tegra_nvlink_set_link_mode {
|
|
__u32 link_mask;
|
|
enum tegra_ctrl_link_mode link_mode;
|
|
};
|
|
|
|
/* TEGRA_CTRL_CMD_NVLINK_GET_LINK_MODE */
|
|
struct tegra_nvlink_get_link_mode {
|
|
__u32 link_mask;
|
|
enum tegra_ctrl_link_mode link_mode;
|
|
};
|
|
|
|
/* TEGRA_CTRL_CMD_NVLINK_SET_TX_MODE */
|
|
struct tegra_nvlink_set_tx_mode {
|
|
__u32 link_mask;
|
|
enum tegra_ctrl_tx_mode tx_mode;
|
|
};
|
|
|
|
/* TEGRA_CTRL_CMD_NVLINK_GET_TX_MODE */
|
|
struct tegra_nvlink_get_tx_mode {
|
|
__u32 link_mask;
|
|
enum tegra_ctrl_tx_mode tx_mode;
|
|
};
|
|
|
|
/* TEGRA_CTRL_CMD_NVLINK_SET_RX_MODE */
|
|
struct tegra_nvlink_set_rx_mode {
|
|
__u32 link_mask;
|
|
enum tegra_ctrl_rx_mode rx_mode;
|
|
};
|
|
|
|
/* TEGRA_CTRL_CMD_NVLINK_GET_RX_MODE */
|
|
struct tegra_nvlink_get_rx_mode {
|
|
__u32 link_mask;
|
|
enum tegra_ctrl_rx_mode rx_mode;
|
|
};
|
|
|
|
/* TEGRA_CTRL_CMD_NVLINK_WRITE_DISCOVERY_TOKEN */
|
|
struct tegra_nvlink_write_discovery_token {
|
|
__u32 link_mask;
|
|
__u64 token;
|
|
};
|
|
|
|
/* TEGRA_CTRL_CMD_NVLINK_READ_DISCOVERY_TOKEN */
|
|
struct tegra_nvlink_read_discovery_token {
|
|
__u32 link_mask;
|
|
__u64 token;
|
|
};
|
|
|
|
/* TEGRA_CTRL_CMD_NVLINK_GET_LOCAL_PCI_INFO */
|
|
struct tegra_nvlink_get_local_pci_info {
|
|
struct tegra_nvlink_device_info local_endpt;
|
|
};
|
|
|
|
/* TEGRA_CTRL_CMD_NVLINK_SET_TOPOLOGY_INFO */
|
|
struct tegra_nvlink_set_topology_info {
|
|
struct tegra_nvlink_device_info remote_endpt;
|
|
__u32 local_link_id;
|
|
__u32 remote_link_id;
|
|
};
|
|
|
|
/* Enum to represent IOCTLs inside the Tegra NVLINK driver */
|
|
enum tnvlink_ioctl_num {
|
|
TNVLINK_IOCTL_GET_NVLINK_CAPS,
|
|
TNVLINK_IOCTL_GET_NVLINK_STATUS,
|
|
TNVLINK_IOCTL_CLEAR_COUNTERS,
|
|
TNVLINK_IOCTL_GET_COUNTERS,
|
|
TNVLINK_IOCTL_GET_ERR_INFO,
|
|
TNVLINK_IOCTL_GET_ERROR_RECOVERIES,
|
|
TNVLINK_IOCTL_SETUP_EOM,
|
|
TNVLINK_IOCTL_TRAIN_INTRANODE_CONN,
|
|
TNVLINK_IOCTL_GET_LP_COUNTERS,
|
|
TNVLINK_IOCTL_CLEAR_LP_COUNTERS,
|
|
TNVLINK_IOCTL_ENABLE_SHIM_DRIVER,
|
|
TNVLINK_IOCTL_ENABLE_DEVICE_INTERRUPTS,
|
|
TNVLINK_IOCTL_SERVICE_DEVICE,
|
|
TNVLINK_IOCTL_DISABLE_DEVICE_INTERRUPTS,
|
|
TNVLINK_IOCTL_INJECT_ERR,
|
|
TNVLINK_IOCTL_SET_LINK_MODE,
|
|
TNVLINK_IOCTL_GET_LINK_MODE,
|
|
TNVLINK_IOCTL_SET_TX_MODE,
|
|
TNVLINK_IOCTL_GET_TX_MODE,
|
|
TNVLINK_IOCTL_SET_RX_MODE,
|
|
TNVLINK_IOCTL_GET_RX_MODE,
|
|
TNVLINK_IOCTL_WRITE_DISCOVERY_TOKEN,
|
|
TNVLINK_IOCTL_READ_DISCOVERY_TOKEN,
|
|
TNVLINK_IOCTL_GET_LOCAL_PCI_INFO,
|
|
TNVLINK_IOCTL_SET_TOPOLOGY_INFO,
|
|
TNVLINK_IOCTL_INTERFACE_DISABLE,
|
|
TNVLINK_IOCTL_FINALIZE_SHUTDOWN,
|
|
TNVLINK_IOCTL_NUM_IOCTLS
|
|
};
|
|
|
|
/* TODO: choose a unique MAGIC number for ioctl implementation */
|
|
#define TEGRA_NVLINK_IOC_MAGIC 'T'
|
|
#define TEGRA_CTRL_CMD_NVLINK_GET_NVLINK_CAPS \
|
|
_IOR(TEGRA_NVLINK_IOC_MAGIC, \
|
|
TNVLINK_IOCTL_GET_NVLINK_CAPS, \
|
|
struct tegra_nvlink_caps)
|
|
#define TEGRA_CTRL_CMD_NVLINK_GET_NVLINK_STATUS \
|
|
_IOR(TEGRA_NVLINK_IOC_MAGIC, \
|
|
TNVLINK_IOCTL_GET_NVLINK_STATUS, \
|
|
struct tegra_nvlink_status)
|
|
#define TEGRA_CTRL_CMD_NVLINK_CLEAR_COUNTERS \
|
|
_IOW(TEGRA_NVLINK_IOC_MAGIC, \
|
|
TNVLINK_IOCTL_CLEAR_COUNTERS, \
|
|
struct tegra_nvlink_clear_counters)
|
|
#define TEGRA_CTRL_CMD_NVLINK_GET_COUNTERS \
|
|
_IOWR(TEGRA_NVLINK_IOC_MAGIC, \
|
|
TNVLINK_IOCTL_GET_COUNTERS, \
|
|
struct tegra_nvlink_get_counters)
|
|
#define TEGRA_CTRL_CMD_NVLINK_GET_ERR_INFO \
|
|
_IOR(TEGRA_NVLINK_IOC_MAGIC, \
|
|
TNVLINK_IOCTL_GET_ERR_INFO, \
|
|
struct tegra_nvlink_get_err_info)
|
|
#define TEGRA_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES \
|
|
_IOWR(TEGRA_NVLINK_IOC_MAGIC, \
|
|
TNVLINK_IOCTL_GET_ERROR_RECOVERIES, \
|
|
struct tegra_nvlink_get_error_recoveries)
|
|
#define TEGRA_CTRL_CMD_NVLINK_SETUP_EOM \
|
|
_IOW(TEGRA_NVLINK_IOC_MAGIC, \
|
|
TNVLINK_IOCTL_SETUP_EOM, \
|
|
struct tegra_nvlink_setup_eom)
|
|
#define TEGRA_CTRL_NVLINK_TRAIN_INTRANODE_CONN \
|
|
_IOWR(TEGRA_NVLINK_IOC_MAGIC, \
|
|
TNVLINK_IOCTL_TRAIN_INTRANODE_CONN, \
|
|
struct tegra_nvlink_train_intranode_conn)
|
|
#define TEGRA_CTRL_CMD_NVLINK_GET_LP_COUNTERS \
|
|
_IOWR(TEGRA_NVLINK_IOC_MAGIC, \
|
|
TNVLINK_IOCTL_GET_LP_COUNTERS, \
|
|
struct tegra_nvlink_get_lp_counters)
|
|
#define TEGRA_CTRL_CMD_NVLINK_CLEAR_LP_COUNTERS \
|
|
_IOW(TEGRA_NVLINK_IOC_MAGIC, \
|
|
TNVLINK_IOCTL_CLEAR_LP_COUNTERS, \
|
|
struct tegra_nvlink_clear_lp_counters)
|
|
#define TEGRA_CTRL_CMD_NVLINK_ENABLE_SHIM_DRIVER \
|
|
_IO(TEGRA_NVLINK_IOC_MAGIC, \
|
|
TNVLINK_IOCTL_ENABLE_SHIM_DRIVER)
|
|
#define TEGRA_CTRL_CMD_NVLINK_ENABLE_DEVICE_INTERRUPTS \
|
|
_IOW(TEGRA_NVLINK_IOC_MAGIC, \
|
|
TNVLINK_IOCTL_ENABLE_DEVICE_INTERRUPTS, \
|
|
struct tegra_nvlink_enable_device_interrupts)
|
|
#define TEGRA_CTRL_CMD_NVLINK_SERVICE_DEVICE \
|
|
_IOW(TEGRA_NVLINK_IOC_MAGIC, \
|
|
TNVLINK_IOCTL_SERVICE_DEVICE, \
|
|
struct tegra_nvlink_service_device)
|
|
#define TEGRA_CTRL_CMD_NVLINK_DISABLE_DEVICE_INTERRUPTS \
|
|
_IOW(TEGRA_NVLINK_IOC_MAGIC, \
|
|
TNVLINK_IOCTL_DISABLE_DEVICE_INTERRUPTS, \
|
|
struct tegra_nvlink_disable_device_interrupts)
|
|
#define TEGRA_CTRL_CMD_NVLINK_INJECT_ERR \
|
|
_IOW(TEGRA_NVLINK_IOC_MAGIC, \
|
|
TNVLINK_IOCTL_INJECT_ERR, \
|
|
struct tegra_nvlink_inject_err)
|
|
#define TEGRA_CTRL_CMD_NVLINK_SET_LINK_MODE \
|
|
_IOW(TEGRA_NVLINK_IOC_MAGIC, \
|
|
TNVLINK_IOCTL_SET_LINK_MODE, \
|
|
struct tegra_nvlink_set_link_mode)
|
|
#define TEGRA_CTRL_CMD_NVLINK_GET_LINK_MODE \
|
|
_IOWR(TEGRA_NVLINK_IOC_MAGIC, \
|
|
TNVLINK_IOCTL_GET_LINK_MODE, \
|
|
struct tegra_nvlink_get_link_mode)
|
|
#define TEGRA_CTRL_CMD_NVLINK_SET_TX_MODE \
|
|
_IOW(TEGRA_NVLINK_IOC_MAGIC, \
|
|
TNVLINK_IOCTL_SET_TX_MODE, \
|
|
struct tegra_nvlink_set_tx_mode)
|
|
#define TEGRA_CTRL_CMD_NVLINK_GET_TX_MODE \
|
|
_IOWR(TEGRA_NVLINK_IOC_MAGIC, \
|
|
TNVLINK_IOCTL_GET_TX_MODE, \
|
|
struct tegra_nvlink_get_tx_mode)
|
|
#define TEGRA_CTRL_CMD_NVLINK_SET_RX_MODE \
|
|
_IOW(TEGRA_NVLINK_IOC_MAGIC, \
|
|
TNVLINK_IOCTL_SET_RX_MODE, \
|
|
struct tegra_nvlink_set_rx_mode)
|
|
#define TEGRA_CTRL_CMD_NVLINK_GET_RX_MODE \
|
|
_IOWR(TEGRA_NVLINK_IOC_MAGIC, \
|
|
TNVLINK_IOCTL_GET_RX_MODE, \
|
|
struct tegra_nvlink_get_rx_mode)
|
|
#define TEGRA_CTRL_CMD_NVLINK_WRITE_DISCOVERY_TOKEN \
|
|
_IOW(TEGRA_NVLINK_IOC_MAGIC, \
|
|
TNVLINK_IOCTL_WRITE_DISCOVERY_TOKEN, \
|
|
struct tegra_nvlink_write_discovery_token)
|
|
#define TEGRA_CTRL_CMD_NVLINK_READ_DISCOVERY_TOKEN \
|
|
_IOWR(TEGRA_NVLINK_IOC_MAGIC, \
|
|
TNVLINK_IOCTL_READ_DISCOVERY_TOKEN, \
|
|
struct tegra_nvlink_read_discovery_token)
|
|
#define TEGRA_CTRL_CMD_NVLINK_GET_LOCAL_PCI_INFO \
|
|
_IOR(TEGRA_NVLINK_IOC_MAGIC, \
|
|
TNVLINK_IOCTL_GET_LOCAL_PCI_INFO, \
|
|
struct tegra_nvlink_get_local_pci_info)
|
|
#define TEGRA_CTRL_CMD_NVLINK_SET_TOPOLOGY_INFO \
|
|
_IOW(TEGRA_NVLINK_IOC_MAGIC, \
|
|
TNVLINK_IOCTL_SET_TOPOLOGY_INFO, \
|
|
struct tegra_nvlink_set_topology_info)
|
|
#define TEGRA_CTRL_CMD_NVLINK_INTERFACE_DISABLE \
|
|
_IO(TEGRA_NVLINK_IOC_MAGIC, \
|
|
TNVLINK_IOCTL_INTERFACE_DISABLE)
|
|
#define TEGRA_CTRL_CMD_NVLINK_FINALIZE_SHUTDOWN \
|
|
_IO(TEGRA_NVLINK_IOC_MAGIC, \
|
|
TNVLINK_IOCTL_FINALIZE_SHUTDOWN)
|
|
|
|
#endif /* TEGRA_NVLINK_UAPI_H */
|