81 lines
1.8 KiB
Plaintext
81 lines
1.8 KiB
Plaintext
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Device tree binding for NVIDIA Tegra186 DPAUX PINCTL
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====================================================
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The Tegra186 DPAUX PINCTL driver manages the DPAUX muxing
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This document defines the device-specific binding for chips after
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Tegra186 DPAUX PINCTL driver.
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This driver models dpaux pins to be muxed as either for I2C or DISPLAY.
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Refer to pinctrl-bindings.txt in this directory for generic information about
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pin controller device tree bindings.
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Required properties:
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--------------------
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- compatible: Must be "nvidia,tegra186-dpaux-padctl" or
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"nvidia,tegra186-dpaux1-padctl" or
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"nvidia,tegra194-dpaux-padctl" or
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"nvidia,tegra194-dpaux1-padctl" or
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"nvidia,tegra194-dpaux2-padctl" or
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"nvidia,tegra194-dpaux3-padctl".
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The pinmux configuration are applied statically at boot time.
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These configurations are defined as the child of the pinctrl state node.
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Each sub-node have following properties:
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Required properties:
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------------------
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- pins: List of pins. Valid values of pins properties for:
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t186: dpaux1-1, dpaux-0.
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t194: dpaux1-1, dpaux-0, dpaux2-2, dpaux3-3.
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- functions: List of functions: Valid values for function properties:
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t186: i2c, display.
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t194: i2c, display.
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Examples:
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========
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Board file extract:
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-------------------
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# DPAUX1 muxed to I2C mode
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i2c@3190000 {
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pinctrl-names = "default";
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pinctrl-0 = <&dpaux_default>;
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};
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host1x {
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...
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dpaux@15040000 {
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...
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compatible = "nvidia,tegra186-dpaux1-padctl";
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dpaux_default: pinmux@0 {
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dpaux1_pins {
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pins = "dpaux1-1";
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function = "i2c";
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};
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};
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...
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};
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# DPAUX0 muxed to I2C mode
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i2c@31b0000 {
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pinctrl-names = "default";
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pinctrl-0 = <&dpaux0_default>;
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};
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host1x {
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...
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dpaux@155c0000 {
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...
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compatible = "nvidia,tegra186-dpaux-padctl";
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dpaux0_default: pinmux@0 {
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dpaux0_pins {
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pins = "dpaux-0";
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function = "i2c";
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};
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};
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...
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};
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