55 lines
1.8 KiB
Plaintext
55 lines
1.8 KiB
Plaintext
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* ARM PrimeCells PL080 and PL081 and derivatives DMA controller
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Required properties:
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- compatible: "arm,pl080", "arm,primecell";
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"arm,pl081", "arm,primecell";
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- reg: Address range of the PL08x registers
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- interrupt: The PL08x interrupt number
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- clocks: The clock running the IP core clock
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- clock-names: Must contain "apb_pclk"
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- lli-bus-interface-ahb1: if AHB master 1 is eligible for fetching LLIs
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- lli-bus-interface-ahb2: if AHB master 2 is eligible for fetching LLIs
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- mem-bus-interface-ahb1: if AHB master 1 is eligible for fetching memory contents
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- mem-bus-interface-ahb2: if AHB master 2 is eligible for fetching memory contents
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- #dma-cells: must be <2>. First cell should contain the DMA request,
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second cell should contain either 1 or 2 depending on
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which AHB master that is used.
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Optional properties:
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- dma-channels: contains the total number of DMA channels supported by the DMAC
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- dma-requests: contains the total number of DMA requests supported by the DMAC
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- memcpy-burst-size: the size of the bursts for memcpy: 1, 4, 8, 16, 32
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64, 128 or 256 bytes are legal values
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- memcpy-bus-width: the bus width used for memcpy: 8, 16 or 32 are legal
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values
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Clients
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Required properties:
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- dmas: List of DMA controller phandle, request channel and AHB master id
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- dma-names: Names of the aforementioned requested channels
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Example:
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dmac0: dma-controller@10130000 {
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compatible = "arm,pl080", "arm,primecell";
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reg = <0x10130000 0x1000>;
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interrupt-parent = <&vica>;
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interrupts = <15>;
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clocks = <&hclkdma0>;
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clock-names = "apb_pclk";
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lli-bus-interface-ahb1;
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lli-bus-interface-ahb2;
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mem-bus-interface-ahb2;
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memcpy-burst-size = <256>;
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memcpy-bus-width = <32>;
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#dma-cells = <2>;
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};
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device@40008000 {
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...
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dmas = <&dmac0 0 2
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&dmac0 1 2>;
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dma-names = "tx", "rx";
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...
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};
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