59 lines
1.1 KiB
Plaintext
59 lines
1.1 KiB
Plaintext
|
Oxford Semiconductor OXNAS SoC Family RESET Controller
|
||
|
|
================================================
|
||
|
|
|
||
|
|
Please also refer to reset.txt in this directory for common reset
|
||
|
|
controller binding usage.
|
||
|
|
|
||
|
|
Required properties:
|
||
|
|
- compatible: Should be "oxsemi,ox810se-reset"
|
||
|
|
- #reset-cells: 1, see below
|
||
|
|
|
||
|
|
Parent node should have the following properties :
|
||
|
|
- compatible: Should be "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd"
|
||
|
|
|
||
|
|
For OX810SE, the indices are :
|
||
|
|
- 0 : ARM
|
||
|
|
- 1 : COPRO
|
||
|
|
- 2 : Reserved
|
||
|
|
- 3 : Reserved
|
||
|
|
- 4 : USBHS
|
||
|
|
- 5 : USBHSPHY
|
||
|
|
- 6 : MAC
|
||
|
|
- 7 : PCI
|
||
|
|
- 8 : DMA
|
||
|
|
- 9 : DPE
|
||
|
|
- 10 : DDR
|
||
|
|
- 11 : SATA
|
||
|
|
- 12 : SATA_LINK
|
||
|
|
- 13 : SATA_PHY
|
||
|
|
- 14 : Reserved
|
||
|
|
- 15 : NAND
|
||
|
|
- 16 : GPIO
|
||
|
|
- 17 : UART1
|
||
|
|
- 18 : UART2
|
||
|
|
- 19 : MISC
|
||
|
|
- 20 : I2S
|
||
|
|
- 21 : AHB_MON
|
||
|
|
- 22 : UART3
|
||
|
|
- 23 : UART4
|
||
|
|
- 24 : SGDMA
|
||
|
|
- 25 : Reserved
|
||
|
|
- 26 : Reserved
|
||
|
|
- 27 : Reserved
|
||
|
|
- 28 : Reserved
|
||
|
|
- 29 : Reserved
|
||
|
|
- 30 : Reserved
|
||
|
|
- 31 : BUS
|
||
|
|
|
||
|
|
example:
|
||
|
|
|
||
|
|
sys: sys-ctrl@000000 {
|
||
|
|
compatible = "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd";
|
||
|
|
reg = <0x000000 0x100000>;
|
||
|
|
|
||
|
|
reset: reset-controller {
|
||
|
|
compatible = "oxsemi,ox810se-reset";
|
||
|
|
#reset-cells = <1>;
|
||
|
|
};
|
||
|
|
};
|